xref: /optee_os/core/arch/arm/plat-stm32mp2/stm32mp_pm.h (revision 25675979615c01f3c6bfbe105f53e07e939dd739)
1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3  * Copyright (c) 2023-2024, STMicroelectronics
4  */
5 
6 #ifndef __STM32MP_PM_H__
7 #define __STM32MP_PM_H__
8 
9 /*
10  * The PSCI topology is defined in TF-A, with 5 power levels supported in
11  * the first parameter a0="Max power level powered down" of TF-A SPD hooks
12  *
13  * power level                (associated low power mode for a0)
14  * 0: CPU1 core#0 or core#1   (Stop1 or LP-Stop1)
15  * 1: D1 domain               (LPLV-Stop1)
16  * 2: LPLV D1                 (Stop2 or LP-Stop2)
17  * 3: D2                      (LPLV-Stop1)
18  * 4: LPLV D2                 (Standby)
19  * 5: MAX                     (PowerOff)
20  *
21  * these power level are only managed in power driver (PMIC), for pm function
22  * use the 2 associated parameters:
23  * - PM_HINT_CONTEXT_STATE : advertise driver to save all their context in DDR
24  *                           (self refresh) for standby mode
25  * - PM_HINT_CLOCK_STATE : advertise driver to interrupt operation when clock
26  *                         are stalled for the other low power modes
27  */
28 #define PM_CORE_LEVEL           0
29 #define PM_D1_LEVEL             1
30 #define PM_D1_LPLV_LEVEL        2
31 #define PM_D2_LEVEL             3
32 #define PM_D2_LPLV_LEVEL        4
33 #define PM_MAX_LEVEL            5
34 
35 #endif /*__STM32MP_PM_H__*/
36