xref: /optee_os/core/arch/arm/plat-stm32mp2/stm32mp_pm.h (revision 0d98c255fb4da7b0931ebe6c738e45d0ae78dfd7)
1*0d98c255SPatrick Delaunay /* SPDX-License-Identifier: BSD-2-Clause */
2*0d98c255SPatrick Delaunay /*
3*0d98c255SPatrick Delaunay  * Copyright (c) 2023-2024, STMicroelectronics
4*0d98c255SPatrick Delaunay  */
5*0d98c255SPatrick Delaunay 
6*0d98c255SPatrick Delaunay #ifndef __STM32MP_PM_H__
7*0d98c255SPatrick Delaunay #define __STM32MP_PM_H__
8*0d98c255SPatrick Delaunay 
9*0d98c255SPatrick Delaunay /*
10*0d98c255SPatrick Delaunay  * The PSCI topology is defined in TF-A, with 5 power levels supported in
11*0d98c255SPatrick Delaunay  * the first parameter a0="Max power level powered down" of TF-A SPD hooks
12*0d98c255SPatrick Delaunay  *
13*0d98c255SPatrick Delaunay  * power level                (associated low power mode for a0)
14*0d98c255SPatrick Delaunay  * 0: CPU1 core#0 or core#1   (Stop1 or LP-Stop1)
15*0d98c255SPatrick Delaunay  * 1: D1 domain               (LPLV-Stop1)
16*0d98c255SPatrick Delaunay  * 2: LPLV D1                 (Stop2 or LP-Stop2)
17*0d98c255SPatrick Delaunay  * 3: D2                      (LPLV-Stop1)
18*0d98c255SPatrick Delaunay  * 4: LPLV D2                 (Standby)
19*0d98c255SPatrick Delaunay  * 5: MAX                     (PowerOff)
20*0d98c255SPatrick Delaunay  *
21*0d98c255SPatrick Delaunay  * these power level are only managed in power driver (PMIC), for pm function
22*0d98c255SPatrick Delaunay  * use the 2 associated parameters:
23*0d98c255SPatrick Delaunay  * - PM_HINT_CONTEXT_STATE : advertise driver to save all their context in DDR
24*0d98c255SPatrick Delaunay  *                           (self refresh) for standby mode
25*0d98c255SPatrick Delaunay  * - PM_HINT_CLOCK_STATE : advertise driver to interrupt operation when clock
26*0d98c255SPatrick Delaunay  *                         are stalled for the other low power modes
27*0d98c255SPatrick Delaunay  */
28*0d98c255SPatrick Delaunay #define PM_CORE_LEVEL           0
29*0d98c255SPatrick Delaunay #define PM_D1_LEVEL             1
30*0d98c255SPatrick Delaunay #define PM_D1_LPLV_LEVEL        2
31*0d98c255SPatrick Delaunay #define PM_D2_LEVEL             3
32*0d98c255SPatrick Delaunay #define PM_D2_LPLV_LEVEL        4
33*0d98c255SPatrick Delaunay #define PM_MAX_LEVEL            5
34*0d98c255SPatrick Delaunay 
35*0d98c255SPatrick Delaunay #endif /*__STM32MP_PM_H__*/
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