1flavor_dts_file-215F_DK = stm32mp215f-dk.dts 2flavor_dts_file-257F_EV1 = stm32mp257f-ev1.dts 3 4flavorlist-MP21 = $(flavor_dts_file-215F_DK) 5flavorlist-MP25 = $(flavor_dts_file-257F_EV1) 6 7# List of all DTS for this PLATFORM 8ALL_DTS = $(flavorlist-MP21) $(flavorlist-MP25) 9 10ifneq ($(PLATFORM_FLAVOR),) 11ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 12$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 13endif 14CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 15endif 16CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp257f-ev1.dts 17 18ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP21)),) 19$(call force,CFG_STM32MP21,y) 20endif 21ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP25)),) 22$(call force,CFG_STM32MP25,y) 23endif 24 25# CFG_STM32MP2x switches are exclusive. 26# - CFG_STM32MP21 is enabled for STM32MP21x-* targets 27# - CFG_STM32MP25 is enabled for STM32MP25x-* targets (default) 28ifeq ($(CFG_STM32MP21),y) 29$(call force,CFG_STM32MP25,n) 30else 31$(call force,CFG_STM32MP21,n) 32$(call force,CFG_STM32MP25,y) 33endif 34 35include core/arch/arm/cpu/cortex-armv8-0.mk 36supported-ta-targets ?= ta_arm64 37 38$(call force,CFG_ARM64_core,y) 39$(call force,CFG_DRIVERS_CLK,y) 40$(call force,CFG_DRIVERS_CLK_DT,y) 41$(call force,CFG_DRIVERS_GPIO,y) 42$(call force,CFG_DRIVERS_PINCTRL,y) 43$(call force,CFG_DT,y) 44$(call force,CFG_GIC,y) 45$(call force,CFG_HALT_CORES_ON_PANIC_SGI,15) 46$(call force,CFG_INIT_CNTVOFF,y) 47$(call force,CFG_SCMI_SCPFW_PRODUCT,stm32mp2) 48$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 49$(call force,CFG_STM32_SHARED_IO,y) 50$(call force,CFG_STM32_STGEN,y) 51$(call force,CFG_STM32MP_CLK_CORE,y) 52$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 53$(call force,CFG_WITH_LPAE,y) 54 55ifeq ($(CFG_STM32MP21),y) 56else 57$(call force,CFG_STM32MP25_CLK,y) 58$(call force,CFG_STM32MP25_RSTCTRL,y) 59endif 60 61CFG_TZDRAM_START ?= 0x82000000 62CFG_TZDRAM_SIZE ?= 0x02000000 63 64# Support DDR ranges up to 8GBytes (address range: 0x80000000 + DDR size) 65CFG_CORE_LARGE_PHYS_ADDR ?= y 66CFG_CORE_ARM64_PA_BITS ?= 34 67 68CFG_CORE_HEAP_SIZE ?= 262144 69CFG_CORE_RESERVED_SHM ?= n 70CFG_DTB_MAX_SIZE ?= 262144 71CFG_HALT_CORES_ON_PANIC ?= y 72CFG_MMAP_REGIONS ?= 30 73CFG_NUM_THREADS ?= 5 74ifeq ($(CFG_STM32MP21),y) 75$(call force,CFG_TEE_CORE_NB_CORE,1) 76endif 77CFG_TEE_CORE_NB_CORE ?= 2 78CFG_STM32MP_OPP_COUNT ?= 3 79 80CFG_STM32_EXTI ?= y 81CFG_STM32_FMC ?= y 82CFG_STM32_GPIO ?= y 83CFG_STM32_HPDMA ?= y 84CFG_STM32_HSEM ?= y 85CFG_STM32_IAC ?= y 86CFG_STM32_IPCC ?= y 87CFG_STM32_OMM ?= y 88CFG_STM32_RIF ?= y 89CFG_STM32_RIFSC ?= y 90CFG_STM32_RISAB ?= y 91CFG_STM32_RISAF ?= y 92CFG_STM32_RNG ?= y 93CFG_STM32_RTC ?= y 94CFG_STM32_SERC ?= y 95CFG_STM32_TAMP ?= y 96CFG_STM32_UART ?= y 97 98CFG_SCMI_PTA ?= y 99CFG_SCMI_SCPFW ?= n 100CFG_SCMI_SCPFW_FROM_DT ?= y 101CFG_SCMI_SERVER_CLOCK_CONSUMER ?= y 102CFG_SCMI_SERVER_RESET_CONSUMER ?= y 103# Default enable some test facitilites 104CFG_ENABLE_EMBEDDED_TESTS ?= y 105CFG_WITH_STATS ?= y 106 107# Default disable ASLR 108CFG_CORE_ASLR ?= n 109 110# UART instance used for early console (0 disables early console) 111CFG_STM32_EARLY_CONSOLE_UART ?= 2 112 113# Default disable external DT support 114CFG_EXTERNAL_DT ?= n 115 116# Default enable HWRNG PTA support 117CFG_HWRNG_PTA ?= y 118ifeq ($(CFG_HWRNG_PTA),y) 119$(call force,CFG_STM32_RNG,y,Required by CFG_HWRNG_PTA) 120$(call force,CFG_WITH_SOFTWARE_PRNG,n,Required by CFG_HWRNG_PTA) 121CFG_HWRNG_QUALITY ?= 1024 122endif 123 124# Enable reset control 125ifeq ($(CFG_STM32MP21_RSTCTRL),y) 126$(call force,CFG_DRIVERS_RSTCTRL,y) 127$(call force,CFG_STM32_RSTCTRL,y) 128endif 129ifeq ($(CFG_STM32MP25_RSTCTRL),y) 130$(call force,CFG_DRIVERS_RSTCTRL,y) 131$(call force,CFG_STM32_RSTCTRL,y) 132endif 133 134# Optional behavior upon receiving illegal access events 135CFG_STM32_PANIC_ON_IAC_EVENT ?= y 136ifeq ($(CFG_TEE_CORE_DEBUG),y) 137CFG_STM32_PANIC_ON_SERC_EVENT ?= n 138else 139CFG_STM32_PANIC_ON_SERC_EVENT ?= y 140endif 141 142# Default enable firewall support 143CFG_DRIVERS_FIREWALL ?= y 144ifeq ($(call cfg-one-enabled, CFG_STM32_RISAB CFG_STM32_RIFSC),y) 145$(call force,CFG_DRIVERS_FIREWALL,y) 146endif 147 148# Enable RTC 149ifeq ($(CFG_STM32_RTC),y) 150$(call force,CFG_DRIVERS_RTC,y) 151endif 152 153ifeq ($(CFG_STM32_SERC),y) 154$(call force,CFG_EXTERNAL_ABORT_PLAT_HANDLER,y) 155endif 156