1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/stm32_bsec.h> 11 #include <kernel/panic.h> 12 #include <stdint.h> 13 #include <types_ext.h> 14 15 /* Backup registers and RAM utils */ 16 vaddr_t stm32mp_bkpreg(unsigned int idx); 17 18 /* Platform util for the GIC */ 19 vaddr_t get_gicc_base(void); 20 vaddr_t get_gicd_base(void); 21 22 /* 23 * Platform util functions for the GPIO driver 24 * @bank: Target GPIO bank ID as per DT bindings 25 * 26 * Platform shall implement these functions to provide to stm32_gpio 27 * driver the resource reference for a target GPIO bank. That are 28 * memory mapped interface base address, interface offset (see below) 29 * and clock identifier. 30 * 31 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 32 * check DT configuration matches platform implementation of the banks 33 * description. 34 */ 35 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 36 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 37 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 38 39 /* Power management service */ 40 #ifdef CFG_PSCI_ARM32 41 void stm32mp_register_online_cpu(void); 42 #else 43 static inline void stm32mp_register_online_cpu(void) 44 { 45 } 46 #endif 47 48 /* 49 * Generic spinlock function that bypass spinlock if MMU is disabled or 50 * lock is NULL. 51 */ 52 uint32_t may_spin_lock(unsigned int *lock); 53 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 54 55 /* 56 * Util for clock gating and to get clock rate for stm32 and platform drivers 57 * @id: Target clock ID, ID used in clock DT bindings 58 */ 59 void stm32_clock_enable(unsigned long id); 60 void stm32_clock_disable(unsigned long id); 61 unsigned long stm32_clock_get_rate(unsigned long id); 62 bool stm32_clock_is_enabled(unsigned long id); 63 64 /* Return true if @clock_id is shared by secure and non-secure worlds */ 65 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 66 67 /* 68 * Util for reset signal assertion/desassertion for stm32 and platform drivers 69 * @id: Target peripheral ID, ID used in reset DT bindings 70 * @to_us: Timeout out in microsecond, or 0 if not waiting signal state 71 */ 72 TEE_Result stm32_reset_assert(unsigned int id, unsigned int timeout_us); 73 TEE_Result stm32_reset_deassert(unsigned int id, unsigned int timeout_us); 74 75 static inline void stm32_reset_set(unsigned int id) 76 { 77 (void)stm32_reset_assert(id, 0); 78 } 79 80 static inline void stm32_reset_release(unsigned int id) 81 { 82 (void)stm32_reset_deassert(id, 0); 83 } 84 85 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 86 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 87 88 /* 89 * Structure and API function for BSEC driver to get some platform data. 90 * 91 * @base: BSEC interface registers physical base address 92 * @upper_start: Base ID for the BSEC upper words in the platform 93 * @max_id: Max value for BSEC word ID for the platform 94 */ 95 struct stm32_bsec_static_cfg { 96 paddr_t base; 97 unsigned int upper_start; 98 unsigned int max_id; 99 }; 100 101 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 102 103 /* 104 * Return true if platform is in closed_device mode 105 */ 106 bool stm32mp_is_closed_device(void); 107 108 /* 109 * Shared registers support: common lock for accessing SoC registers 110 * shared between several drivers. 111 */ 112 void io_mask32_stm32shregs(vaddr_t va, uint32_t value, uint32_t mask); 113 114 static inline void io_setbits32_stm32shregs(vaddr_t va, uint32_t value) 115 { 116 io_mask32_stm32shregs(va, value, value); 117 } 118 119 static inline void io_clrbits32_stm32shregs(vaddr_t va, uint32_t value) 120 { 121 io_mask32_stm32shregs(va, 0, value); 122 } 123 124 void io_clrsetbits32_stm32shregs(vaddr_t va, uint32_t clr, uint32_t set); 125 126 /* 127 * Shared reference counter: increments by 2 on secure increment 128 * request, decrements by 2 on secure decrement request. Bit #0 129 * is set to 1 on non-secure increment request and reset to 0 on 130 * non-secure decrement request. These counters initialize to 131 * either 0, 1 or 2 upon their expect default state. 132 * Counters saturate to UINT_MAX / 2. 133 */ 134 #define SHREFCNT_NONSECURE_FLAG 0x1ul 135 #define SHREFCNT_SECURE_STEP 0x2ul 136 #define SHREFCNT_MAX (UINT_MAX / 2) 137 138 /* Return 1 if refcnt increments from 0, else return 0 */ 139 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 140 { 141 int rc = !*refcnt; 142 143 if (secure) { 144 if (*refcnt < SHREFCNT_MAX) { 145 *refcnt += SHREFCNT_SECURE_STEP; 146 assert(*refcnt < SHREFCNT_MAX); 147 } 148 } else { 149 *refcnt |= SHREFCNT_NONSECURE_FLAG; 150 } 151 152 return rc; 153 } 154 155 /* Return 1 if refcnt decrements to 0, else return 0 */ 156 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 157 { 158 int rc = 0; 159 160 if (secure) { 161 if (*refcnt < SHREFCNT_MAX) { 162 if (*refcnt < SHREFCNT_SECURE_STEP) 163 panic(); 164 165 *refcnt -= SHREFCNT_SECURE_STEP; 166 rc = !*refcnt; 167 } 168 } else { 169 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 170 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 171 } 172 173 return rc; 174 } 175 176 static inline int incr_refcnt(unsigned int *refcnt) 177 { 178 return incr_shrefcnt(refcnt, true); 179 } 180 181 static inline int decr_refcnt(unsigned int *refcnt) 182 { 183 return decr_shrefcnt(refcnt, true); 184 } 185 186 /* 187 * Shared peripherals and resources registration 188 * 189 * Resources listed in enum stm32mp_shres assigned at run-time to the 190 * non-secure world, to the secure world or shared by both worlds. 191 * In the later case, there must exist a secure service in OP-TEE 192 * for the non-secure world to access the resource. 193 * 194 * Resources may be a peripheral, a bus, a clock or a memory. 195 * 196 * Shared resources driver API functions allows drivers to register the 197 * resource as secure, non-secure or shared and to get the resource 198 * assignation state. 199 */ 200 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 201 202 enum stm32mp_shres { 203 STM32MP1_SHRES_GPIOZ_0 = 0, 204 STM32MP1_SHRES_GPIOZ_1, 205 STM32MP1_SHRES_GPIOZ_2, 206 STM32MP1_SHRES_GPIOZ_3, 207 STM32MP1_SHRES_GPIOZ_4, 208 STM32MP1_SHRES_GPIOZ_5, 209 STM32MP1_SHRES_GPIOZ_6, 210 STM32MP1_SHRES_GPIOZ_7, 211 STM32MP1_SHRES_IWDG1, 212 STM32MP1_SHRES_USART1, 213 STM32MP1_SHRES_SPI6, 214 STM32MP1_SHRES_I2C4, 215 STM32MP1_SHRES_RNG1, 216 STM32MP1_SHRES_HASH1, 217 STM32MP1_SHRES_CRYP1, 218 STM32MP1_SHRES_I2C6, 219 STM32MP1_SHRES_RTC, 220 STM32MP1_SHRES_MCU, 221 STM32MP1_SHRES_PLL3, 222 STM32MP1_SHRES_MDMA, 223 224 STM32MP1_SHRES_COUNT 225 }; 226 227 /* Register resource @id as a secure peripheral */ 228 void stm32mp_register_secure_periph(enum stm32mp_shres id); 229 230 /* Register resource @id as a non-secure peripheral */ 231 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 232 233 /* 234 * Register resource identified by @base as a secure peripheral 235 * @base: IOMEM physical base address of the resource 236 */ 237 void stm32mp_register_secure_periph_iomem(vaddr_t base); 238 239 /* 240 * Register resource identified by @base as a non-secure peripheral 241 * @base: IOMEM physical base address of the resource 242 */ 243 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 244 245 /* 246 * Register GPIO resource as a secure peripheral 247 * @bank: Bank of the target GPIO 248 * @pin: Bit position of the target GPIO in the bank 249 */ 250 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 251 252 /* 253 * Register GPIO resource as a non-secure peripheral 254 * @bank: Bank of the target GPIO 255 * @pin: Bit position of the target GPIO in the bank 256 */ 257 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 258 259 /* Return true if and only if resource @id is registered as secure */ 260 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 261 262 /* Return true if and only if GPIO bank @bank is registered as secure */ 263 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 264 265 /* Return true if and only if GPIO bank @bank is registered as shared */ 266 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 267 268 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 269 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 270 271 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 272 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 273 274 #endif /*__STM32_UTIL_H__*/ 275