1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/stm32_bsec.h> 12 #include <kernel/panic.h> 13 #include <stdint.h> 14 #include <types_ext.h> 15 16 /* Backup registers and RAM utils */ 17 vaddr_t stm32mp_bkpreg(unsigned int idx); 18 19 /* 20 * SYSCFG IO compensation. 21 * These functions assume non-secure world is suspended. 22 */ 23 void stm32mp_syscfg_enable_io_compensation(void); 24 void stm32mp_syscfg_disable_io_compensation(void); 25 26 /* Platform util for the GIC */ 27 vaddr_t get_gicc_base(void); 28 vaddr_t get_gicd_base(void); 29 30 /* 31 * Platform util functions for the GPIO driver 32 * @bank: Target GPIO bank ID as per DT bindings 33 * 34 * Platform shall implement these functions to provide to stm32_gpio 35 * driver the resource reference for a target GPIO bank. That are 36 * memory mapped interface base address, interface offset (see below) 37 * and clock identifier. 38 * 39 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 40 * check DT configuration matches platform implementation of the banks 41 * description. 42 */ 43 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 44 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 45 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 46 47 /* Platform util for PMIC support */ 48 bool stm32mp_with_pmic(void); 49 50 /* Power management service */ 51 #ifdef CFG_PSCI_ARM32 52 void stm32mp_register_online_cpu(void); 53 #else 54 static inline void stm32mp_register_online_cpu(void) 55 { 56 } 57 #endif 58 59 /* 60 * Generic spinlock function that bypass spinlock if MMU is disabled or 61 * lock is NULL. 62 */ 63 uint32_t may_spin_lock(unsigned int *lock); 64 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 65 66 /* 67 * Util for clock gating and to get clock rate for stm32 and platform drivers 68 * @id: Target clock ID, ID used in clock DT bindings 69 */ 70 void stm32_clock_enable(unsigned long id); 71 void stm32_clock_disable(unsigned long id); 72 unsigned long stm32_clock_get_rate(unsigned long id); 73 bool stm32_clock_is_enabled(unsigned long id); 74 75 /* Return true if @clock_id is shared by secure and non-secure worlds */ 76 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 77 78 extern const struct clk_ops stm32mp1_clk_ops; 79 80 #if defined(CFG_STPMIC1) 81 /* Return true if non-secure world can manipulate regulator @pmic_regu_name */ 82 bool stm32mp_nsec_can_access_pmic_regu(const char *pmic_regu_name); 83 #else 84 static inline bool stm32mp_nsec_can_access_pmic_regu(const char *name __unused) 85 { 86 return false; 87 } 88 #endif 89 90 /* 91 * Util for reset signal assertion/desassertion for stm32 and platform drivers 92 * @id: Target peripheral ID, ID used in reset DT bindings 93 * @to_us: Timeout out in microsecond, or 0 if not waiting signal state 94 */ 95 TEE_Result stm32_reset_assert(unsigned int id, unsigned int timeout_us); 96 TEE_Result stm32_reset_deassert(unsigned int id, unsigned int timeout_us); 97 98 /* Specific reset to manage the MCU hold boot */ 99 void stm32_reset_assert_deassert_mcu(bool assert_not_deassert); 100 101 static inline void stm32_reset_set(unsigned int id) 102 { 103 (void)stm32_reset_assert(id, 0); 104 } 105 106 static inline void stm32_reset_release(unsigned int id) 107 { 108 (void)stm32_reset_deassert(id, 0); 109 } 110 111 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 112 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 113 114 /* 115 * Structure and API function for BSEC driver to get some platform data. 116 * 117 * @base: BSEC interface registers physical base address 118 * @upper_start: Base ID for the BSEC upper words in the platform 119 * @max_id: Max value for BSEC word ID for the platform 120 */ 121 struct stm32_bsec_static_cfg { 122 paddr_t base; 123 unsigned int upper_start; 124 unsigned int max_id; 125 }; 126 127 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 128 129 /* 130 * Return true if platform is in closed_device mode 131 */ 132 bool stm32mp_is_closed_device(void); 133 134 /* 135 * Shared registers support: common lock for accessing SoC registers 136 * shared between several drivers. 137 */ 138 void io_mask32_stm32shregs(vaddr_t va, uint32_t value, uint32_t mask); 139 140 static inline void io_setbits32_stm32shregs(vaddr_t va, uint32_t value) 141 { 142 io_mask32_stm32shregs(va, value, value); 143 } 144 145 static inline void io_clrbits32_stm32shregs(vaddr_t va, uint32_t value) 146 { 147 io_mask32_stm32shregs(va, 0, value); 148 } 149 150 void io_clrsetbits32_stm32shregs(vaddr_t va, uint32_t clr, uint32_t set); 151 152 /* 153 * Shared reference counter: increments by 2 on secure increment 154 * request, decrements by 2 on secure decrement request. Bit #0 155 * is set to 1 on non-secure increment request and reset to 0 on 156 * non-secure decrement request. These counters initialize to 157 * either 0, 1 or 2 upon their expect default state. 158 * Counters saturate to UINT_MAX / 2. 159 */ 160 #define SHREFCNT_NONSECURE_FLAG 0x1ul 161 #define SHREFCNT_SECURE_STEP 0x2ul 162 #define SHREFCNT_MAX (UINT_MAX / 2) 163 164 /* Return 1 if refcnt increments from 0, else return 0 */ 165 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 166 { 167 int rc = !*refcnt; 168 169 if (secure) { 170 if (*refcnt < SHREFCNT_MAX) { 171 *refcnt += SHREFCNT_SECURE_STEP; 172 assert(*refcnt < SHREFCNT_MAX); 173 } 174 } else { 175 *refcnt |= SHREFCNT_NONSECURE_FLAG; 176 } 177 178 return rc; 179 } 180 181 /* Return 1 if refcnt decrements to 0, else return 0 */ 182 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 183 { 184 int rc = 0; 185 186 if (secure) { 187 if (*refcnt < SHREFCNT_MAX) { 188 if (*refcnt < SHREFCNT_SECURE_STEP) 189 panic(); 190 191 *refcnt -= SHREFCNT_SECURE_STEP; 192 rc = !*refcnt; 193 } 194 } else { 195 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 196 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 197 } 198 199 return rc; 200 } 201 202 static inline int incr_refcnt(unsigned int *refcnt) 203 { 204 return incr_shrefcnt(refcnt, true); 205 } 206 207 static inline int decr_refcnt(unsigned int *refcnt) 208 { 209 return decr_shrefcnt(refcnt, true); 210 } 211 212 /* 213 * Shared peripherals and resources registration 214 * 215 * Resources listed in enum stm32mp_shres assigned at run-time to the 216 * non-secure world, to the secure world or shared by both worlds. 217 * In the later case, there must exist a secure service in OP-TEE 218 * for the non-secure world to access the resource. 219 * 220 * Resources may be a peripheral, a bus, a clock or a memory. 221 * 222 * Shared resources driver API functions allows drivers to register the 223 * resource as secure, non-secure or shared and to get the resource 224 * assignation state. 225 */ 226 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 227 228 enum stm32mp_shres { 229 STM32MP1_SHRES_GPIOZ_0 = 0, 230 STM32MP1_SHRES_GPIOZ_1, 231 STM32MP1_SHRES_GPIOZ_2, 232 STM32MP1_SHRES_GPIOZ_3, 233 STM32MP1_SHRES_GPIOZ_4, 234 STM32MP1_SHRES_GPIOZ_5, 235 STM32MP1_SHRES_GPIOZ_6, 236 STM32MP1_SHRES_GPIOZ_7, 237 STM32MP1_SHRES_IWDG1, 238 STM32MP1_SHRES_USART1, 239 STM32MP1_SHRES_SPI6, 240 STM32MP1_SHRES_I2C4, 241 STM32MP1_SHRES_RNG1, 242 STM32MP1_SHRES_HASH1, 243 STM32MP1_SHRES_CRYP1, 244 STM32MP1_SHRES_I2C6, 245 STM32MP1_SHRES_RTC, 246 STM32MP1_SHRES_MCU, 247 STM32MP1_SHRES_PLL3, 248 STM32MP1_SHRES_MDMA, 249 250 STM32MP1_SHRES_COUNT 251 }; 252 253 /* Register resource @id as a secure peripheral */ 254 void stm32mp_register_secure_periph(enum stm32mp_shres id); 255 256 /* Register resource @id as a non-secure peripheral */ 257 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 258 259 /* 260 * Register resource identified by @base as a secure peripheral 261 * @base: IOMEM physical base address of the resource 262 */ 263 void stm32mp_register_secure_periph_iomem(vaddr_t base); 264 265 /* 266 * Register resource identified by @base as a non-secure peripheral 267 * @base: IOMEM physical base address of the resource 268 */ 269 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 270 271 /* 272 * Register GPIO resource as a secure peripheral 273 * @bank: Bank of the target GPIO 274 * @pin: Bit position of the target GPIO in the bank 275 */ 276 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 277 278 /* 279 * Register GPIO resource as a non-secure peripheral 280 * @bank: Bank of the target GPIO 281 * @pin: Bit position of the target GPIO in the bank 282 */ 283 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 284 285 /* Return true if and only if resource @id is registered as secure */ 286 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 287 288 /* Return true if and only if GPIO bank @bank is registered as secure */ 289 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 290 291 /* Return true if and only if GPIO bank @bank is registered as shared */ 292 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 293 294 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 295 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 296 297 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 298 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 299 300 #endif /*__STM32_UTIL_H__*/ 301