1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/stm32_bsec.h> 12 #include <kernel/panic.h> 13 #include <stdint.h> 14 #include <types_ext.h> 15 16 /* Backup registers and RAM utils */ 17 vaddr_t stm32mp_bkpreg(unsigned int idx); 18 19 /* 20 * SYSCFG IO compensation. 21 * These functions assume non-secure world is suspended. 22 */ 23 void stm32mp_syscfg_enable_io_compensation(void); 24 void stm32mp_syscfg_disable_io_compensation(void); 25 26 /* Platform util for the RCC drivers */ 27 vaddr_t stm32_rcc_base(void); 28 29 /* Platform util for the GIC */ 30 vaddr_t get_gicd_base(void); 31 32 /* 33 * Platform util functions for the GPIO driver 34 * @bank: Target GPIO bank ID as per DT bindings 35 * 36 * Platform shall implement these functions to provide to stm32_gpio 37 * driver the resource reference for a target GPIO bank. That are 38 * memory mapped interface base address, interface offset (see below) 39 * and clock identifier. 40 * 41 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 42 * check DT configuration matches platform implementation of the banks 43 * description. 44 */ 45 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 46 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 47 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 48 struct clk *stm32_get_gpio_bank_clk(unsigned int bank); 49 50 /* Platform util for PMIC support */ 51 bool stm32mp_with_pmic(void); 52 53 /* Power management service */ 54 #ifdef CFG_PSCI_ARM32 55 void stm32mp_register_online_cpu(void); 56 #else 57 static inline void stm32mp_register_online_cpu(void) 58 { 59 } 60 #endif 61 62 /* 63 * Generic spinlock function that bypass spinlock if MMU is disabled or 64 * lock is NULL. 65 */ 66 uint32_t may_spin_lock(unsigned int *lock); 67 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 68 69 /* 70 * Util for clock gating and to get clock rate for stm32 and platform drivers 71 * @id: Target clock ID, ID used in clock DT bindings 72 */ 73 void stm32_clock_enable(unsigned long id); 74 void stm32_clock_disable(unsigned long id); 75 unsigned long stm32_clock_get_rate(unsigned long id); 76 bool stm32_clock_is_enabled(unsigned long id); 77 78 /* Helper from platform RCC clock driver */ 79 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id); 80 81 /* Return true if @clock_id is shared by secure and non-secure worlds */ 82 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 83 84 extern const struct clk_ops stm32mp1_clk_ops; 85 86 #if defined(CFG_STPMIC1) 87 /* Return true if non-secure world can manipulate regulator @pmic_regu_name */ 88 bool stm32mp_nsec_can_access_pmic_regu(const char *pmic_regu_name); 89 #else 90 static inline bool stm32mp_nsec_can_access_pmic_regu(const char *name __unused) 91 { 92 return false; 93 } 94 #endif 95 96 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 97 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 98 99 /* Return rstctrl instance related to RCC reset controller DT binding ID */ 100 struct rstctrl *stm32mp_rcc_reset_id_to_rstctrl(unsigned int binding_id); 101 102 /* 103 * Structure and API function for BSEC driver to get some platform data. 104 * 105 * @base: BSEC interface registers physical base address 106 * @upper_start: Base ID for the BSEC upper words in the platform 107 * @max_id: Max value for BSEC word ID for the platform 108 */ 109 struct stm32_bsec_static_cfg { 110 paddr_t base; 111 unsigned int upper_start; 112 unsigned int max_id; 113 }; 114 115 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 116 117 /* 118 * Return true if platform is in closed_device mode 119 */ 120 bool stm32mp_is_closed_device(void); 121 122 /* 123 * Shared registers support: common lock for accessing SoC registers 124 * shared between several drivers. 125 */ 126 void io_mask32_stm32shregs(vaddr_t va, uint32_t value, uint32_t mask); 127 128 static inline void io_setbits32_stm32shregs(vaddr_t va, uint32_t value) 129 { 130 io_mask32_stm32shregs(va, value, value); 131 } 132 133 static inline void io_clrbits32_stm32shregs(vaddr_t va, uint32_t value) 134 { 135 io_mask32_stm32shregs(va, 0, value); 136 } 137 138 void io_clrsetbits32_stm32shregs(vaddr_t va, uint32_t clr, uint32_t set); 139 140 /* 141 * Shared reference counter: increments by 2 on secure increment 142 * request, decrements by 2 on secure decrement request. Bit #0 143 * is set to 1 on non-secure increment request and reset to 0 on 144 * non-secure decrement request. These counters initialize to 145 * either 0, 1 or 2 upon their expect default state. 146 * Counters saturate to UINT_MAX / 2. 147 */ 148 #define SHREFCNT_NONSECURE_FLAG 0x1ul 149 #define SHREFCNT_SECURE_STEP 0x2ul 150 #define SHREFCNT_MAX (UINT_MAX / 2) 151 152 /* Return 1 if refcnt increments from 0, else return 0 */ 153 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 154 { 155 int rc = !*refcnt; 156 157 if (secure) { 158 if (*refcnt < SHREFCNT_MAX) { 159 *refcnt += SHREFCNT_SECURE_STEP; 160 assert(*refcnt < SHREFCNT_MAX); 161 } 162 } else { 163 *refcnt |= SHREFCNT_NONSECURE_FLAG; 164 } 165 166 return rc; 167 } 168 169 /* Return 1 if refcnt decrements to 0, else return 0 */ 170 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 171 { 172 int rc = 0; 173 174 if (secure) { 175 if (*refcnt < SHREFCNT_MAX) { 176 if (*refcnt < SHREFCNT_SECURE_STEP) 177 panic(); 178 179 *refcnt -= SHREFCNT_SECURE_STEP; 180 rc = !*refcnt; 181 } 182 } else { 183 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 184 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 185 } 186 187 return rc; 188 } 189 190 static inline int incr_refcnt(unsigned int *refcnt) 191 { 192 return incr_shrefcnt(refcnt, true); 193 } 194 195 static inline int decr_refcnt(unsigned int *refcnt) 196 { 197 return decr_shrefcnt(refcnt, true); 198 } 199 200 /* 201 * Shared peripherals and resources registration 202 * 203 * Resources listed in enum stm32mp_shres assigned at run-time to the 204 * non-secure world, to the secure world or shared by both worlds. 205 * In the later case, there must exist a secure service in OP-TEE 206 * for the non-secure world to access the resource. 207 * 208 * Resources may be a peripheral, a bus, a clock or a memory. 209 * 210 * Shared resources driver API functions allows drivers to register the 211 * resource as secure, non-secure or shared and to get the resource 212 * assignation state. 213 */ 214 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 215 216 enum stm32mp_shres { 217 STM32MP1_SHRES_GPIOZ_0 = 0, 218 STM32MP1_SHRES_GPIOZ_1, 219 STM32MP1_SHRES_GPIOZ_2, 220 STM32MP1_SHRES_GPIOZ_3, 221 STM32MP1_SHRES_GPIOZ_4, 222 STM32MP1_SHRES_GPIOZ_5, 223 STM32MP1_SHRES_GPIOZ_6, 224 STM32MP1_SHRES_GPIOZ_7, 225 STM32MP1_SHRES_IWDG1, 226 STM32MP1_SHRES_USART1, 227 STM32MP1_SHRES_SPI6, 228 STM32MP1_SHRES_I2C4, 229 STM32MP1_SHRES_RNG1, 230 STM32MP1_SHRES_HASH1, 231 STM32MP1_SHRES_CRYP1, 232 STM32MP1_SHRES_I2C6, 233 STM32MP1_SHRES_RTC, 234 STM32MP1_SHRES_MCU, 235 STM32MP1_SHRES_PLL3, 236 STM32MP1_SHRES_MDMA, 237 238 STM32MP1_SHRES_COUNT 239 }; 240 241 /* Register resource @id as a secure peripheral */ 242 void stm32mp_register_secure_periph(enum stm32mp_shres id); 243 244 /* Register resource @id as a non-secure peripheral */ 245 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 246 247 /* 248 * Register resource identified by @base as a secure peripheral 249 * @base: IOMEM physical base address of the resource 250 */ 251 void stm32mp_register_secure_periph_iomem(vaddr_t base); 252 253 /* 254 * Register resource identified by @base as a non-secure peripheral 255 * @base: IOMEM physical base address of the resource 256 */ 257 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 258 259 /* 260 * Register GPIO resource as a secure peripheral 261 * @bank: Bank of the target GPIO 262 * @pin: Bit position of the target GPIO in the bank 263 */ 264 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 265 266 /* 267 * Register GPIO resource as a non-secure peripheral 268 * @bank: Bank of the target GPIO 269 * @pin: Bit position of the target GPIO in the bank 270 */ 271 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 272 273 /* Return true if and only if resource @id is registered as secure */ 274 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 275 276 /* Return true if and only if GPIO bank @bank is registered as secure */ 277 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 278 279 /* Return true if and only if GPIO bank @bank is registered as shared */ 280 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 281 282 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 283 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 284 285 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 286 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 287 288 #endif /*__STM32_UTIL_H__*/ 289