1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2022, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/pinctrl.h> 12 #include <drivers/stm32_bsec.h> 13 #include <kernel/panic.h> 14 #include <stdint.h> 15 #include <tee_api_types.h> 16 #include <types_ext.h> 17 18 /* Backup registers and RAM utils */ 19 vaddr_t stm32mp_bkpreg(unsigned int idx); 20 21 /* Platform util for the RCC drivers */ 22 vaddr_t stm32_rcc_base(void); 23 24 /* Platform util for the GIC */ 25 vaddr_t get_gicd_base(void); 26 27 /* Platform util for PMIC support */ 28 bool stm32mp_with_pmic(void); 29 30 /* Power management service */ 31 #ifdef CFG_PSCI_ARM32 32 void stm32mp_register_online_cpu(void); 33 #else 34 static inline void stm32mp_register_online_cpu(void) 35 { 36 } 37 #endif 38 39 /* 40 * Generic spinlock function that bypass spinlock if MMU is disabled or 41 * lock is NULL. 42 */ 43 uint32_t may_spin_lock(unsigned int *lock); 44 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 45 46 /* Helper from platform RCC clock driver */ 47 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id); 48 49 extern const struct clk_ops stm32mp1_clk_ops; 50 51 #ifdef CFG_STM32MP1_SHARED_RESOURCES 52 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 53 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 54 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 55 static inline bool stm32mp_nsec_can_access_reset(unsigned int reset_id __unused) 56 { 57 return true; 58 } 59 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 60 61 /* Return rstctrl instance related to RCC reset controller DT binding ID */ 62 struct rstctrl *stm32mp_rcc_reset_id_to_rstctrl(unsigned int binding_id); 63 64 /* 65 * Structure and API function for BSEC driver to get some platform data. 66 * 67 * @base: BSEC interface registers physical base address 68 * @upper_start: Base ID for the BSEC upper words in the platform 69 * @max_id: Max value for BSEC word ID for the platform 70 */ 71 struct stm32_bsec_static_cfg { 72 paddr_t base; 73 unsigned int upper_start; 74 unsigned int max_id; 75 }; 76 77 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 78 79 /* 80 * Shared reference counter: increments by 2 on secure increment 81 * request, decrements by 2 on secure decrement request. Bit #0 82 * is set to 1 on non-secure increment request and reset to 0 on 83 * non-secure decrement request. These counters initialize to 84 * either 0, 1 or 2 upon their expect default state. 85 * Counters saturate to UINT_MAX / 2. 86 */ 87 #define SHREFCNT_NONSECURE_FLAG 0x1ul 88 #define SHREFCNT_SECURE_STEP 0x2ul 89 #define SHREFCNT_MAX (UINT_MAX / 2) 90 91 /* Return 1 if refcnt increments from 0, else return 0 */ 92 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 93 { 94 int rc = !*refcnt; 95 96 if (secure) { 97 if (*refcnt < SHREFCNT_MAX) { 98 *refcnt += SHREFCNT_SECURE_STEP; 99 assert(*refcnt < SHREFCNT_MAX); 100 } 101 } else { 102 *refcnt |= SHREFCNT_NONSECURE_FLAG; 103 } 104 105 return rc; 106 } 107 108 /* Return 1 if refcnt decrements to 0, else return 0 */ 109 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 110 { 111 int rc = 0; 112 113 if (secure) { 114 if (*refcnt < SHREFCNT_MAX) { 115 if (*refcnt < SHREFCNT_SECURE_STEP) 116 panic(); 117 118 *refcnt -= SHREFCNT_SECURE_STEP; 119 rc = !*refcnt; 120 } 121 } else { 122 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 123 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 124 } 125 126 return rc; 127 } 128 129 static inline int incr_refcnt(unsigned int *refcnt) 130 { 131 return incr_shrefcnt(refcnt, true); 132 } 133 134 static inline int decr_refcnt(unsigned int *refcnt) 135 { 136 return decr_shrefcnt(refcnt, true); 137 } 138 139 /* 140 * Shared peripherals and resources registration 141 * 142 * Resources listed in enum stm32mp_shres assigned at run-time to the 143 * non-secure world, to the secure world or shared by both worlds. 144 * In the later case, there must exist a secure service in OP-TEE 145 * for the non-secure world to access the resource. 146 * 147 * Resources may be a peripheral, a bus, a clock or a memory. 148 * 149 * Shared resources driver API functions allows drivers to register the 150 * resource as secure, non-secure or shared and to get the resource 151 * assignation state. 152 */ 153 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 154 155 enum stm32mp_shres { 156 STM32MP1_SHRES_GPIOZ_0 = 0, 157 STM32MP1_SHRES_GPIOZ_1, 158 STM32MP1_SHRES_GPIOZ_2, 159 STM32MP1_SHRES_GPIOZ_3, 160 STM32MP1_SHRES_GPIOZ_4, 161 STM32MP1_SHRES_GPIOZ_5, 162 STM32MP1_SHRES_GPIOZ_6, 163 STM32MP1_SHRES_GPIOZ_7, 164 STM32MP1_SHRES_IWDG1, 165 STM32MP1_SHRES_USART1, 166 STM32MP1_SHRES_SPI6, 167 STM32MP1_SHRES_I2C4, 168 STM32MP1_SHRES_RNG1, 169 STM32MP1_SHRES_HASH1, 170 STM32MP1_SHRES_CRYP1, 171 STM32MP1_SHRES_I2C6, 172 STM32MP1_SHRES_RTC, 173 STM32MP1_SHRES_MCU, 174 STM32MP1_SHRES_PLL3, 175 STM32MP1_SHRES_MDMA, 176 STM32MP1_SHRES_SRAM1, 177 STM32MP1_SHRES_SRAM2, 178 STM32MP1_SHRES_SRAM3, 179 STM32MP1_SHRES_SRAM4, 180 181 STM32MP1_SHRES_COUNT 182 }; 183 184 bool stm32mp_allow_probe_shared_device(const void *fdt, int node); 185 186 #if defined(CFG_STM32MP15) && defined(CFG_WITH_PAGER) 187 /* 188 * Return the SRAM alias physical address related to @pa when applicable or 189 * @pa if it does not relate to an SRAMx non-aliased memory address. 190 */ 191 paddr_t stm32mp1_pa_or_sram_alias_pa(paddr_t pa); 192 193 /* Return whether or not the physical address range intersec pager secure RAM */ 194 bool stm32mp1_ram_intersect_pager_ram(paddr_t base, size_t size); 195 #else 196 static inline paddr_t stm32mp1_pa_or_sram_alias_pa(paddr_t pa) 197 { 198 return pa; 199 } 200 201 static inline bool stm32mp1_ram_intersect_pager_ram(paddr_t base __unused, 202 size_t size __unused) 203 { 204 return false; 205 } 206 #endif /*CFG_STM32MP15 && CFG_WITH_PAGER*/ 207 208 #ifdef CFG_STM32MP1_SHARED_RESOURCES 209 /* Register resource @id as a secure peripheral */ 210 void stm32mp_register_secure_periph(enum stm32mp_shres id); 211 212 /* Register resource @id as a non-secure peripheral */ 213 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 214 215 /* 216 * Register resource identified by @base as a secure peripheral 217 * @base: IOMEM physical base address of the resource 218 */ 219 void stm32mp_register_secure_periph_iomem(vaddr_t base); 220 221 /* 222 * Register resource identified by @base as a non-secure peripheral 223 * @base: IOMEM physical base address of the resource 224 */ 225 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 226 227 /* Return true if and only if resource @id is registered as secure */ 228 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 229 230 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 231 232 static inline void stm32mp_register_secure_periph(enum stm32mp_shres id 233 __unused) 234 { 235 } 236 237 static inline void stm32mp_register_non_secure_periph(enum stm32mp_shres id 238 __unused) 239 { 240 } 241 242 static inline void stm32mp_register_secure_periph_iomem(vaddr_t base __unused) 243 { 244 } 245 246 static inline void stm32mp_register_non_secure_periph_iomem(vaddr_t base 247 __unused) 248 { 249 } 250 251 static inline bool stm32mp_periph_is_secure(enum stm32mp_shres id __unused) 252 { 253 return true; 254 } 255 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 256 #endif /*__STM32_UTIL_H__*/ 257