1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/stm32_bsec.h> 11 #include <kernel/panic.h> 12 #include <stdint.h> 13 #include <types_ext.h> 14 15 /* Backup registers and RAM utils */ 16 vaddr_t stm32mp_bkpreg(unsigned int idx); 17 18 /* 19 * SYSCFG IO compensation. 20 * These functions assume non-secure world is suspended. 21 */ 22 void stm32mp_syscfg_enable_io_compensation(void); 23 void stm32mp_syscfg_disable_io_compensation(void); 24 25 /* Platform util for the GIC */ 26 vaddr_t get_gicc_base(void); 27 vaddr_t get_gicd_base(void); 28 29 /* 30 * Platform util functions for the GPIO driver 31 * @bank: Target GPIO bank ID as per DT bindings 32 * 33 * Platform shall implement these functions to provide to stm32_gpio 34 * driver the resource reference for a target GPIO bank. That are 35 * memory mapped interface base address, interface offset (see below) 36 * and clock identifier. 37 * 38 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 39 * check DT configuration matches platform implementation of the banks 40 * description. 41 */ 42 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 43 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 44 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 45 46 /* Platform util for PMIC support */ 47 bool stm32mp_with_pmic(void); 48 49 /* Power management service */ 50 #ifdef CFG_PSCI_ARM32 51 void stm32mp_register_online_cpu(void); 52 #else 53 static inline void stm32mp_register_online_cpu(void) 54 { 55 } 56 #endif 57 58 /* 59 * Generic spinlock function that bypass spinlock if MMU is disabled or 60 * lock is NULL. 61 */ 62 uint32_t may_spin_lock(unsigned int *lock); 63 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 64 65 /* 66 * Util for clock gating and to get clock rate for stm32 and platform drivers 67 * @id: Target clock ID, ID used in clock DT bindings 68 */ 69 void stm32_clock_enable(unsigned long id); 70 void stm32_clock_disable(unsigned long id); 71 unsigned long stm32_clock_get_rate(unsigned long id); 72 bool stm32_clock_is_enabled(unsigned long id); 73 74 /* Return true if @clock_id is shared by secure and non-secure worlds */ 75 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 76 77 /* Return true if non-secure world can manipulate regulator @pmic_regu_name */ 78 bool stm32mp_nsec_can_access_pmic_regu(const char *pmic_regu_name); 79 80 /* 81 * Util for reset signal assertion/desassertion for stm32 and platform drivers 82 * @id: Target peripheral ID, ID used in reset DT bindings 83 * @to_us: Timeout out in microsecond, or 0 if not waiting signal state 84 */ 85 TEE_Result stm32_reset_assert(unsigned int id, unsigned int timeout_us); 86 TEE_Result stm32_reset_deassert(unsigned int id, unsigned int timeout_us); 87 88 /* Specific reset to manage the MCU hold boot */ 89 void stm32_reset_assert_deassert_mcu(bool assert_not_deassert); 90 91 static inline void stm32_reset_set(unsigned int id) 92 { 93 (void)stm32_reset_assert(id, 0); 94 } 95 96 static inline void stm32_reset_release(unsigned int id) 97 { 98 (void)stm32_reset_deassert(id, 0); 99 } 100 101 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 102 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 103 104 /* 105 * Structure and API function for BSEC driver to get some platform data. 106 * 107 * @base: BSEC interface registers physical base address 108 * @upper_start: Base ID for the BSEC upper words in the platform 109 * @max_id: Max value for BSEC word ID for the platform 110 */ 111 struct stm32_bsec_static_cfg { 112 paddr_t base; 113 unsigned int upper_start; 114 unsigned int max_id; 115 }; 116 117 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 118 119 /* 120 * Return true if platform is in closed_device mode 121 */ 122 bool stm32mp_is_closed_device(void); 123 124 /* 125 * Shared registers support: common lock for accessing SoC registers 126 * shared between several drivers. 127 */ 128 void io_mask32_stm32shregs(vaddr_t va, uint32_t value, uint32_t mask); 129 130 static inline void io_setbits32_stm32shregs(vaddr_t va, uint32_t value) 131 { 132 io_mask32_stm32shregs(va, value, value); 133 } 134 135 static inline void io_clrbits32_stm32shregs(vaddr_t va, uint32_t value) 136 { 137 io_mask32_stm32shregs(va, 0, value); 138 } 139 140 void io_clrsetbits32_stm32shregs(vaddr_t va, uint32_t clr, uint32_t set); 141 142 /* 143 * Shared reference counter: increments by 2 on secure increment 144 * request, decrements by 2 on secure decrement request. Bit #0 145 * is set to 1 on non-secure increment request and reset to 0 on 146 * non-secure decrement request. These counters initialize to 147 * either 0, 1 or 2 upon their expect default state. 148 * Counters saturate to UINT_MAX / 2. 149 */ 150 #define SHREFCNT_NONSECURE_FLAG 0x1ul 151 #define SHREFCNT_SECURE_STEP 0x2ul 152 #define SHREFCNT_MAX (UINT_MAX / 2) 153 154 /* Return 1 if refcnt increments from 0, else return 0 */ 155 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 156 { 157 int rc = !*refcnt; 158 159 if (secure) { 160 if (*refcnt < SHREFCNT_MAX) { 161 *refcnt += SHREFCNT_SECURE_STEP; 162 assert(*refcnt < SHREFCNT_MAX); 163 } 164 } else { 165 *refcnt |= SHREFCNT_NONSECURE_FLAG; 166 } 167 168 return rc; 169 } 170 171 /* Return 1 if refcnt decrements to 0, else return 0 */ 172 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 173 { 174 int rc = 0; 175 176 if (secure) { 177 if (*refcnt < SHREFCNT_MAX) { 178 if (*refcnt < SHREFCNT_SECURE_STEP) 179 panic(); 180 181 *refcnt -= SHREFCNT_SECURE_STEP; 182 rc = !*refcnt; 183 } 184 } else { 185 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 186 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 187 } 188 189 return rc; 190 } 191 192 static inline int incr_refcnt(unsigned int *refcnt) 193 { 194 return incr_shrefcnt(refcnt, true); 195 } 196 197 static inline int decr_refcnt(unsigned int *refcnt) 198 { 199 return decr_shrefcnt(refcnt, true); 200 } 201 202 /* 203 * Shared peripherals and resources registration 204 * 205 * Resources listed in enum stm32mp_shres assigned at run-time to the 206 * non-secure world, to the secure world or shared by both worlds. 207 * In the later case, there must exist a secure service in OP-TEE 208 * for the non-secure world to access the resource. 209 * 210 * Resources may be a peripheral, a bus, a clock or a memory. 211 * 212 * Shared resources driver API functions allows drivers to register the 213 * resource as secure, non-secure or shared and to get the resource 214 * assignation state. 215 */ 216 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 217 218 enum stm32mp_shres { 219 STM32MP1_SHRES_GPIOZ_0 = 0, 220 STM32MP1_SHRES_GPIOZ_1, 221 STM32MP1_SHRES_GPIOZ_2, 222 STM32MP1_SHRES_GPIOZ_3, 223 STM32MP1_SHRES_GPIOZ_4, 224 STM32MP1_SHRES_GPIOZ_5, 225 STM32MP1_SHRES_GPIOZ_6, 226 STM32MP1_SHRES_GPIOZ_7, 227 STM32MP1_SHRES_IWDG1, 228 STM32MP1_SHRES_USART1, 229 STM32MP1_SHRES_SPI6, 230 STM32MP1_SHRES_I2C4, 231 STM32MP1_SHRES_RNG1, 232 STM32MP1_SHRES_HASH1, 233 STM32MP1_SHRES_CRYP1, 234 STM32MP1_SHRES_I2C6, 235 STM32MP1_SHRES_RTC, 236 STM32MP1_SHRES_MCU, 237 STM32MP1_SHRES_PLL3, 238 STM32MP1_SHRES_MDMA, 239 240 STM32MP1_SHRES_COUNT 241 }; 242 243 /* Register resource @id as a secure peripheral */ 244 void stm32mp_register_secure_periph(enum stm32mp_shres id); 245 246 /* Register resource @id as a non-secure peripheral */ 247 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 248 249 /* 250 * Register resource identified by @base as a secure peripheral 251 * @base: IOMEM physical base address of the resource 252 */ 253 void stm32mp_register_secure_periph_iomem(vaddr_t base); 254 255 /* 256 * Register resource identified by @base as a non-secure peripheral 257 * @base: IOMEM physical base address of the resource 258 */ 259 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 260 261 /* 262 * Register GPIO resource as a secure peripheral 263 * @bank: Bank of the target GPIO 264 * @pin: Bit position of the target GPIO in the bank 265 */ 266 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 267 268 /* 269 * Register GPIO resource as a non-secure peripheral 270 * @bank: Bank of the target GPIO 271 * @pin: Bit position of the target GPIO in the bank 272 */ 273 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 274 275 /* Return true if and only if resource @id is registered as secure */ 276 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 277 278 /* Return true if and only if GPIO bank @bank is registered as secure */ 279 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 280 281 /* Return true if and only if GPIO bank @bank is registered as shared */ 282 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 283 284 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 285 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 286 287 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 288 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 289 290 #endif /*__STM32_UTIL_H__*/ 291