1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/stm32_bsec.h> 11 #include <kernel/panic.h> 12 #include <stdint.h> 13 #include <types_ext.h> 14 15 /* Backup registers and RAM utils */ 16 vaddr_t stm32mp_bkpreg(unsigned int idx); 17 18 /* Platform util for the GIC */ 19 vaddr_t get_gicc_base(void); 20 vaddr_t get_gicd_base(void); 21 22 /* 23 * Platform util functions for the GPIO driver 24 * @bank: Target GPIO bank ID as per DT bindings 25 * 26 * Platform shall implement these functions to provide to stm32_gpio 27 * driver the resource reference for a target GPIO bank. That are 28 * memory mapped interface base address, interface offset (see below) 29 * and clock identifier. 30 * 31 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 32 * check DT configuration matches platform implementation of the banks 33 * description. 34 */ 35 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 36 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 37 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 38 39 /* Power management service */ 40 #ifdef CFG_PSCI_ARM32 41 void stm32mp_register_online_cpu(void); 42 #else 43 static inline void stm32mp_register_online_cpu(void) 44 { 45 } 46 #endif 47 48 /* 49 * Generic spinlock function that bypass spinlock if MMU is disabled or 50 * lock is NULL. 51 */ 52 uint32_t may_spin_lock(unsigned int *lock); 53 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 54 55 /* 56 * Util for clock gating and to get clock rate for stm32 and platform drivers 57 * @id: Target clock ID, ID used in clock DT bindings 58 */ 59 void stm32_clock_enable(unsigned long id); 60 void stm32_clock_disable(unsigned long id); 61 unsigned long stm32_clock_get_rate(unsigned long id); 62 bool stm32_clock_is_enabled(unsigned long id); 63 64 /* 65 * Util for reset signal assertion/desassertion for stm32 and platform drivers 66 * @id: Target peripheral ID, ID used in reset DT bindings 67 * @to_us: Timeout out in microsecond, or 0 if not waiting signal state 68 */ 69 TEE_Result stm32_reset_assert(unsigned int id, unsigned int timeout_us); 70 TEE_Result stm32_reset_deassert(unsigned int id, unsigned int timeout_us); 71 72 static inline void stm32_reset_set(unsigned int id) 73 { 74 (void)stm32_reset_assert(id, 0); 75 } 76 77 static inline void stm32_reset_release(unsigned int id) 78 { 79 (void)stm32_reset_deassert(id, 0); 80 } 81 82 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 83 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 84 85 /* 86 * Structure and API function for BSEC driver to get some platform data. 87 * 88 * @base: BSEC interface registers physical base address 89 * @upper_start: Base ID for the BSEC upper words in the platform 90 * @max_id: Max value for BSEC word ID for the platform 91 * @closed_device_id: BSEC word ID storing the "closed_device" OTP bit 92 * @closed_device_position: Bit position of "closed_device" bit in the OTP word 93 */ 94 struct stm32_bsec_static_cfg { 95 paddr_t base; 96 unsigned int upper_start; 97 unsigned int max_id; 98 unsigned int closed_device_id; 99 unsigned int closed_device_position; 100 }; 101 102 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 103 104 /* 105 * Return true if platform is in closed_device mode 106 */ 107 bool stm32mp_is_closed_device(void); 108 109 /* 110 * Shared registers support: common lock for accessing SoC registers 111 * shared between several drivers. 112 */ 113 void io_mask32_stm32shregs(vaddr_t va, uint32_t value, uint32_t mask); 114 115 static inline void io_setbits32_stm32shregs(vaddr_t va, uint32_t value) 116 { 117 io_mask32_stm32shregs(va, value, value); 118 } 119 120 static inline void io_clrbits32_stm32shregs(vaddr_t va, uint32_t value) 121 { 122 io_mask32_stm32shregs(va, 0, value); 123 } 124 125 void io_clrsetbits32_stm32shregs(vaddr_t va, uint32_t clr, uint32_t set); 126 127 /* 128 * Shared reference counter: increments by 2 on secure increment 129 * request, decrements by 2 on secure decrement request. Bit #0 130 * is set to 1 on non-secure increment request and reset to 0 on 131 * non-secure decrement request. These counters initialize to 132 * either 0, 1 or 2 upon their expect default state. 133 * Counters saturate to UINT_MAX / 2. 134 */ 135 #define SHREFCNT_NONSECURE_FLAG 0x1ul 136 #define SHREFCNT_SECURE_STEP 0x2ul 137 #define SHREFCNT_MAX (UINT_MAX / 2) 138 139 /* Return 1 if refcnt increments from 0, else return 0 */ 140 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 141 { 142 int rc = !*refcnt; 143 144 if (secure) { 145 if (*refcnt < SHREFCNT_MAX) { 146 *refcnt += SHREFCNT_SECURE_STEP; 147 assert(*refcnt < SHREFCNT_MAX); 148 } 149 } else { 150 *refcnt |= SHREFCNT_NONSECURE_FLAG; 151 } 152 153 return rc; 154 } 155 156 /* Return 1 if refcnt decrements to 0, else return 0 */ 157 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 158 { 159 int rc = 0; 160 161 if (secure) { 162 if (*refcnt < SHREFCNT_MAX) { 163 if (*refcnt < SHREFCNT_SECURE_STEP) 164 panic(); 165 166 *refcnt -= SHREFCNT_SECURE_STEP; 167 rc = !*refcnt; 168 } 169 } else { 170 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 171 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 172 } 173 174 return rc; 175 } 176 177 static inline int incr_refcnt(unsigned int *refcnt) 178 { 179 return incr_shrefcnt(refcnt, true); 180 } 181 182 static inline int decr_refcnt(unsigned int *refcnt) 183 { 184 return decr_shrefcnt(refcnt, true); 185 } 186 187 /* 188 * Shared peripherals and resources registration 189 * 190 * Resources listed in enum stm32mp_shres assigned at run-time to the 191 * non-secure world, to the secure world or shared by both worlds. 192 * In the later case, there must exist a secure service in OP-TEE 193 * for the non-secure world to access the resource. 194 * 195 * Resources may be a peripheral, a bus, a clock or a memory. 196 * 197 * Shared resources driver API functions allows drivers to register the 198 * resource as secure, non-secure or shared and to get the resource 199 * assignation state. 200 */ 201 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 202 203 enum stm32mp_shres { 204 STM32MP1_SHRES_GPIOZ_0 = 0, 205 STM32MP1_SHRES_GPIOZ_1, 206 STM32MP1_SHRES_GPIOZ_2, 207 STM32MP1_SHRES_GPIOZ_3, 208 STM32MP1_SHRES_GPIOZ_4, 209 STM32MP1_SHRES_GPIOZ_5, 210 STM32MP1_SHRES_GPIOZ_6, 211 STM32MP1_SHRES_GPIOZ_7, 212 STM32MP1_SHRES_IWDG1, 213 STM32MP1_SHRES_USART1, 214 STM32MP1_SHRES_SPI6, 215 STM32MP1_SHRES_I2C4, 216 STM32MP1_SHRES_RNG1, 217 STM32MP1_SHRES_HASH1, 218 STM32MP1_SHRES_CRYP1, 219 STM32MP1_SHRES_I2C6, 220 STM32MP1_SHRES_RTC, 221 STM32MP1_SHRES_MCU, 222 STM32MP1_SHRES_HSI, 223 STM32MP1_SHRES_LSI, 224 STM32MP1_SHRES_HSE, 225 STM32MP1_SHRES_LSE, 226 STM32MP1_SHRES_CSI, 227 STM32MP1_SHRES_PLL1, 228 STM32MP1_SHRES_PLL1_P, 229 STM32MP1_SHRES_PLL1_Q, 230 STM32MP1_SHRES_PLL1_R, 231 STM32MP1_SHRES_PLL2, 232 STM32MP1_SHRES_PLL2_P, 233 STM32MP1_SHRES_PLL2_Q, 234 STM32MP1_SHRES_PLL2_R, 235 STM32MP1_SHRES_PLL3, 236 STM32MP1_SHRES_PLL3_P, 237 STM32MP1_SHRES_PLL3_Q, 238 STM32MP1_SHRES_PLL3_R, 239 STM32MP1_SHRES_MDMA, 240 STM32MP1_SHRES_COUNT 241 }; 242 243 /* Register resource @id as a secure peripheral */ 244 void stm32mp_register_secure_periph(enum stm32mp_shres id); 245 246 /* Register resource @id as a non-secure peripheral */ 247 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 248 249 /* 250 * Register resource identified by @base as a secure peripheral 251 * @base: IOMEM physical base address of the resource 252 */ 253 void stm32mp_register_secure_periph_iomem(vaddr_t base); 254 255 /* 256 * Register resource identified by @base as a non-secure peripheral 257 * @base: IOMEM physical base address of the resource 258 */ 259 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 260 261 /* 262 * Register GPIO resource as a secure peripheral 263 * @bank: Bank of the target GPIO 264 * @pin: Bit position of the target GPIO in the bank 265 */ 266 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 267 268 /* 269 * Register GPIO resource as a non-secure peripheral 270 * @bank: Bank of the target GPIO 271 * @pin: Bit position of the target GPIO in the bank 272 */ 273 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 274 275 /* Return true if and only if resource @id is registered as secure */ 276 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 277 278 /* Return true if and only if GPIO bank @bank is registered as secure */ 279 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 280 281 /* Return true if and only if GPIO bank @bank is registered as shared */ 282 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 283 284 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 285 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 286 287 /* Return true if and only if @clock_id is shareable */ 288 bool stm32mp_clock_is_shareable(unsigned long clock_id); 289 290 /* Return true if and only if @clock_id is shared by secure and non-secure */ 291 bool stm32mp_clock_is_shared(unsigned long clock_id); 292 293 /* Return true if and only if @clock_id is assigned to non-secure world */ 294 bool stm32mp_clock_is_non_secure(unsigned long clock_id); 295 296 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 297 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 298 299 #endif /*__STM32_UTIL_H__*/ 300