1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2022, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/stm32_bsec.h> 12 #include <kernel/panic.h> 13 #include <stdint.h> 14 #include <types_ext.h> 15 16 /* Backup registers and RAM utils */ 17 vaddr_t stm32mp_bkpreg(unsigned int idx); 18 19 /* 20 * SYSCFG IO compensation. 21 * These functions assume non-secure world is suspended. 22 */ 23 void stm32mp_syscfg_enable_io_compensation(void); 24 void stm32mp_syscfg_disable_io_compensation(void); 25 26 /* Platform util for the RCC drivers */ 27 vaddr_t stm32_rcc_base(void); 28 29 /* Platform util for the GIC */ 30 vaddr_t get_gicd_base(void); 31 32 /* 33 * Platform util functions for the GPIO driver 34 * @bank: Target GPIO bank ID as per DT bindings 35 * 36 * Platform shall implement these functions to provide to stm32_gpio 37 * driver the resource reference for a target GPIO bank. That are 38 * memory mapped interface base address, interface offset (see below) 39 * and clock identifier. 40 * 41 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 42 * check DT configuration matches platform implementation of the banks 43 * description. 44 */ 45 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 46 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 47 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 48 struct clk *stm32_get_gpio_bank_clk(unsigned int bank); 49 50 /* Platform util for PMIC support */ 51 bool stm32mp_with_pmic(void); 52 53 /* Power management service */ 54 #ifdef CFG_PSCI_ARM32 55 void stm32mp_register_online_cpu(void); 56 #else 57 static inline void stm32mp_register_online_cpu(void) 58 { 59 } 60 #endif 61 62 /* 63 * Generic spinlock function that bypass spinlock if MMU is disabled or 64 * lock is NULL. 65 */ 66 uint32_t may_spin_lock(unsigned int *lock); 67 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 68 69 /* Helper from platform RCC clock driver */ 70 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id); 71 72 #ifdef CFG_STM32MP1_SHARED_RESOURCES 73 /* Return true if @clock_id is shared by secure and non-secure worlds */ 74 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 75 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 76 static inline bool stm32mp_nsec_can_access_clock(unsigned long clock_id 77 __unused) 78 { 79 return true; 80 } 81 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 82 83 extern const struct clk_ops stm32mp1_clk_ops; 84 85 #if defined(CFG_STPMIC1) 86 /* Return true if non-secure world can manipulate regulator @pmic_regu_name */ 87 bool stm32mp_nsec_can_access_pmic_regu(const char *pmic_regu_name); 88 #else 89 static inline bool stm32mp_nsec_can_access_pmic_regu(const char *name __unused) 90 { 91 return false; 92 } 93 #endif 94 95 #ifdef CFG_STM32MP1_SHARED_RESOURCES 96 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 97 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 98 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 99 static inline bool stm32mp_nsec_can_access_reset(unsigned int reset_id __unused) 100 { 101 return true; 102 } 103 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 104 105 /* Return rstctrl instance related to RCC reset controller DT binding ID */ 106 struct rstctrl *stm32mp_rcc_reset_id_to_rstctrl(unsigned int binding_id); 107 108 /* 109 * Structure and API function for BSEC driver to get some platform data. 110 * 111 * @base: BSEC interface registers physical base address 112 * @upper_start: Base ID for the BSEC upper words in the platform 113 * @max_id: Max value for BSEC word ID for the platform 114 */ 115 struct stm32_bsec_static_cfg { 116 paddr_t base; 117 unsigned int upper_start; 118 unsigned int max_id; 119 }; 120 121 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 122 123 /* 124 * Shared reference counter: increments by 2 on secure increment 125 * request, decrements by 2 on secure decrement request. Bit #0 126 * is set to 1 on non-secure increment request and reset to 0 on 127 * non-secure decrement request. These counters initialize to 128 * either 0, 1 or 2 upon their expect default state. 129 * Counters saturate to UINT_MAX / 2. 130 */ 131 #define SHREFCNT_NONSECURE_FLAG 0x1ul 132 #define SHREFCNT_SECURE_STEP 0x2ul 133 #define SHREFCNT_MAX (UINT_MAX / 2) 134 135 /* Return 1 if refcnt increments from 0, else return 0 */ 136 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 137 { 138 int rc = !*refcnt; 139 140 if (secure) { 141 if (*refcnt < SHREFCNT_MAX) { 142 *refcnt += SHREFCNT_SECURE_STEP; 143 assert(*refcnt < SHREFCNT_MAX); 144 } 145 } else { 146 *refcnt |= SHREFCNT_NONSECURE_FLAG; 147 } 148 149 return rc; 150 } 151 152 /* Return 1 if refcnt decrements to 0, else return 0 */ 153 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 154 { 155 int rc = 0; 156 157 if (secure) { 158 if (*refcnt < SHREFCNT_MAX) { 159 if (*refcnt < SHREFCNT_SECURE_STEP) 160 panic(); 161 162 *refcnt -= SHREFCNT_SECURE_STEP; 163 rc = !*refcnt; 164 } 165 } else { 166 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 167 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 168 } 169 170 return rc; 171 } 172 173 static inline int incr_refcnt(unsigned int *refcnt) 174 { 175 return incr_shrefcnt(refcnt, true); 176 } 177 178 static inline int decr_refcnt(unsigned int *refcnt) 179 { 180 return decr_shrefcnt(refcnt, true); 181 } 182 183 /* 184 * Shared peripherals and resources registration 185 * 186 * Resources listed in enum stm32mp_shres assigned at run-time to the 187 * non-secure world, to the secure world or shared by both worlds. 188 * In the later case, there must exist a secure service in OP-TEE 189 * for the non-secure world to access the resource. 190 * 191 * Resources may be a peripheral, a bus, a clock or a memory. 192 * 193 * Shared resources driver API functions allows drivers to register the 194 * resource as secure, non-secure or shared and to get the resource 195 * assignation state. 196 */ 197 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 198 199 enum stm32mp_shres { 200 STM32MP1_SHRES_GPIOZ_0 = 0, 201 STM32MP1_SHRES_GPIOZ_1, 202 STM32MP1_SHRES_GPIOZ_2, 203 STM32MP1_SHRES_GPIOZ_3, 204 STM32MP1_SHRES_GPIOZ_4, 205 STM32MP1_SHRES_GPIOZ_5, 206 STM32MP1_SHRES_GPIOZ_6, 207 STM32MP1_SHRES_GPIOZ_7, 208 STM32MP1_SHRES_IWDG1, 209 STM32MP1_SHRES_USART1, 210 STM32MP1_SHRES_SPI6, 211 STM32MP1_SHRES_I2C4, 212 STM32MP1_SHRES_RNG1, 213 STM32MP1_SHRES_HASH1, 214 STM32MP1_SHRES_CRYP1, 215 STM32MP1_SHRES_I2C6, 216 STM32MP1_SHRES_RTC, 217 STM32MP1_SHRES_MCU, 218 STM32MP1_SHRES_PLL3, 219 STM32MP1_SHRES_MDMA, 220 221 STM32MP1_SHRES_COUNT 222 }; 223 224 #ifdef CFG_STM32MP1_SHARED_RESOURCES 225 /* Register resource @id as a secure peripheral */ 226 void stm32mp_register_secure_periph(enum stm32mp_shres id); 227 228 /* Register resource @id as a non-secure peripheral */ 229 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 230 231 /* 232 * Register resource identified by @base as a secure peripheral 233 * @base: IOMEM physical base address of the resource 234 */ 235 void stm32mp_register_secure_periph_iomem(vaddr_t base); 236 237 /* 238 * Register resource identified by @base as a non-secure peripheral 239 * @base: IOMEM physical base address of the resource 240 */ 241 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 242 243 /* 244 * Register GPIO resource as a secure peripheral 245 * @bank: Bank of the target GPIO 246 * @pin: Bit position of the target GPIO in the bank 247 */ 248 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 249 250 /* 251 * Register GPIO resource as a non-secure peripheral 252 * @bank: Bank of the target GPIO 253 * @pin: Bit position of the target GPIO in the bank 254 */ 255 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 256 257 /* Return true if and only if resource @id is registered as secure */ 258 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 259 260 /* Return true if and only if GPIO bank @bank is registered as secure */ 261 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 262 263 /* Return true if and only if GPIO bank @bank is registered as shared */ 264 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 265 266 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 267 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 268 269 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 270 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 271 272 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 273 274 static inline void stm32mp_register_secure_periph(enum stm32mp_shres id 275 __unused) 276 { 277 } 278 279 static inline void stm32mp_register_non_secure_periph(enum stm32mp_shres id 280 __unused) 281 { 282 } 283 284 static inline void stm32mp_register_secure_periph_iomem(vaddr_t base __unused) 285 { 286 } 287 288 static inline void stm32mp_register_non_secure_periph_iomem(vaddr_t base 289 __unused) 290 { 291 } 292 293 static inline void stm32mp_register_secure_gpio(unsigned int bank __unused, 294 unsigned int pin __unused) 295 { 296 } 297 298 static inline void stm32mp_register_non_secure_gpio(unsigned int bank __unused, 299 unsigned int pin __unused) 300 { 301 } 302 303 static inline bool stm32mp_periph_is_secure(enum stm32mp_shres id __unused) 304 { 305 return true; 306 } 307 308 static inline bool stm32mp_gpio_bank_is_secure(unsigned int bank __unused) 309 { 310 return true; 311 } 312 313 static inline bool stm32mp_gpio_bank_is_shared(unsigned int bank __unused) 314 { 315 return false; 316 } 317 318 static inline bool stm32mp_gpio_bank_is_non_secure(unsigned int bank __unused) 319 { 320 return false; 321 } 322 323 static inline void stm32mp_register_clock_parents_secure(unsigned long clock_id 324 __unused) 325 { 326 } 327 328 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 329 #endif /*__STM32_UTIL_H__*/ 330