1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/stm32_bsec.h> 12 #include <kernel/panic.h> 13 #include <stdint.h> 14 #include <types_ext.h> 15 16 /* Backup registers and RAM utils */ 17 vaddr_t stm32mp_bkpreg(unsigned int idx); 18 19 /* 20 * SYSCFG IO compensation. 21 * These functions assume non-secure world is suspended. 22 */ 23 void stm32mp_syscfg_enable_io_compensation(void); 24 void stm32mp_syscfg_disable_io_compensation(void); 25 26 /* Platform util for the GIC */ 27 vaddr_t get_gicc_base(void); 28 vaddr_t get_gicd_base(void); 29 30 /* 31 * Platform util functions for the GPIO driver 32 * @bank: Target GPIO bank ID as per DT bindings 33 * 34 * Platform shall implement these functions to provide to stm32_gpio 35 * driver the resource reference for a target GPIO bank. That are 36 * memory mapped interface base address, interface offset (see below) 37 * and clock identifier. 38 * 39 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 40 * check DT configuration matches platform implementation of the banks 41 * description. 42 */ 43 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 44 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 45 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 46 struct clk *stm32_get_gpio_bank_clk(unsigned int bank); 47 48 /* Platform util for PMIC support */ 49 bool stm32mp_with_pmic(void); 50 51 /* Power management service */ 52 #ifdef CFG_PSCI_ARM32 53 void stm32mp_register_online_cpu(void); 54 #else 55 static inline void stm32mp_register_online_cpu(void) 56 { 57 } 58 #endif 59 60 /* 61 * Generic spinlock function that bypass spinlock if MMU is disabled or 62 * lock is NULL. 63 */ 64 uint32_t may_spin_lock(unsigned int *lock); 65 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 66 67 /* 68 * Util for clock gating and to get clock rate for stm32 and platform drivers 69 * @id: Target clock ID, ID used in clock DT bindings 70 */ 71 void stm32_clock_enable(unsigned long id); 72 void stm32_clock_disable(unsigned long id); 73 unsigned long stm32_clock_get_rate(unsigned long id); 74 bool stm32_clock_is_enabled(unsigned long id); 75 76 /* Helper from platform RCC clock driver */ 77 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id); 78 79 /* Return true if @clock_id is shared by secure and non-secure worlds */ 80 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 81 82 extern const struct clk_ops stm32mp1_clk_ops; 83 84 #if defined(CFG_STPMIC1) 85 /* Return true if non-secure world can manipulate regulator @pmic_regu_name */ 86 bool stm32mp_nsec_can_access_pmic_regu(const char *pmic_regu_name); 87 #else 88 static inline bool stm32mp_nsec_can_access_pmic_regu(const char *name __unused) 89 { 90 return false; 91 } 92 #endif 93 94 /* 95 * Util for reset signal assertion/desassertion for stm32 and platform drivers 96 * @id: Target peripheral ID, ID used in reset DT bindings 97 * @to_us: Timeout out in microsecond, or 0 if not waiting signal state 98 */ 99 TEE_Result stm32_reset_assert(unsigned int id, unsigned int timeout_us); 100 TEE_Result stm32_reset_deassert(unsigned int id, unsigned int timeout_us); 101 102 /* Specific reset to manage the MCU hold boot */ 103 void stm32_reset_assert_deassert_mcu(bool assert_not_deassert); 104 105 static inline void stm32_reset_set(unsigned int id) 106 { 107 (void)stm32_reset_assert(id, 0); 108 } 109 110 static inline void stm32_reset_release(unsigned int id) 111 { 112 (void)stm32_reset_deassert(id, 0); 113 } 114 115 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 116 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 117 118 /* 119 * Structure and API function for BSEC driver to get some platform data. 120 * 121 * @base: BSEC interface registers physical base address 122 * @upper_start: Base ID for the BSEC upper words in the platform 123 * @max_id: Max value for BSEC word ID for the platform 124 */ 125 struct stm32_bsec_static_cfg { 126 paddr_t base; 127 unsigned int upper_start; 128 unsigned int max_id; 129 }; 130 131 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 132 133 /* 134 * Return true if platform is in closed_device mode 135 */ 136 bool stm32mp_is_closed_device(void); 137 138 /* 139 * Shared registers support: common lock for accessing SoC registers 140 * shared between several drivers. 141 */ 142 void io_mask32_stm32shregs(vaddr_t va, uint32_t value, uint32_t mask); 143 144 static inline void io_setbits32_stm32shregs(vaddr_t va, uint32_t value) 145 { 146 io_mask32_stm32shregs(va, value, value); 147 } 148 149 static inline void io_clrbits32_stm32shregs(vaddr_t va, uint32_t value) 150 { 151 io_mask32_stm32shregs(va, 0, value); 152 } 153 154 void io_clrsetbits32_stm32shregs(vaddr_t va, uint32_t clr, uint32_t set); 155 156 /* 157 * Shared reference counter: increments by 2 on secure increment 158 * request, decrements by 2 on secure decrement request. Bit #0 159 * is set to 1 on non-secure increment request and reset to 0 on 160 * non-secure decrement request. These counters initialize to 161 * either 0, 1 or 2 upon their expect default state. 162 * Counters saturate to UINT_MAX / 2. 163 */ 164 #define SHREFCNT_NONSECURE_FLAG 0x1ul 165 #define SHREFCNT_SECURE_STEP 0x2ul 166 #define SHREFCNT_MAX (UINT_MAX / 2) 167 168 /* Return 1 if refcnt increments from 0, else return 0 */ 169 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 170 { 171 int rc = !*refcnt; 172 173 if (secure) { 174 if (*refcnt < SHREFCNT_MAX) { 175 *refcnt += SHREFCNT_SECURE_STEP; 176 assert(*refcnt < SHREFCNT_MAX); 177 } 178 } else { 179 *refcnt |= SHREFCNT_NONSECURE_FLAG; 180 } 181 182 return rc; 183 } 184 185 /* Return 1 if refcnt decrements to 0, else return 0 */ 186 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 187 { 188 int rc = 0; 189 190 if (secure) { 191 if (*refcnt < SHREFCNT_MAX) { 192 if (*refcnt < SHREFCNT_SECURE_STEP) 193 panic(); 194 195 *refcnt -= SHREFCNT_SECURE_STEP; 196 rc = !*refcnt; 197 } 198 } else { 199 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 200 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 201 } 202 203 return rc; 204 } 205 206 static inline int incr_refcnt(unsigned int *refcnt) 207 { 208 return incr_shrefcnt(refcnt, true); 209 } 210 211 static inline int decr_refcnt(unsigned int *refcnt) 212 { 213 return decr_shrefcnt(refcnt, true); 214 } 215 216 /* 217 * Shared peripherals and resources registration 218 * 219 * Resources listed in enum stm32mp_shres assigned at run-time to the 220 * non-secure world, to the secure world or shared by both worlds. 221 * In the later case, there must exist a secure service in OP-TEE 222 * for the non-secure world to access the resource. 223 * 224 * Resources may be a peripheral, a bus, a clock or a memory. 225 * 226 * Shared resources driver API functions allows drivers to register the 227 * resource as secure, non-secure or shared and to get the resource 228 * assignation state. 229 */ 230 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 231 232 enum stm32mp_shres { 233 STM32MP1_SHRES_GPIOZ_0 = 0, 234 STM32MP1_SHRES_GPIOZ_1, 235 STM32MP1_SHRES_GPIOZ_2, 236 STM32MP1_SHRES_GPIOZ_3, 237 STM32MP1_SHRES_GPIOZ_4, 238 STM32MP1_SHRES_GPIOZ_5, 239 STM32MP1_SHRES_GPIOZ_6, 240 STM32MP1_SHRES_GPIOZ_7, 241 STM32MP1_SHRES_IWDG1, 242 STM32MP1_SHRES_USART1, 243 STM32MP1_SHRES_SPI6, 244 STM32MP1_SHRES_I2C4, 245 STM32MP1_SHRES_RNG1, 246 STM32MP1_SHRES_HASH1, 247 STM32MP1_SHRES_CRYP1, 248 STM32MP1_SHRES_I2C6, 249 STM32MP1_SHRES_RTC, 250 STM32MP1_SHRES_MCU, 251 STM32MP1_SHRES_PLL3, 252 STM32MP1_SHRES_MDMA, 253 254 STM32MP1_SHRES_COUNT 255 }; 256 257 /* Register resource @id as a secure peripheral */ 258 void stm32mp_register_secure_periph(enum stm32mp_shres id); 259 260 /* Register resource @id as a non-secure peripheral */ 261 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 262 263 /* 264 * Register resource identified by @base as a secure peripheral 265 * @base: IOMEM physical base address of the resource 266 */ 267 void stm32mp_register_secure_periph_iomem(vaddr_t base); 268 269 /* 270 * Register resource identified by @base as a non-secure peripheral 271 * @base: IOMEM physical base address of the resource 272 */ 273 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 274 275 /* 276 * Register GPIO resource as a secure peripheral 277 * @bank: Bank of the target GPIO 278 * @pin: Bit position of the target GPIO in the bank 279 */ 280 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 281 282 /* 283 * Register GPIO resource as a non-secure peripheral 284 * @bank: Bank of the target GPIO 285 * @pin: Bit position of the target GPIO in the bank 286 */ 287 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 288 289 /* Return true if and only if resource @id is registered as secure */ 290 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 291 292 /* Return true if and only if GPIO bank @bank is registered as secure */ 293 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 294 295 /* Return true if and only if GPIO bank @bank is registered as shared */ 296 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 297 298 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 299 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 300 301 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 302 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 303 304 #endif /*__STM32_UTIL_H__*/ 305