1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/stm32_bsec.h> 12 #include <kernel/panic.h> 13 #include <stdint.h> 14 #include <types_ext.h> 15 16 /* Backup registers and RAM utils */ 17 vaddr_t stm32mp_bkpreg(unsigned int idx); 18 19 /* 20 * SYSCFG IO compensation. 21 * These functions assume non-secure world is suspended. 22 */ 23 void stm32mp_syscfg_enable_io_compensation(void); 24 void stm32mp_syscfg_disable_io_compensation(void); 25 26 /* Platform util for the RCC drivers */ 27 vaddr_t stm32_rcc_base(void); 28 29 /* Platform util for the GIC */ 30 vaddr_t get_gicd_base(void); 31 32 /* 33 * Platform util functions for the GPIO driver 34 * @bank: Target GPIO bank ID as per DT bindings 35 * 36 * Platform shall implement these functions to provide to stm32_gpio 37 * driver the resource reference for a target GPIO bank. That are 38 * memory mapped interface base address, interface offset (see below) 39 * and clock identifier. 40 * 41 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 42 * check DT configuration matches platform implementation of the banks 43 * description. 44 */ 45 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 46 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 47 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 48 struct clk *stm32_get_gpio_bank_clk(unsigned int bank); 49 50 /* Platform util for PMIC support */ 51 bool stm32mp_with_pmic(void); 52 53 /* Power management service */ 54 #ifdef CFG_PSCI_ARM32 55 void stm32mp_register_online_cpu(void); 56 #else 57 static inline void stm32mp_register_online_cpu(void) 58 { 59 } 60 #endif 61 62 /* 63 * Generic spinlock function that bypass spinlock if MMU is disabled or 64 * lock is NULL. 65 */ 66 uint32_t may_spin_lock(unsigned int *lock); 67 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 68 69 /* Helper from platform RCC clock driver */ 70 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id); 71 72 /* Return true if @clock_id is shared by secure and non-secure worlds */ 73 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 74 75 extern const struct clk_ops stm32mp1_clk_ops; 76 77 #if defined(CFG_STPMIC1) 78 /* Return true if non-secure world can manipulate regulator @pmic_regu_name */ 79 bool stm32mp_nsec_can_access_pmic_regu(const char *pmic_regu_name); 80 #else 81 static inline bool stm32mp_nsec_can_access_pmic_regu(const char *name __unused) 82 { 83 return false; 84 } 85 #endif 86 87 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 88 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 89 90 /* Return rstctrl instance related to RCC reset controller DT binding ID */ 91 struct rstctrl *stm32mp_rcc_reset_id_to_rstctrl(unsigned int binding_id); 92 93 /* 94 * Structure and API function for BSEC driver to get some platform data. 95 * 96 * @base: BSEC interface registers physical base address 97 * @upper_start: Base ID for the BSEC upper words in the platform 98 * @max_id: Max value for BSEC word ID for the platform 99 */ 100 struct stm32_bsec_static_cfg { 101 paddr_t base; 102 unsigned int upper_start; 103 unsigned int max_id; 104 }; 105 106 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 107 108 /* 109 * Return true if platform is in closed_device mode 110 */ 111 bool stm32mp_is_closed_device(void); 112 113 /* 114 * Shared registers support: common lock for accessing SoC registers 115 * shared between several drivers. 116 */ 117 void io_mask32_stm32shregs(vaddr_t va, uint32_t value, uint32_t mask); 118 119 static inline void io_setbits32_stm32shregs(vaddr_t va, uint32_t value) 120 { 121 io_mask32_stm32shregs(va, value, value); 122 } 123 124 static inline void io_clrbits32_stm32shregs(vaddr_t va, uint32_t value) 125 { 126 io_mask32_stm32shregs(va, 0, value); 127 } 128 129 void io_clrsetbits32_stm32shregs(vaddr_t va, uint32_t clr, uint32_t set); 130 131 /* 132 * Shared reference counter: increments by 2 on secure increment 133 * request, decrements by 2 on secure decrement request. Bit #0 134 * is set to 1 on non-secure increment request and reset to 0 on 135 * non-secure decrement request. These counters initialize to 136 * either 0, 1 or 2 upon their expect default state. 137 * Counters saturate to UINT_MAX / 2. 138 */ 139 #define SHREFCNT_NONSECURE_FLAG 0x1ul 140 #define SHREFCNT_SECURE_STEP 0x2ul 141 #define SHREFCNT_MAX (UINT_MAX / 2) 142 143 /* Return 1 if refcnt increments from 0, else return 0 */ 144 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 145 { 146 int rc = !*refcnt; 147 148 if (secure) { 149 if (*refcnt < SHREFCNT_MAX) { 150 *refcnt += SHREFCNT_SECURE_STEP; 151 assert(*refcnt < SHREFCNT_MAX); 152 } 153 } else { 154 *refcnt |= SHREFCNT_NONSECURE_FLAG; 155 } 156 157 return rc; 158 } 159 160 /* Return 1 if refcnt decrements to 0, else return 0 */ 161 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 162 { 163 int rc = 0; 164 165 if (secure) { 166 if (*refcnt < SHREFCNT_MAX) { 167 if (*refcnt < SHREFCNT_SECURE_STEP) 168 panic(); 169 170 *refcnt -= SHREFCNT_SECURE_STEP; 171 rc = !*refcnt; 172 } 173 } else { 174 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 175 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 176 } 177 178 return rc; 179 } 180 181 static inline int incr_refcnt(unsigned int *refcnt) 182 { 183 return incr_shrefcnt(refcnt, true); 184 } 185 186 static inline int decr_refcnt(unsigned int *refcnt) 187 { 188 return decr_shrefcnt(refcnt, true); 189 } 190 191 /* 192 * Shared peripherals and resources registration 193 * 194 * Resources listed in enum stm32mp_shres assigned at run-time to the 195 * non-secure world, to the secure world or shared by both worlds. 196 * In the later case, there must exist a secure service in OP-TEE 197 * for the non-secure world to access the resource. 198 * 199 * Resources may be a peripheral, a bus, a clock or a memory. 200 * 201 * Shared resources driver API functions allows drivers to register the 202 * resource as secure, non-secure or shared and to get the resource 203 * assignation state. 204 */ 205 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 206 207 enum stm32mp_shres { 208 STM32MP1_SHRES_GPIOZ_0 = 0, 209 STM32MP1_SHRES_GPIOZ_1, 210 STM32MP1_SHRES_GPIOZ_2, 211 STM32MP1_SHRES_GPIOZ_3, 212 STM32MP1_SHRES_GPIOZ_4, 213 STM32MP1_SHRES_GPIOZ_5, 214 STM32MP1_SHRES_GPIOZ_6, 215 STM32MP1_SHRES_GPIOZ_7, 216 STM32MP1_SHRES_IWDG1, 217 STM32MP1_SHRES_USART1, 218 STM32MP1_SHRES_SPI6, 219 STM32MP1_SHRES_I2C4, 220 STM32MP1_SHRES_RNG1, 221 STM32MP1_SHRES_HASH1, 222 STM32MP1_SHRES_CRYP1, 223 STM32MP1_SHRES_I2C6, 224 STM32MP1_SHRES_RTC, 225 STM32MP1_SHRES_MCU, 226 STM32MP1_SHRES_PLL3, 227 STM32MP1_SHRES_MDMA, 228 229 STM32MP1_SHRES_COUNT 230 }; 231 232 /* Register resource @id as a secure peripheral */ 233 void stm32mp_register_secure_periph(enum stm32mp_shres id); 234 235 /* Register resource @id as a non-secure peripheral */ 236 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 237 238 /* 239 * Register resource identified by @base as a secure peripheral 240 * @base: IOMEM physical base address of the resource 241 */ 242 void stm32mp_register_secure_periph_iomem(vaddr_t base); 243 244 /* 245 * Register resource identified by @base as a non-secure peripheral 246 * @base: IOMEM physical base address of the resource 247 */ 248 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 249 250 /* 251 * Register GPIO resource as a secure peripheral 252 * @bank: Bank of the target GPIO 253 * @pin: Bit position of the target GPIO in the bank 254 */ 255 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 256 257 /* 258 * Register GPIO resource as a non-secure peripheral 259 * @bank: Bank of the target GPIO 260 * @pin: Bit position of the target GPIO in the bank 261 */ 262 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 263 264 /* Return true if and only if resource @id is registered as secure */ 265 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 266 267 /* Return true if and only if GPIO bank @bank is registered as secure */ 268 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 269 270 /* Return true if and only if GPIO bank @bank is registered as shared */ 271 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 272 273 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 274 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 275 276 #if defined(CFG_STM32MP15) 277 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 278 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 279 #else 280 static inline void stm32mp_register_clock_parents_secure(unsigned long clock_id 281 __unused) 282 { 283 } 284 #endif 285 286 #endif /*__STM32_UTIL_H__*/ 287