1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/stm32_bsec.h> 11 #include <kernel/panic.h> 12 #include <stdint.h> 13 #include <types_ext.h> 14 15 /* Backup registers and RAM utils */ 16 vaddr_t stm32mp_bkpreg(unsigned int idx); 17 18 /* Platform util for the GIC */ 19 vaddr_t get_gicc_base(void); 20 vaddr_t get_gicd_base(void); 21 22 /* 23 * Platform util functions for the GPIO driver 24 * @bank: Target GPIO bank ID as per DT bindings 25 * 26 * Platform shall implement these functions to provide to stm32_gpio 27 * driver the resource reference for a target GPIO bank. That are 28 * memory mapped interface base address, interface offset (see below) 29 * and clock identifier. 30 * 31 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 32 * check DT configuration matches platform implementation of the banks 33 * description. 34 */ 35 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 36 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 37 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 38 39 /* Power management service */ 40 #ifdef CFG_PSCI_ARM32 41 void stm32mp_register_online_cpu(void); 42 #else 43 static inline void stm32mp_register_online_cpu(void) 44 { 45 } 46 #endif 47 48 /* 49 * Generic spinlock function that bypass spinlock if MMU is disabled or 50 * lock is NULL. 51 */ 52 uint32_t may_spin_lock(unsigned int *lock); 53 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 54 55 /* 56 * Util for clock gating and to get clock rate for stm32 and platform drivers 57 * @id: Target clock ID, ID used in clock DT bindings 58 */ 59 void stm32_clock_enable(unsigned long id); 60 void stm32_clock_disable(unsigned long id); 61 unsigned long stm32_clock_get_rate(unsigned long id); 62 bool stm32_clock_is_enabled(unsigned long id); 63 64 /* 65 * Util for reset signal assertion/desassertion for stm32 and platform drivers 66 * @id: Target peripheral ID, ID used in reset DT bindings 67 */ 68 void stm32_reset_assert(unsigned int id); 69 void stm32_reset_deassert(unsigned int id); 70 71 /* 72 * Structure and API function for BSEC driver to get some platform data. 73 * 74 * @base: BSEC interface registers physical base address 75 * @upper_start: Base ID for the BSEC upper words in the platform 76 * @max_id: Max value for BSEC word ID for the platform 77 * @closed_device_id: BSEC word ID storing the "closed_device" OTP bit 78 * @closed_device_position: Bit position of "closed_device" bit in the OTP word 79 */ 80 struct stm32_bsec_static_cfg { 81 paddr_t base; 82 unsigned int upper_start; 83 unsigned int max_id; 84 unsigned int closed_device_id; 85 unsigned int closed_device_position; 86 }; 87 88 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 89 90 /* 91 * Shared reference counter: increments by 2 on secure increment 92 * request, decrements by 2 on secure decrement request. Bit #0 93 * is set to 1 on non-secure increment request and reset to 0 on 94 * non-secure decrement request. These counters initialize to 95 * either 0, 1 or 2 upon their expect default state. 96 * Counters saturate to UINT_MAX / 2. 97 */ 98 #define SHREFCNT_NONSECURE_FLAG 0x1ul 99 #define SHREFCNT_SECURE_STEP 0x2ul 100 #define SHREFCNT_MAX (UINT_MAX / 2) 101 102 /* Return 1 if refcnt increments from 0, else return 0 */ 103 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 104 { 105 int rc = !*refcnt; 106 107 if (secure) { 108 if (*refcnt < SHREFCNT_MAX) { 109 *refcnt += SHREFCNT_SECURE_STEP; 110 assert(*refcnt < SHREFCNT_MAX); 111 } 112 } else { 113 *refcnt |= SHREFCNT_NONSECURE_FLAG; 114 } 115 116 return rc; 117 } 118 119 /* Return 1 if refcnt decrements to 0, else return 0 */ 120 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 121 { 122 int rc = 0; 123 124 if (secure) { 125 if (*refcnt < SHREFCNT_MAX) { 126 if (*refcnt < SHREFCNT_SECURE_STEP) 127 panic(); 128 129 *refcnt -= SHREFCNT_SECURE_STEP; 130 rc = !*refcnt; 131 } 132 } else { 133 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 134 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 135 } 136 137 return rc; 138 } 139 140 static inline int incr_refcnt(unsigned int *refcnt) 141 { 142 return incr_shrefcnt(refcnt, true); 143 } 144 145 static inline int decr_refcnt(unsigned int *refcnt) 146 { 147 return decr_shrefcnt(refcnt, true); 148 } 149 150 /* 151 * Shared peripherals and resources registration 152 * 153 * Resources listed in enum stm32mp_shres assigned at run-time to the 154 * non-secure world, to the secure world or shared by both worlds. 155 * In the later case, there must exist a secure service in OP-TEE 156 * for the non-secure world to access the resource. 157 * 158 * Resources may be a peripheral, a bus, a clock or a memory. 159 * 160 * Shared resources driver API functions allows drivers to register the 161 * resource as secure, non-secure or shared and to get the resource 162 * assignation state. 163 */ 164 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 165 166 enum stm32mp_shres { 167 STM32MP1_SHRES_GPIOZ_0 = 0, 168 STM32MP1_SHRES_GPIOZ_1, 169 STM32MP1_SHRES_GPIOZ_2, 170 STM32MP1_SHRES_GPIOZ_3, 171 STM32MP1_SHRES_GPIOZ_4, 172 STM32MP1_SHRES_GPIOZ_5, 173 STM32MP1_SHRES_GPIOZ_6, 174 STM32MP1_SHRES_GPIOZ_7, 175 STM32MP1_SHRES_IWDG1, 176 STM32MP1_SHRES_USART1, 177 STM32MP1_SHRES_SPI6, 178 STM32MP1_SHRES_I2C4, 179 STM32MP1_SHRES_RNG1, 180 STM32MP1_SHRES_HASH1, 181 STM32MP1_SHRES_CRYP1, 182 STM32MP1_SHRES_I2C6, 183 STM32MP1_SHRES_RTC, 184 STM32MP1_SHRES_MCU, 185 STM32MP1_SHRES_HSI, 186 STM32MP1_SHRES_LSI, 187 STM32MP1_SHRES_HSE, 188 STM32MP1_SHRES_LSE, 189 STM32MP1_SHRES_CSI, 190 STM32MP1_SHRES_PLL1, 191 STM32MP1_SHRES_PLL1_P, 192 STM32MP1_SHRES_PLL1_Q, 193 STM32MP1_SHRES_PLL1_R, 194 STM32MP1_SHRES_PLL2, 195 STM32MP1_SHRES_PLL2_P, 196 STM32MP1_SHRES_PLL2_Q, 197 STM32MP1_SHRES_PLL2_R, 198 STM32MP1_SHRES_PLL3, 199 STM32MP1_SHRES_PLL3_P, 200 STM32MP1_SHRES_PLL3_Q, 201 STM32MP1_SHRES_PLL3_R, 202 STM32MP1_SHRES_COUNT 203 }; 204 205 /* Register resource @id as a secure peripheral */ 206 void stm32mp_register_secure_periph(enum stm32mp_shres id); 207 208 /* Register resource @id as a non-secure peripheral */ 209 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 210 211 /* 212 * Register resource identified by @base as a secure peripheral 213 * @base: IOMEM physical base address of the resource 214 */ 215 void stm32mp_register_secure_periph_iomem(vaddr_t base); 216 217 /* 218 * Register resource identified by @base as a non-secure peripheral 219 * @base: IOMEM physical base address of the resource 220 */ 221 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 222 223 /* 224 * Register GPIO resource as a secure peripheral 225 * @bank: Bank of the target GPIO 226 * @pin: Bit position of the target GPIO in the bank 227 */ 228 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 229 230 /* 231 * Register GPIO resource as a non-secure peripheral 232 * @bank: Bank of the target GPIO 233 * @pin: Bit position of the target GPIO in the bank 234 */ 235 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 236 237 /* Return true if and only if resource @id is registered as secure */ 238 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 239 240 /* Return true if and only if the resource @id is registered as non-secure */ 241 bool stm32mp_periph_is_non_secure(enum stm32mp_shres id); 242 243 /* Return true if and only if the resource @id is not registered */ 244 bool stm32mp_periph_is_unregistered(enum stm32mp_shres id); 245 246 /* Return true if and only if GPIO bank @bank is registered as secure */ 247 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 248 249 /* Return true if and only if GPIO bank @bank is registered as shared */ 250 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 251 252 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 253 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 254 255 /* Return true if and only if @clock_id is shareable */ 256 bool stm32mp_clock_is_shareable(unsigned long clock_id); 257 258 /* Return true if and only if @clock_id is shared by secure and non-secure */ 259 bool stm32mp_clock_is_shared(unsigned long clock_id); 260 261 /* Return true if and only if @clock_id is assigned to non-secure world */ 262 bool stm32mp_clock_is_non_secure(unsigned long clock_id); 263 264 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 265 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 266 267 #endif /*__STM32_UTIL_H__*/ 268