1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2022, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/stm32_bsec.h> 12 #include <kernel/panic.h> 13 #include <stdint.h> 14 #include <types_ext.h> 15 16 /* Backup registers and RAM utils */ 17 vaddr_t stm32mp_bkpreg(unsigned int idx); 18 19 /* 20 * SYSCFG IO compensation. 21 * These functions assume non-secure world is suspended. 22 */ 23 void stm32mp_syscfg_enable_io_compensation(void); 24 void stm32mp_syscfg_disable_io_compensation(void); 25 26 /* Platform util for the RCC drivers */ 27 vaddr_t stm32_rcc_base(void); 28 29 /* Platform util for the GIC */ 30 vaddr_t get_gicd_base(void); 31 32 /* 33 * Platform util functions for the GPIO driver 34 * @bank: Target GPIO bank ID as per DT bindings 35 * 36 * Platform shall implement these functions to provide to stm32_gpio 37 * driver the resource reference for a target GPIO bank. That are 38 * memory mapped interface base address, interface offset (see below) 39 * and clock identifier. 40 * 41 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 42 * check DT configuration matches platform implementation of the banks 43 * description. 44 */ 45 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 46 47 /* Platform util for PMIC support */ 48 bool stm32mp_with_pmic(void); 49 50 /* Power management service */ 51 #ifdef CFG_PSCI_ARM32 52 void stm32mp_register_online_cpu(void); 53 #else 54 static inline void stm32mp_register_online_cpu(void) 55 { 56 } 57 #endif 58 59 /* 60 * Generic spinlock function that bypass spinlock if MMU is disabled or 61 * lock is NULL. 62 */ 63 uint32_t may_spin_lock(unsigned int *lock); 64 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 65 66 /* Helper from platform RCC clock driver */ 67 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id); 68 69 #ifdef CFG_STM32MP1_SHARED_RESOURCES 70 /* Return true if @clock_id is shared by secure and non-secure worlds */ 71 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 72 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 73 static inline bool stm32mp_nsec_can_access_clock(unsigned long clock_id 74 __unused) 75 { 76 return true; 77 } 78 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 79 80 extern const struct clk_ops stm32mp1_clk_ops; 81 82 #if defined(CFG_STPMIC1) 83 /* Return true if non-secure world can manipulate regulator @pmic_regu_name */ 84 bool stm32mp_nsec_can_access_pmic_regu(const char *pmic_regu_name); 85 #else 86 static inline bool stm32mp_nsec_can_access_pmic_regu(const char *name __unused) 87 { 88 return false; 89 } 90 #endif 91 92 #ifdef CFG_STM32MP1_SHARED_RESOURCES 93 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 94 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 95 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 96 static inline bool stm32mp_nsec_can_access_reset(unsigned int reset_id __unused) 97 { 98 return true; 99 } 100 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 101 102 /* Return rstctrl instance related to RCC reset controller DT binding ID */ 103 struct rstctrl *stm32mp_rcc_reset_id_to_rstctrl(unsigned int binding_id); 104 105 /* 106 * Structure and API function for BSEC driver to get some platform data. 107 * 108 * @base: BSEC interface registers physical base address 109 * @upper_start: Base ID for the BSEC upper words in the platform 110 * @max_id: Max value for BSEC word ID for the platform 111 */ 112 struct stm32_bsec_static_cfg { 113 paddr_t base; 114 unsigned int upper_start; 115 unsigned int max_id; 116 }; 117 118 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 119 120 /* 121 * Shared reference counter: increments by 2 on secure increment 122 * request, decrements by 2 on secure decrement request. Bit #0 123 * is set to 1 on non-secure increment request and reset to 0 on 124 * non-secure decrement request. These counters initialize to 125 * either 0, 1 or 2 upon their expect default state. 126 * Counters saturate to UINT_MAX / 2. 127 */ 128 #define SHREFCNT_NONSECURE_FLAG 0x1ul 129 #define SHREFCNT_SECURE_STEP 0x2ul 130 #define SHREFCNT_MAX (UINT_MAX / 2) 131 132 /* Return 1 if refcnt increments from 0, else return 0 */ 133 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 134 { 135 int rc = !*refcnt; 136 137 if (secure) { 138 if (*refcnt < SHREFCNT_MAX) { 139 *refcnt += SHREFCNT_SECURE_STEP; 140 assert(*refcnt < SHREFCNT_MAX); 141 } 142 } else { 143 *refcnt |= SHREFCNT_NONSECURE_FLAG; 144 } 145 146 return rc; 147 } 148 149 /* Return 1 if refcnt decrements to 0, else return 0 */ 150 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 151 { 152 int rc = 0; 153 154 if (secure) { 155 if (*refcnt < SHREFCNT_MAX) { 156 if (*refcnt < SHREFCNT_SECURE_STEP) 157 panic(); 158 159 *refcnt -= SHREFCNT_SECURE_STEP; 160 rc = !*refcnt; 161 } 162 } else { 163 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 164 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 165 } 166 167 return rc; 168 } 169 170 static inline int incr_refcnt(unsigned int *refcnt) 171 { 172 return incr_shrefcnt(refcnt, true); 173 } 174 175 static inline int decr_refcnt(unsigned int *refcnt) 176 { 177 return decr_shrefcnt(refcnt, true); 178 } 179 180 /* 181 * Shared peripherals and resources registration 182 * 183 * Resources listed in enum stm32mp_shres assigned at run-time to the 184 * non-secure world, to the secure world or shared by both worlds. 185 * In the later case, there must exist a secure service in OP-TEE 186 * for the non-secure world to access the resource. 187 * 188 * Resources may be a peripheral, a bus, a clock or a memory. 189 * 190 * Shared resources driver API functions allows drivers to register the 191 * resource as secure, non-secure or shared and to get the resource 192 * assignation state. 193 */ 194 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 195 196 enum stm32mp_shres { 197 STM32MP1_SHRES_GPIOZ_0 = 0, 198 STM32MP1_SHRES_GPIOZ_1, 199 STM32MP1_SHRES_GPIOZ_2, 200 STM32MP1_SHRES_GPIOZ_3, 201 STM32MP1_SHRES_GPIOZ_4, 202 STM32MP1_SHRES_GPIOZ_5, 203 STM32MP1_SHRES_GPIOZ_6, 204 STM32MP1_SHRES_GPIOZ_7, 205 STM32MP1_SHRES_IWDG1, 206 STM32MP1_SHRES_USART1, 207 STM32MP1_SHRES_SPI6, 208 STM32MP1_SHRES_I2C4, 209 STM32MP1_SHRES_RNG1, 210 STM32MP1_SHRES_HASH1, 211 STM32MP1_SHRES_CRYP1, 212 STM32MP1_SHRES_I2C6, 213 STM32MP1_SHRES_RTC, 214 STM32MP1_SHRES_MCU, 215 STM32MP1_SHRES_PLL3, 216 STM32MP1_SHRES_MDMA, 217 STM32MP1_SHRES_SRAM1, 218 STM32MP1_SHRES_SRAM2, 219 STM32MP1_SHRES_SRAM3, 220 STM32MP1_SHRES_SRAM4, 221 222 STM32MP1_SHRES_COUNT 223 }; 224 225 #ifdef CFG_STM32MP1_SHARED_RESOURCES 226 /* Register resource @id as a secure peripheral */ 227 void stm32mp_register_secure_periph(enum stm32mp_shres id); 228 229 /* Register resource @id as a non-secure peripheral */ 230 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 231 232 /* 233 * Register resource identified by @base as a secure peripheral 234 * @base: IOMEM physical base address of the resource 235 */ 236 void stm32mp_register_secure_periph_iomem(vaddr_t base); 237 238 /* 239 * Register resource identified by @base as a non-secure peripheral 240 * @base: IOMEM physical base address of the resource 241 */ 242 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 243 244 /* 245 * Register GPIO resource as a secure peripheral 246 * @bank: Bank of the target GPIO 247 * @pin: Bit position of the target GPIO in the bank 248 */ 249 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 250 251 /* 252 * Register GPIO resource as a non-secure peripheral 253 * @bank: Bank of the target GPIO 254 * @pin: Bit position of the target GPIO in the bank 255 */ 256 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 257 258 /* Return true if and only if resource @id is registered as secure */ 259 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 260 261 /* Return true if and only if GPIO bank @bank is registered as secure */ 262 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 263 264 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 265 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 266 267 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 268 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 269 270 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 271 272 static inline void stm32mp_register_secure_periph(enum stm32mp_shres id 273 __unused) 274 { 275 } 276 277 static inline void stm32mp_register_non_secure_periph(enum stm32mp_shres id 278 __unused) 279 { 280 } 281 282 static inline void stm32mp_register_secure_periph_iomem(vaddr_t base __unused) 283 { 284 } 285 286 static inline void stm32mp_register_non_secure_periph_iomem(vaddr_t base 287 __unused) 288 { 289 } 290 291 static inline void stm32mp_register_secure_gpio(unsigned int bank __unused, 292 unsigned int pin __unused) 293 { 294 } 295 296 static inline void stm32mp_register_non_secure_gpio(unsigned int bank __unused, 297 unsigned int pin __unused) 298 { 299 } 300 301 static inline bool stm32mp_periph_is_secure(enum stm32mp_shres id __unused) 302 { 303 return true; 304 } 305 306 static inline bool stm32mp_gpio_bank_is_secure(unsigned int bank __unused) 307 { 308 return true; 309 } 310 311 static inline bool stm32mp_gpio_bank_is_non_secure(unsigned int bank __unused) 312 { 313 return false; 314 } 315 316 static inline void stm32mp_register_clock_parents_secure(unsigned long clock_id 317 __unused) 318 { 319 } 320 321 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 322 #endif /*__STM32_UTIL_H__*/ 323