1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/stm32_bsec.h> 11 #include <kernel/panic.h> 12 #include <stdint.h> 13 #include <types_ext.h> 14 15 /* Backup registers and RAM utils */ 16 vaddr_t stm32mp_bkpreg(unsigned int idx); 17 18 /* Platform util for the GIC */ 19 vaddr_t get_gicc_base(void); 20 vaddr_t get_gicd_base(void); 21 22 /* 23 * Platform util functions for the GPIO driver 24 * @bank: Target GPIO bank ID as per DT bindings 25 * 26 * Platform shall implement these functions to provide to stm32_gpio 27 * driver the resource reference for a target GPIO bank. That are 28 * memory mapped interface base address, interface offset (see below) 29 * and clock identifier. 30 * 31 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 32 * check DT configuration matches platform implementation of the banks 33 * description. 34 */ 35 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 36 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 37 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 38 39 /* Platform util for PMIC support */ 40 bool stm32mp_with_pmic(void); 41 42 /* Power management service */ 43 #ifdef CFG_PSCI_ARM32 44 void stm32mp_register_online_cpu(void); 45 #else 46 static inline void stm32mp_register_online_cpu(void) 47 { 48 } 49 #endif 50 51 /* 52 * Generic spinlock function that bypass spinlock if MMU is disabled or 53 * lock is NULL. 54 */ 55 uint32_t may_spin_lock(unsigned int *lock); 56 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 57 58 /* 59 * Util for clock gating and to get clock rate for stm32 and platform drivers 60 * @id: Target clock ID, ID used in clock DT bindings 61 */ 62 void stm32_clock_enable(unsigned long id); 63 void stm32_clock_disable(unsigned long id); 64 unsigned long stm32_clock_get_rate(unsigned long id); 65 bool stm32_clock_is_enabled(unsigned long id); 66 67 /* Return true if @clock_id is shared by secure and non-secure worlds */ 68 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 69 70 /* 71 * Util for reset signal assertion/desassertion for stm32 and platform drivers 72 * @id: Target peripheral ID, ID used in reset DT bindings 73 * @to_us: Timeout out in microsecond, or 0 if not waiting signal state 74 */ 75 TEE_Result stm32_reset_assert(unsigned int id, unsigned int timeout_us); 76 TEE_Result stm32_reset_deassert(unsigned int id, unsigned int timeout_us); 77 78 static inline void stm32_reset_set(unsigned int id) 79 { 80 (void)stm32_reset_assert(id, 0); 81 } 82 83 static inline void stm32_reset_release(unsigned int id) 84 { 85 (void)stm32_reset_deassert(id, 0); 86 } 87 88 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 89 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 90 91 /* 92 * Structure and API function for BSEC driver to get some platform data. 93 * 94 * @base: BSEC interface registers physical base address 95 * @upper_start: Base ID for the BSEC upper words in the platform 96 * @max_id: Max value for BSEC word ID for the platform 97 */ 98 struct stm32_bsec_static_cfg { 99 paddr_t base; 100 unsigned int upper_start; 101 unsigned int max_id; 102 }; 103 104 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 105 106 /* 107 * Return true if platform is in closed_device mode 108 */ 109 bool stm32mp_is_closed_device(void); 110 111 /* 112 * Shared registers support: common lock for accessing SoC registers 113 * shared between several drivers. 114 */ 115 void io_mask32_stm32shregs(vaddr_t va, uint32_t value, uint32_t mask); 116 117 static inline void io_setbits32_stm32shregs(vaddr_t va, uint32_t value) 118 { 119 io_mask32_stm32shregs(va, value, value); 120 } 121 122 static inline void io_clrbits32_stm32shregs(vaddr_t va, uint32_t value) 123 { 124 io_mask32_stm32shregs(va, 0, value); 125 } 126 127 void io_clrsetbits32_stm32shregs(vaddr_t va, uint32_t clr, uint32_t set); 128 129 /* 130 * Shared reference counter: increments by 2 on secure increment 131 * request, decrements by 2 on secure decrement request. Bit #0 132 * is set to 1 on non-secure increment request and reset to 0 on 133 * non-secure decrement request. These counters initialize to 134 * either 0, 1 or 2 upon their expect default state. 135 * Counters saturate to UINT_MAX / 2. 136 */ 137 #define SHREFCNT_NONSECURE_FLAG 0x1ul 138 #define SHREFCNT_SECURE_STEP 0x2ul 139 #define SHREFCNT_MAX (UINT_MAX / 2) 140 141 /* Return 1 if refcnt increments from 0, else return 0 */ 142 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 143 { 144 int rc = !*refcnt; 145 146 if (secure) { 147 if (*refcnt < SHREFCNT_MAX) { 148 *refcnt += SHREFCNT_SECURE_STEP; 149 assert(*refcnt < SHREFCNT_MAX); 150 } 151 } else { 152 *refcnt |= SHREFCNT_NONSECURE_FLAG; 153 } 154 155 return rc; 156 } 157 158 /* Return 1 if refcnt decrements to 0, else return 0 */ 159 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 160 { 161 int rc = 0; 162 163 if (secure) { 164 if (*refcnt < SHREFCNT_MAX) { 165 if (*refcnt < SHREFCNT_SECURE_STEP) 166 panic(); 167 168 *refcnt -= SHREFCNT_SECURE_STEP; 169 rc = !*refcnt; 170 } 171 } else { 172 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 173 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 174 } 175 176 return rc; 177 } 178 179 static inline int incr_refcnt(unsigned int *refcnt) 180 { 181 return incr_shrefcnt(refcnt, true); 182 } 183 184 static inline int decr_refcnt(unsigned int *refcnt) 185 { 186 return decr_shrefcnt(refcnt, true); 187 } 188 189 /* 190 * Shared peripherals and resources registration 191 * 192 * Resources listed in enum stm32mp_shres assigned at run-time to the 193 * non-secure world, to the secure world or shared by both worlds. 194 * In the later case, there must exist a secure service in OP-TEE 195 * for the non-secure world to access the resource. 196 * 197 * Resources may be a peripheral, a bus, a clock or a memory. 198 * 199 * Shared resources driver API functions allows drivers to register the 200 * resource as secure, non-secure or shared and to get the resource 201 * assignation state. 202 */ 203 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 204 205 enum stm32mp_shres { 206 STM32MP1_SHRES_GPIOZ_0 = 0, 207 STM32MP1_SHRES_GPIOZ_1, 208 STM32MP1_SHRES_GPIOZ_2, 209 STM32MP1_SHRES_GPIOZ_3, 210 STM32MP1_SHRES_GPIOZ_4, 211 STM32MP1_SHRES_GPIOZ_5, 212 STM32MP1_SHRES_GPIOZ_6, 213 STM32MP1_SHRES_GPIOZ_7, 214 STM32MP1_SHRES_IWDG1, 215 STM32MP1_SHRES_USART1, 216 STM32MP1_SHRES_SPI6, 217 STM32MP1_SHRES_I2C4, 218 STM32MP1_SHRES_RNG1, 219 STM32MP1_SHRES_HASH1, 220 STM32MP1_SHRES_CRYP1, 221 STM32MP1_SHRES_I2C6, 222 STM32MP1_SHRES_RTC, 223 STM32MP1_SHRES_MCU, 224 STM32MP1_SHRES_PLL3, 225 STM32MP1_SHRES_MDMA, 226 227 STM32MP1_SHRES_COUNT 228 }; 229 230 /* Register resource @id as a secure peripheral */ 231 void stm32mp_register_secure_periph(enum stm32mp_shres id); 232 233 /* Register resource @id as a non-secure peripheral */ 234 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 235 236 /* 237 * Register resource identified by @base as a secure peripheral 238 * @base: IOMEM physical base address of the resource 239 */ 240 void stm32mp_register_secure_periph_iomem(vaddr_t base); 241 242 /* 243 * Register resource identified by @base as a non-secure peripheral 244 * @base: IOMEM physical base address of the resource 245 */ 246 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 247 248 /* 249 * Register GPIO resource as a secure peripheral 250 * @bank: Bank of the target GPIO 251 * @pin: Bit position of the target GPIO in the bank 252 */ 253 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 254 255 /* 256 * Register GPIO resource as a non-secure peripheral 257 * @bank: Bank of the target GPIO 258 * @pin: Bit position of the target GPIO in the bank 259 */ 260 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 261 262 /* Return true if and only if resource @id is registered as secure */ 263 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 264 265 /* Return true if and only if GPIO bank @bank is registered as secure */ 266 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 267 268 /* Return true if and only if GPIO bank @bank is registered as shared */ 269 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 270 271 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 272 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 273 274 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 275 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 276 277 #endif /*__STM32_UTIL_H__*/ 278