1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/stm32_bsec.h> 11 #include <kernel/panic.h> 12 #include <stdint.h> 13 #include <types_ext.h> 14 15 /* Backup registers and RAM utils */ 16 vaddr_t stm32mp_bkpreg(unsigned int idx); 17 18 /* 19 * SYSCFG IO compensation. 20 * These functions assume non-secure world is suspended. 21 */ 22 void stm32mp_syscfg_enable_io_compensation(void); 23 void stm32mp_syscfg_disable_io_compensation(void); 24 25 /* Platform util for the GIC */ 26 vaddr_t get_gicc_base(void); 27 vaddr_t get_gicd_base(void); 28 29 /* 30 * Platform util functions for the GPIO driver 31 * @bank: Target GPIO bank ID as per DT bindings 32 * 33 * Platform shall implement these functions to provide to stm32_gpio 34 * driver the resource reference for a target GPIO bank. That are 35 * memory mapped interface base address, interface offset (see below) 36 * and clock identifier. 37 * 38 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 39 * check DT configuration matches platform implementation of the banks 40 * description. 41 */ 42 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 43 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 44 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 45 46 /* Platform util for PMIC support */ 47 bool stm32mp_with_pmic(void); 48 49 /* Power management service */ 50 #ifdef CFG_PSCI_ARM32 51 void stm32mp_register_online_cpu(void); 52 #else 53 static inline void stm32mp_register_online_cpu(void) 54 { 55 } 56 #endif 57 58 /* 59 * Generic spinlock function that bypass spinlock if MMU is disabled or 60 * lock is NULL. 61 */ 62 uint32_t may_spin_lock(unsigned int *lock); 63 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 64 65 /* 66 * Util for clock gating and to get clock rate for stm32 and platform drivers 67 * @id: Target clock ID, ID used in clock DT bindings 68 */ 69 void stm32_clock_enable(unsigned long id); 70 void stm32_clock_disable(unsigned long id); 71 unsigned long stm32_clock_get_rate(unsigned long id); 72 bool stm32_clock_is_enabled(unsigned long id); 73 74 /* Return true if @clock_id is shared by secure and non-secure worlds */ 75 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 76 77 /* 78 * Util for reset signal assertion/desassertion for stm32 and platform drivers 79 * @id: Target peripheral ID, ID used in reset DT bindings 80 * @to_us: Timeout out in microsecond, or 0 if not waiting signal state 81 */ 82 TEE_Result stm32_reset_assert(unsigned int id, unsigned int timeout_us); 83 TEE_Result stm32_reset_deassert(unsigned int id, unsigned int timeout_us); 84 85 static inline void stm32_reset_set(unsigned int id) 86 { 87 (void)stm32_reset_assert(id, 0); 88 } 89 90 static inline void stm32_reset_release(unsigned int id) 91 { 92 (void)stm32_reset_deassert(id, 0); 93 } 94 95 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 96 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 97 98 /* 99 * Structure and API function for BSEC driver to get some platform data. 100 * 101 * @base: BSEC interface registers physical base address 102 * @upper_start: Base ID for the BSEC upper words in the platform 103 * @max_id: Max value for BSEC word ID for the platform 104 */ 105 struct stm32_bsec_static_cfg { 106 paddr_t base; 107 unsigned int upper_start; 108 unsigned int max_id; 109 }; 110 111 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 112 113 /* 114 * Return true if platform is in closed_device mode 115 */ 116 bool stm32mp_is_closed_device(void); 117 118 /* 119 * Shared registers support: common lock for accessing SoC registers 120 * shared between several drivers. 121 */ 122 void io_mask32_stm32shregs(vaddr_t va, uint32_t value, uint32_t mask); 123 124 static inline void io_setbits32_stm32shregs(vaddr_t va, uint32_t value) 125 { 126 io_mask32_stm32shregs(va, value, value); 127 } 128 129 static inline void io_clrbits32_stm32shregs(vaddr_t va, uint32_t value) 130 { 131 io_mask32_stm32shregs(va, 0, value); 132 } 133 134 void io_clrsetbits32_stm32shregs(vaddr_t va, uint32_t clr, uint32_t set); 135 136 /* 137 * Shared reference counter: increments by 2 on secure increment 138 * request, decrements by 2 on secure decrement request. Bit #0 139 * is set to 1 on non-secure increment request and reset to 0 on 140 * non-secure decrement request. These counters initialize to 141 * either 0, 1 or 2 upon their expect default state. 142 * Counters saturate to UINT_MAX / 2. 143 */ 144 #define SHREFCNT_NONSECURE_FLAG 0x1ul 145 #define SHREFCNT_SECURE_STEP 0x2ul 146 #define SHREFCNT_MAX (UINT_MAX / 2) 147 148 /* Return 1 if refcnt increments from 0, else return 0 */ 149 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 150 { 151 int rc = !*refcnt; 152 153 if (secure) { 154 if (*refcnt < SHREFCNT_MAX) { 155 *refcnt += SHREFCNT_SECURE_STEP; 156 assert(*refcnt < SHREFCNT_MAX); 157 } 158 } else { 159 *refcnt |= SHREFCNT_NONSECURE_FLAG; 160 } 161 162 return rc; 163 } 164 165 /* Return 1 if refcnt decrements to 0, else return 0 */ 166 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 167 { 168 int rc = 0; 169 170 if (secure) { 171 if (*refcnt < SHREFCNT_MAX) { 172 if (*refcnt < SHREFCNT_SECURE_STEP) 173 panic(); 174 175 *refcnt -= SHREFCNT_SECURE_STEP; 176 rc = !*refcnt; 177 } 178 } else { 179 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 180 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 181 } 182 183 return rc; 184 } 185 186 static inline int incr_refcnt(unsigned int *refcnt) 187 { 188 return incr_shrefcnt(refcnt, true); 189 } 190 191 static inline int decr_refcnt(unsigned int *refcnt) 192 { 193 return decr_shrefcnt(refcnt, true); 194 } 195 196 /* 197 * Shared peripherals and resources registration 198 * 199 * Resources listed in enum stm32mp_shres assigned at run-time to the 200 * non-secure world, to the secure world or shared by both worlds. 201 * In the later case, there must exist a secure service in OP-TEE 202 * for the non-secure world to access the resource. 203 * 204 * Resources may be a peripheral, a bus, a clock or a memory. 205 * 206 * Shared resources driver API functions allows drivers to register the 207 * resource as secure, non-secure or shared and to get the resource 208 * assignation state. 209 */ 210 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 211 212 enum stm32mp_shres { 213 STM32MP1_SHRES_GPIOZ_0 = 0, 214 STM32MP1_SHRES_GPIOZ_1, 215 STM32MP1_SHRES_GPIOZ_2, 216 STM32MP1_SHRES_GPIOZ_3, 217 STM32MP1_SHRES_GPIOZ_4, 218 STM32MP1_SHRES_GPIOZ_5, 219 STM32MP1_SHRES_GPIOZ_6, 220 STM32MP1_SHRES_GPIOZ_7, 221 STM32MP1_SHRES_IWDG1, 222 STM32MP1_SHRES_USART1, 223 STM32MP1_SHRES_SPI6, 224 STM32MP1_SHRES_I2C4, 225 STM32MP1_SHRES_RNG1, 226 STM32MP1_SHRES_HASH1, 227 STM32MP1_SHRES_CRYP1, 228 STM32MP1_SHRES_I2C6, 229 STM32MP1_SHRES_RTC, 230 STM32MP1_SHRES_MCU, 231 STM32MP1_SHRES_PLL3, 232 STM32MP1_SHRES_MDMA, 233 234 STM32MP1_SHRES_COUNT 235 }; 236 237 /* Register resource @id as a secure peripheral */ 238 void stm32mp_register_secure_periph(enum stm32mp_shres id); 239 240 /* Register resource @id as a non-secure peripheral */ 241 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 242 243 /* 244 * Register resource identified by @base as a secure peripheral 245 * @base: IOMEM physical base address of the resource 246 */ 247 void stm32mp_register_secure_periph_iomem(vaddr_t base); 248 249 /* 250 * Register resource identified by @base as a non-secure peripheral 251 * @base: IOMEM physical base address of the resource 252 */ 253 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 254 255 /* 256 * Register GPIO resource as a secure peripheral 257 * @bank: Bank of the target GPIO 258 * @pin: Bit position of the target GPIO in the bank 259 */ 260 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 261 262 /* 263 * Register GPIO resource as a non-secure peripheral 264 * @bank: Bank of the target GPIO 265 * @pin: Bit position of the target GPIO in the bank 266 */ 267 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 268 269 /* Return true if and only if resource @id is registered as secure */ 270 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 271 272 /* Return true if and only if GPIO bank @bank is registered as secure */ 273 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 274 275 /* Return true if and only if GPIO bank @bank is registered as shared */ 276 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 277 278 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 279 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 280 281 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 282 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 283 284 #endif /*__STM32_UTIL_H__*/ 285