1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/stm32_bsec.h> 12 #include <kernel/panic.h> 13 #include <stdint.h> 14 #include <types_ext.h> 15 16 /* Backup registers and RAM utils */ 17 vaddr_t stm32mp_bkpreg(unsigned int idx); 18 19 /* 20 * SYSCFG IO compensation. 21 * These functions assume non-secure world is suspended. 22 */ 23 void stm32mp_syscfg_enable_io_compensation(void); 24 void stm32mp_syscfg_disable_io_compensation(void); 25 26 /* Platform util for the GIC */ 27 vaddr_t get_gicd_base(void); 28 29 /* 30 * Platform util functions for the GPIO driver 31 * @bank: Target GPIO bank ID as per DT bindings 32 * 33 * Platform shall implement these functions to provide to stm32_gpio 34 * driver the resource reference for a target GPIO bank. That are 35 * memory mapped interface base address, interface offset (see below) 36 * and clock identifier. 37 * 38 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 39 * check DT configuration matches platform implementation of the banks 40 * description. 41 */ 42 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 43 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 44 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 45 struct clk *stm32_get_gpio_bank_clk(unsigned int bank); 46 47 /* Platform util for PMIC support */ 48 bool stm32mp_with_pmic(void); 49 50 /* Power management service */ 51 #ifdef CFG_PSCI_ARM32 52 void stm32mp_register_online_cpu(void); 53 #else 54 static inline void stm32mp_register_online_cpu(void) 55 { 56 } 57 #endif 58 59 /* 60 * Generic spinlock function that bypass spinlock if MMU is disabled or 61 * lock is NULL. 62 */ 63 uint32_t may_spin_lock(unsigned int *lock); 64 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 65 66 /* 67 * Util for clock gating and to get clock rate for stm32 and platform drivers 68 * @id: Target clock ID, ID used in clock DT bindings 69 */ 70 void stm32_clock_enable(unsigned long id); 71 void stm32_clock_disable(unsigned long id); 72 unsigned long stm32_clock_get_rate(unsigned long id); 73 bool stm32_clock_is_enabled(unsigned long id); 74 75 /* Helper from platform RCC clock driver */ 76 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id); 77 78 /* Return true if @clock_id is shared by secure and non-secure worlds */ 79 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 80 81 extern const struct clk_ops stm32mp1_clk_ops; 82 83 #if defined(CFG_STPMIC1) 84 /* Return true if non-secure world can manipulate regulator @pmic_regu_name */ 85 bool stm32mp_nsec_can_access_pmic_regu(const char *pmic_regu_name); 86 #else 87 static inline bool stm32mp_nsec_can_access_pmic_regu(const char *name __unused) 88 { 89 return false; 90 } 91 #endif 92 93 /* 94 * Util for reset signal assertion/desassertion for stm32 and platform drivers 95 * @id: Target peripheral ID, ID used in reset DT bindings 96 * @to_us: Timeout out in microsecond, or 0 if not waiting signal state 97 */ 98 TEE_Result stm32_reset_assert(unsigned int id, unsigned int timeout_us); 99 TEE_Result stm32_reset_deassert(unsigned int id, unsigned int timeout_us); 100 101 /* Specific reset to manage the MCU hold boot */ 102 void stm32_reset_assert_deassert_mcu(bool assert_not_deassert); 103 104 static inline void stm32_reset_set(unsigned int id) 105 { 106 (void)stm32_reset_assert(id, 0); 107 } 108 109 static inline void stm32_reset_release(unsigned int id) 110 { 111 (void)stm32_reset_deassert(id, 0); 112 } 113 114 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 115 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 116 117 /* 118 * Structure and API function for BSEC driver to get some platform data. 119 * 120 * @base: BSEC interface registers physical base address 121 * @upper_start: Base ID for the BSEC upper words in the platform 122 * @max_id: Max value for BSEC word ID for the platform 123 */ 124 struct stm32_bsec_static_cfg { 125 paddr_t base; 126 unsigned int upper_start; 127 unsigned int max_id; 128 }; 129 130 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 131 132 /* 133 * Return true if platform is in closed_device mode 134 */ 135 bool stm32mp_is_closed_device(void); 136 137 /* 138 * Shared registers support: common lock for accessing SoC registers 139 * shared between several drivers. 140 */ 141 void io_mask32_stm32shregs(vaddr_t va, uint32_t value, uint32_t mask); 142 143 static inline void io_setbits32_stm32shregs(vaddr_t va, uint32_t value) 144 { 145 io_mask32_stm32shregs(va, value, value); 146 } 147 148 static inline void io_clrbits32_stm32shregs(vaddr_t va, uint32_t value) 149 { 150 io_mask32_stm32shregs(va, 0, value); 151 } 152 153 void io_clrsetbits32_stm32shregs(vaddr_t va, uint32_t clr, uint32_t set); 154 155 /* 156 * Shared reference counter: increments by 2 on secure increment 157 * request, decrements by 2 on secure decrement request. Bit #0 158 * is set to 1 on non-secure increment request and reset to 0 on 159 * non-secure decrement request. These counters initialize to 160 * either 0, 1 or 2 upon their expect default state. 161 * Counters saturate to UINT_MAX / 2. 162 */ 163 #define SHREFCNT_NONSECURE_FLAG 0x1ul 164 #define SHREFCNT_SECURE_STEP 0x2ul 165 #define SHREFCNT_MAX (UINT_MAX / 2) 166 167 /* Return 1 if refcnt increments from 0, else return 0 */ 168 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 169 { 170 int rc = !*refcnt; 171 172 if (secure) { 173 if (*refcnt < SHREFCNT_MAX) { 174 *refcnt += SHREFCNT_SECURE_STEP; 175 assert(*refcnt < SHREFCNT_MAX); 176 } 177 } else { 178 *refcnt |= SHREFCNT_NONSECURE_FLAG; 179 } 180 181 return rc; 182 } 183 184 /* Return 1 if refcnt decrements to 0, else return 0 */ 185 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 186 { 187 int rc = 0; 188 189 if (secure) { 190 if (*refcnt < SHREFCNT_MAX) { 191 if (*refcnt < SHREFCNT_SECURE_STEP) 192 panic(); 193 194 *refcnt -= SHREFCNT_SECURE_STEP; 195 rc = !*refcnt; 196 } 197 } else { 198 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 199 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 200 } 201 202 return rc; 203 } 204 205 static inline int incr_refcnt(unsigned int *refcnt) 206 { 207 return incr_shrefcnt(refcnt, true); 208 } 209 210 static inline int decr_refcnt(unsigned int *refcnt) 211 { 212 return decr_shrefcnt(refcnt, true); 213 } 214 215 /* 216 * Shared peripherals and resources registration 217 * 218 * Resources listed in enum stm32mp_shres assigned at run-time to the 219 * non-secure world, to the secure world or shared by both worlds. 220 * In the later case, there must exist a secure service in OP-TEE 221 * for the non-secure world to access the resource. 222 * 223 * Resources may be a peripheral, a bus, a clock or a memory. 224 * 225 * Shared resources driver API functions allows drivers to register the 226 * resource as secure, non-secure or shared and to get the resource 227 * assignation state. 228 */ 229 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 230 231 enum stm32mp_shres { 232 STM32MP1_SHRES_GPIOZ_0 = 0, 233 STM32MP1_SHRES_GPIOZ_1, 234 STM32MP1_SHRES_GPIOZ_2, 235 STM32MP1_SHRES_GPIOZ_3, 236 STM32MP1_SHRES_GPIOZ_4, 237 STM32MP1_SHRES_GPIOZ_5, 238 STM32MP1_SHRES_GPIOZ_6, 239 STM32MP1_SHRES_GPIOZ_7, 240 STM32MP1_SHRES_IWDG1, 241 STM32MP1_SHRES_USART1, 242 STM32MP1_SHRES_SPI6, 243 STM32MP1_SHRES_I2C4, 244 STM32MP1_SHRES_RNG1, 245 STM32MP1_SHRES_HASH1, 246 STM32MP1_SHRES_CRYP1, 247 STM32MP1_SHRES_I2C6, 248 STM32MP1_SHRES_RTC, 249 STM32MP1_SHRES_MCU, 250 STM32MP1_SHRES_PLL3, 251 STM32MP1_SHRES_MDMA, 252 253 STM32MP1_SHRES_COUNT 254 }; 255 256 /* Register resource @id as a secure peripheral */ 257 void stm32mp_register_secure_periph(enum stm32mp_shres id); 258 259 /* Register resource @id as a non-secure peripheral */ 260 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 261 262 /* 263 * Register resource identified by @base as a secure peripheral 264 * @base: IOMEM physical base address of the resource 265 */ 266 void stm32mp_register_secure_periph_iomem(vaddr_t base); 267 268 /* 269 * Register resource identified by @base as a non-secure peripheral 270 * @base: IOMEM physical base address of the resource 271 */ 272 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 273 274 /* 275 * Register GPIO resource as a secure peripheral 276 * @bank: Bank of the target GPIO 277 * @pin: Bit position of the target GPIO in the bank 278 */ 279 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 280 281 /* 282 * Register GPIO resource as a non-secure peripheral 283 * @bank: Bank of the target GPIO 284 * @pin: Bit position of the target GPIO in the bank 285 */ 286 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 287 288 /* Return true if and only if resource @id is registered as secure */ 289 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 290 291 /* Return true if and only if GPIO bank @bank is registered as secure */ 292 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 293 294 /* Return true if and only if GPIO bank @bank is registered as shared */ 295 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 296 297 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 298 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 299 300 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 301 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 302 303 #endif /*__STM32_UTIL_H__*/ 304