1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2022, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/pinctrl.h> 12 #include <drivers/stm32_bsec.h> 13 #include <kernel/panic.h> 14 #include <stdint.h> 15 #include <tee_api_types.h> 16 #include <types_ext.h> 17 18 /* Backup registers and RAM utils */ 19 vaddr_t stm32mp_bkpreg(unsigned int idx); 20 21 /* 22 * SYSCFG IO compensation. 23 * These functions assume non-secure world is suspended. 24 */ 25 void stm32mp_syscfg_enable_io_compensation(void); 26 void stm32mp_syscfg_disable_io_compensation(void); 27 28 /* Platform util for the RCC drivers */ 29 vaddr_t stm32_rcc_base(void); 30 31 /* Platform util for the GIC */ 32 vaddr_t get_gicd_base(void); 33 34 /* Platform util for PMIC support */ 35 bool stm32mp_with_pmic(void); 36 37 /* Power management service */ 38 #ifdef CFG_PSCI_ARM32 39 void stm32mp_register_online_cpu(void); 40 #else 41 static inline void stm32mp_register_online_cpu(void) 42 { 43 } 44 #endif 45 46 /* 47 * Generic spinlock function that bypass spinlock if MMU is disabled or 48 * lock is NULL. 49 */ 50 uint32_t may_spin_lock(unsigned int *lock); 51 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 52 53 /* Helper from platform RCC clock driver */ 54 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id); 55 56 #ifdef CFG_STM32MP1_SHARED_RESOURCES 57 /* Return true if @clock_id is shared by secure and non-secure worlds */ 58 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 59 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 60 static inline bool stm32mp_nsec_can_access_clock(unsigned long clock_id 61 __unused) 62 { 63 return true; 64 } 65 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 66 67 extern const struct clk_ops stm32mp1_clk_ops; 68 69 #if defined(CFG_STPMIC1) 70 /* Return true if non-secure world can manipulate regulator @pmic_regu_name */ 71 bool stm32mp_nsec_can_access_pmic_regu(const char *pmic_regu_name); 72 #else 73 static inline bool stm32mp_nsec_can_access_pmic_regu(const char *name __unused) 74 { 75 return false; 76 } 77 #endif 78 79 #ifdef CFG_STM32MP1_SHARED_RESOURCES 80 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 81 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 82 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 83 static inline bool stm32mp_nsec_can_access_reset(unsigned int reset_id __unused) 84 { 85 return true; 86 } 87 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 88 89 /* Return rstctrl instance related to RCC reset controller DT binding ID */ 90 struct rstctrl *stm32mp_rcc_reset_id_to_rstctrl(unsigned int binding_id); 91 92 /* 93 * Structure and API function for BSEC driver to get some platform data. 94 * 95 * @base: BSEC interface registers physical base address 96 * @upper_start: Base ID for the BSEC upper words in the platform 97 * @max_id: Max value for BSEC word ID for the platform 98 */ 99 struct stm32_bsec_static_cfg { 100 paddr_t base; 101 unsigned int upper_start; 102 unsigned int max_id; 103 }; 104 105 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 106 107 /* 108 * Shared reference counter: increments by 2 on secure increment 109 * request, decrements by 2 on secure decrement request. Bit #0 110 * is set to 1 on non-secure increment request and reset to 0 on 111 * non-secure decrement request. These counters initialize to 112 * either 0, 1 or 2 upon their expect default state. 113 * Counters saturate to UINT_MAX / 2. 114 */ 115 #define SHREFCNT_NONSECURE_FLAG 0x1ul 116 #define SHREFCNT_SECURE_STEP 0x2ul 117 #define SHREFCNT_MAX (UINT_MAX / 2) 118 119 /* Return 1 if refcnt increments from 0, else return 0 */ 120 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 121 { 122 int rc = !*refcnt; 123 124 if (secure) { 125 if (*refcnt < SHREFCNT_MAX) { 126 *refcnt += SHREFCNT_SECURE_STEP; 127 assert(*refcnt < SHREFCNT_MAX); 128 } 129 } else { 130 *refcnt |= SHREFCNT_NONSECURE_FLAG; 131 } 132 133 return rc; 134 } 135 136 /* Return 1 if refcnt decrements to 0, else return 0 */ 137 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 138 { 139 int rc = 0; 140 141 if (secure) { 142 if (*refcnt < SHREFCNT_MAX) { 143 if (*refcnt < SHREFCNT_SECURE_STEP) 144 panic(); 145 146 *refcnt -= SHREFCNT_SECURE_STEP; 147 rc = !*refcnt; 148 } 149 } else { 150 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 151 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 152 } 153 154 return rc; 155 } 156 157 static inline int incr_refcnt(unsigned int *refcnt) 158 { 159 return incr_shrefcnt(refcnt, true); 160 } 161 162 static inline int decr_refcnt(unsigned int *refcnt) 163 { 164 return decr_shrefcnt(refcnt, true); 165 } 166 167 /* 168 * Shared peripherals and resources registration 169 * 170 * Resources listed in enum stm32mp_shres assigned at run-time to the 171 * non-secure world, to the secure world or shared by both worlds. 172 * In the later case, there must exist a secure service in OP-TEE 173 * for the non-secure world to access the resource. 174 * 175 * Resources may be a peripheral, a bus, a clock or a memory. 176 * 177 * Shared resources driver API functions allows drivers to register the 178 * resource as secure, non-secure or shared and to get the resource 179 * assignation state. 180 */ 181 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 182 183 enum stm32mp_shres { 184 STM32MP1_SHRES_GPIOZ_0 = 0, 185 STM32MP1_SHRES_GPIOZ_1, 186 STM32MP1_SHRES_GPIOZ_2, 187 STM32MP1_SHRES_GPIOZ_3, 188 STM32MP1_SHRES_GPIOZ_4, 189 STM32MP1_SHRES_GPIOZ_5, 190 STM32MP1_SHRES_GPIOZ_6, 191 STM32MP1_SHRES_GPIOZ_7, 192 STM32MP1_SHRES_IWDG1, 193 STM32MP1_SHRES_USART1, 194 STM32MP1_SHRES_SPI6, 195 STM32MP1_SHRES_I2C4, 196 STM32MP1_SHRES_RNG1, 197 STM32MP1_SHRES_HASH1, 198 STM32MP1_SHRES_CRYP1, 199 STM32MP1_SHRES_I2C6, 200 STM32MP1_SHRES_RTC, 201 STM32MP1_SHRES_MCU, 202 STM32MP1_SHRES_PLL3, 203 STM32MP1_SHRES_MDMA, 204 STM32MP1_SHRES_SRAM1, 205 STM32MP1_SHRES_SRAM2, 206 STM32MP1_SHRES_SRAM3, 207 STM32MP1_SHRES_SRAM4, 208 209 STM32MP1_SHRES_COUNT 210 }; 211 212 #ifdef CFG_STM32MP1_SHARED_RESOURCES 213 /* Register resource @id as a secure peripheral */ 214 void stm32mp_register_secure_periph(enum stm32mp_shres id); 215 216 /* Register resource @id as a non-secure peripheral */ 217 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 218 219 /* 220 * Register resource identified by @base as a secure peripheral 221 * @base: IOMEM physical base address of the resource 222 */ 223 void stm32mp_register_secure_periph_iomem(vaddr_t base); 224 225 /* 226 * Register resource identified by @base as a non-secure peripheral 227 * @base: IOMEM physical base address of the resource 228 */ 229 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 230 231 /* 232 * Register GPIO resource as a secure peripheral 233 * @bank: Bank of the target GPIO 234 * @pin: Bit position of the target GPIO in the bank 235 */ 236 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 237 238 /* 239 * Register GPIO resource as a non-secure peripheral 240 * @bank: Bank of the target GPIO 241 * @pin: Bit position of the target GPIO in the bank 242 */ 243 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 244 245 /* 246 * Register pin resource of a pin control state as a secure peripheral 247 * @bank: Bank of the target GPIO 248 * @pin: Bit position of the target GPIO in the bank 249 */ 250 void stm32mp_register_secure_pinctrl(struct pinctrl_state *pinctrl); 251 252 /* 253 * Register pin resource of a pin control state as a non-secure peripheral 254 * @bank: Bank of the target GPIO 255 * @pin: Bit position of the target GPIO in the bank 256 */ 257 void stm32mp_register_non_secure_pinctrl(struct pinctrl_state *pinctrl); 258 259 /* Return true if and only if resource @id is registered as secure */ 260 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 261 262 /* Return true if and only if GPIO bank @bank is registered as secure */ 263 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 264 265 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 266 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 267 268 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 269 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 270 271 /* Register number of pins in the GPIOZ bank */ 272 void stm32mp_register_gpioz_pin_count(size_t count); 273 274 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 275 276 static inline void stm32mp_register_secure_periph(enum stm32mp_shres id 277 __unused) 278 { 279 } 280 281 static inline void stm32mp_register_non_secure_periph(enum stm32mp_shres id 282 __unused) 283 { 284 } 285 286 static inline void stm32mp_register_secure_periph_iomem(vaddr_t base __unused) 287 { 288 } 289 290 static inline void stm32mp_register_non_secure_periph_iomem(vaddr_t base 291 __unused) 292 { 293 } 294 295 static inline void stm32mp_register_secure_gpio(unsigned int bank __unused, 296 unsigned int pin __unused) 297 { 298 } 299 300 static inline void stm32mp_register_non_secure_gpio(unsigned int bank __unused, 301 unsigned int pin __unused) 302 { 303 } 304 305 static inline void 306 stm32mp_register_secure_pinctrl(struct pinctrl_state *pinctrl __unused) 307 { 308 } 309 310 static inline void 311 stm32mp_register_non_secure_pinctrl(struct pinctrl_state *pinctrl __unused) 312 { 313 } 314 315 static inline bool stm32mp_periph_is_secure(enum stm32mp_shres id __unused) 316 { 317 return true; 318 } 319 320 static inline bool stm32mp_gpio_bank_is_secure(unsigned int bank __unused) 321 { 322 return true; 323 } 324 325 static inline bool stm32mp_gpio_bank_is_non_secure(unsigned int bank __unused) 326 { 327 return false; 328 } 329 330 static inline void stm32mp_register_clock_parents_secure(unsigned long clock_id 331 __unused) 332 { 333 } 334 335 static inline void stm32mp_register_gpioz_pin_count(size_t count __unused) 336 { 337 } 338 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 339 #endif /*__STM32_UTIL_H__*/ 340