1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2022, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/stm32_bsec.h> 12 #include <kernel/panic.h> 13 #include <stdint.h> 14 #include <types_ext.h> 15 16 /* Backup registers and RAM utils */ 17 vaddr_t stm32mp_bkpreg(unsigned int idx); 18 19 /* 20 * SYSCFG IO compensation. 21 * These functions assume non-secure world is suspended. 22 */ 23 void stm32mp_syscfg_enable_io_compensation(void); 24 void stm32mp_syscfg_disable_io_compensation(void); 25 26 /* Platform util for the RCC drivers */ 27 vaddr_t stm32_rcc_base(void); 28 29 /* Platform util for the GIC */ 30 vaddr_t get_gicd_base(void); 31 32 /* 33 * Platform util functions for the GPIO driver 34 * @bank: Target GPIO bank ID as per DT bindings 35 * 36 * Platform shall implement these functions to provide to stm32_gpio 37 * driver the resource reference for a target GPIO bank. That are 38 * memory mapped interface base address, interface offset (see below) 39 * and clock identifier. 40 * 41 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 42 * check DT configuration matches platform implementation of the banks 43 * description. 44 */ 45 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 46 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 47 48 /* Platform util for PMIC support */ 49 bool stm32mp_with_pmic(void); 50 51 /* Power management service */ 52 #ifdef CFG_PSCI_ARM32 53 void stm32mp_register_online_cpu(void); 54 #else 55 static inline void stm32mp_register_online_cpu(void) 56 { 57 } 58 #endif 59 60 /* 61 * Generic spinlock function that bypass spinlock if MMU is disabled or 62 * lock is NULL. 63 */ 64 uint32_t may_spin_lock(unsigned int *lock); 65 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 66 67 /* Helper from platform RCC clock driver */ 68 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id); 69 70 #ifdef CFG_STM32MP1_SHARED_RESOURCES 71 /* Return true if @clock_id is shared by secure and non-secure worlds */ 72 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 73 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 74 static inline bool stm32mp_nsec_can_access_clock(unsigned long clock_id 75 __unused) 76 { 77 return true; 78 } 79 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 80 81 extern const struct clk_ops stm32mp1_clk_ops; 82 83 #if defined(CFG_STPMIC1) 84 /* Return true if non-secure world can manipulate regulator @pmic_regu_name */ 85 bool stm32mp_nsec_can_access_pmic_regu(const char *pmic_regu_name); 86 #else 87 static inline bool stm32mp_nsec_can_access_pmic_regu(const char *name __unused) 88 { 89 return false; 90 } 91 #endif 92 93 #ifdef CFG_STM32MP1_SHARED_RESOURCES 94 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 95 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 96 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 97 static inline bool stm32mp_nsec_can_access_reset(unsigned int reset_id __unused) 98 { 99 return true; 100 } 101 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 102 103 /* Return rstctrl instance related to RCC reset controller DT binding ID */ 104 struct rstctrl *stm32mp_rcc_reset_id_to_rstctrl(unsigned int binding_id); 105 106 /* 107 * Structure and API function for BSEC driver to get some platform data. 108 * 109 * @base: BSEC interface registers physical base address 110 * @upper_start: Base ID for the BSEC upper words in the platform 111 * @max_id: Max value for BSEC word ID for the platform 112 */ 113 struct stm32_bsec_static_cfg { 114 paddr_t base; 115 unsigned int upper_start; 116 unsigned int max_id; 117 }; 118 119 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 120 121 /* 122 * Shared reference counter: increments by 2 on secure increment 123 * request, decrements by 2 on secure decrement request. Bit #0 124 * is set to 1 on non-secure increment request and reset to 0 on 125 * non-secure decrement request. These counters initialize to 126 * either 0, 1 or 2 upon their expect default state. 127 * Counters saturate to UINT_MAX / 2. 128 */ 129 #define SHREFCNT_NONSECURE_FLAG 0x1ul 130 #define SHREFCNT_SECURE_STEP 0x2ul 131 #define SHREFCNT_MAX (UINT_MAX / 2) 132 133 /* Return 1 if refcnt increments from 0, else return 0 */ 134 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 135 { 136 int rc = !*refcnt; 137 138 if (secure) { 139 if (*refcnt < SHREFCNT_MAX) { 140 *refcnt += SHREFCNT_SECURE_STEP; 141 assert(*refcnt < SHREFCNT_MAX); 142 } 143 } else { 144 *refcnt |= SHREFCNT_NONSECURE_FLAG; 145 } 146 147 return rc; 148 } 149 150 /* Return 1 if refcnt decrements to 0, else return 0 */ 151 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 152 { 153 int rc = 0; 154 155 if (secure) { 156 if (*refcnt < SHREFCNT_MAX) { 157 if (*refcnt < SHREFCNT_SECURE_STEP) 158 panic(); 159 160 *refcnt -= SHREFCNT_SECURE_STEP; 161 rc = !*refcnt; 162 } 163 } else { 164 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 165 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 166 } 167 168 return rc; 169 } 170 171 static inline int incr_refcnt(unsigned int *refcnt) 172 { 173 return incr_shrefcnt(refcnt, true); 174 } 175 176 static inline int decr_refcnt(unsigned int *refcnt) 177 { 178 return decr_shrefcnt(refcnt, true); 179 } 180 181 /* 182 * Shared peripherals and resources registration 183 * 184 * Resources listed in enum stm32mp_shres assigned at run-time to the 185 * non-secure world, to the secure world or shared by both worlds. 186 * In the later case, there must exist a secure service in OP-TEE 187 * for the non-secure world to access the resource. 188 * 189 * Resources may be a peripheral, a bus, a clock or a memory. 190 * 191 * Shared resources driver API functions allows drivers to register the 192 * resource as secure, non-secure or shared and to get the resource 193 * assignation state. 194 */ 195 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 196 197 enum stm32mp_shres { 198 STM32MP1_SHRES_GPIOZ_0 = 0, 199 STM32MP1_SHRES_GPIOZ_1, 200 STM32MP1_SHRES_GPIOZ_2, 201 STM32MP1_SHRES_GPIOZ_3, 202 STM32MP1_SHRES_GPIOZ_4, 203 STM32MP1_SHRES_GPIOZ_5, 204 STM32MP1_SHRES_GPIOZ_6, 205 STM32MP1_SHRES_GPIOZ_7, 206 STM32MP1_SHRES_IWDG1, 207 STM32MP1_SHRES_USART1, 208 STM32MP1_SHRES_SPI6, 209 STM32MP1_SHRES_I2C4, 210 STM32MP1_SHRES_RNG1, 211 STM32MP1_SHRES_HASH1, 212 STM32MP1_SHRES_CRYP1, 213 STM32MP1_SHRES_I2C6, 214 STM32MP1_SHRES_RTC, 215 STM32MP1_SHRES_MCU, 216 STM32MP1_SHRES_PLL3, 217 STM32MP1_SHRES_MDMA, 218 219 STM32MP1_SHRES_COUNT 220 }; 221 222 #ifdef CFG_STM32MP1_SHARED_RESOURCES 223 /* Register resource @id as a secure peripheral */ 224 void stm32mp_register_secure_periph(enum stm32mp_shres id); 225 226 /* Register resource @id as a non-secure peripheral */ 227 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 228 229 /* 230 * Register resource identified by @base as a secure peripheral 231 * @base: IOMEM physical base address of the resource 232 */ 233 void stm32mp_register_secure_periph_iomem(vaddr_t base); 234 235 /* 236 * Register resource identified by @base as a non-secure peripheral 237 * @base: IOMEM physical base address of the resource 238 */ 239 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 240 241 /* 242 * Register GPIO resource as a secure peripheral 243 * @bank: Bank of the target GPIO 244 * @pin: Bit position of the target GPIO in the bank 245 */ 246 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 247 248 /* 249 * Register GPIO resource as a non-secure peripheral 250 * @bank: Bank of the target GPIO 251 * @pin: Bit position of the target GPIO in the bank 252 */ 253 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 254 255 /* Return true if and only if resource @id is registered as secure */ 256 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 257 258 /* Return true if and only if GPIO bank @bank is registered as secure */ 259 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 260 261 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 262 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 263 264 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 265 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 266 267 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 268 269 static inline void stm32mp_register_secure_periph(enum stm32mp_shres id 270 __unused) 271 { 272 } 273 274 static inline void stm32mp_register_non_secure_periph(enum stm32mp_shres id 275 __unused) 276 { 277 } 278 279 static inline void stm32mp_register_secure_periph_iomem(vaddr_t base __unused) 280 { 281 } 282 283 static inline void stm32mp_register_non_secure_periph_iomem(vaddr_t base 284 __unused) 285 { 286 } 287 288 static inline void stm32mp_register_secure_gpio(unsigned int bank __unused, 289 unsigned int pin __unused) 290 { 291 } 292 293 static inline void stm32mp_register_non_secure_gpio(unsigned int bank __unused, 294 unsigned int pin __unused) 295 { 296 } 297 298 static inline bool stm32mp_periph_is_secure(enum stm32mp_shres id __unused) 299 { 300 return true; 301 } 302 303 static inline bool stm32mp_gpio_bank_is_secure(unsigned int bank __unused) 304 { 305 return true; 306 } 307 308 static inline bool stm32mp_gpio_bank_is_non_secure(unsigned int bank __unused) 309 { 310 return false; 311 } 312 313 static inline void stm32mp_register_clock_parents_secure(unsigned long clock_id 314 __unused) 315 { 316 } 317 318 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 319 #endif /*__STM32_UTIL_H__*/ 320