1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/stm32_bsec.h> 11 #include <kernel/panic.h> 12 #include <stdint.h> 13 #include <types_ext.h> 14 15 /* Backup registers and RAM utils */ 16 vaddr_t stm32mp_bkpreg(unsigned int idx); 17 18 /* Platform util for the GIC */ 19 vaddr_t get_gicc_base(void); 20 vaddr_t get_gicd_base(void); 21 22 /* 23 * Platform util functions for the GPIO driver 24 * @bank: Target GPIO bank ID as per DT bindings 25 * 26 * Platform shall implement these functions to provide to stm32_gpio 27 * driver the resource reference for a target GPIO bank. That are 28 * memory mapped interface base address, interface offset (see below) 29 * and clock identifier. 30 * 31 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 32 * check DT configuration matches platform implementation of the banks 33 * description. 34 */ 35 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 36 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 37 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 38 39 /* Power management service */ 40 #ifdef CFG_PSCI_ARM32 41 void stm32mp_register_online_cpu(void); 42 #else 43 static inline void stm32mp_register_online_cpu(void) 44 { 45 } 46 #endif 47 48 /* 49 * Generic spinlock function that bypass spinlock if MMU is disabled or 50 * lock is NULL. 51 */ 52 uint32_t may_spin_lock(unsigned int *lock); 53 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 54 55 /* 56 * Util for clock gating and to get clock rate for stm32 and platform drivers 57 * @id: Target clock ID, ID used in clock DT bindings 58 */ 59 void stm32_clock_enable(unsigned long id); 60 void stm32_clock_disable(unsigned long id); 61 unsigned long stm32_clock_get_rate(unsigned long id); 62 bool stm32_clock_is_enabled(unsigned long id); 63 64 /* 65 * Util for reset signal assertion/desassertion for stm32 and platform drivers 66 * @id: Target peripheral ID, ID used in reset DT bindings 67 */ 68 void stm32_reset_assert(unsigned int id); 69 void stm32_reset_deassert(unsigned int id); 70 71 /* 72 * Structure and API function for BSEC driver to get some platform data. 73 * 74 * @base: BSEC interface registers physical base address 75 * @upper_start: Base ID for the BSEC upper words in the platform 76 * @max_id: Max value for BSEC word ID for the platform 77 * @closed_device_id: BSEC word ID storing the "closed_device" OTP bit 78 * @closed_device_position: Bit position of "closed_device" bit in the OTP word 79 */ 80 struct stm32_bsec_static_cfg { 81 paddr_t base; 82 unsigned int upper_start; 83 unsigned int max_id; 84 unsigned int closed_device_id; 85 unsigned int closed_device_position; 86 }; 87 88 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 89 90 /* 91 * Return true if platform is in closed_device mode 92 */ 93 bool stm32mp_is_closed_device(void); 94 95 /* 96 * Shared registers support: common lock for accessing SoC registers 97 * shared between several drivers. 98 */ 99 void io_mask32_stm32shregs(vaddr_t va, uint32_t value, uint32_t mask); 100 101 static inline void io_setbits32_stm32shregs(vaddr_t va, uint32_t value) 102 { 103 io_mask32_stm32shregs(va, value, value); 104 } 105 106 static inline void io_clrbits32_stm32shregs(vaddr_t va, uint32_t value) 107 { 108 io_mask32_stm32shregs(va, 0, value); 109 } 110 111 void io_clrsetbits32_stm32shregs(vaddr_t va, uint32_t clr, uint32_t set); 112 113 /* 114 * Shared reference counter: increments by 2 on secure increment 115 * request, decrements by 2 on secure decrement request. Bit #0 116 * is set to 1 on non-secure increment request and reset to 0 on 117 * non-secure decrement request. These counters initialize to 118 * either 0, 1 or 2 upon their expect default state. 119 * Counters saturate to UINT_MAX / 2. 120 */ 121 #define SHREFCNT_NONSECURE_FLAG 0x1ul 122 #define SHREFCNT_SECURE_STEP 0x2ul 123 #define SHREFCNT_MAX (UINT_MAX / 2) 124 125 /* Return 1 if refcnt increments from 0, else return 0 */ 126 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 127 { 128 int rc = !*refcnt; 129 130 if (secure) { 131 if (*refcnt < SHREFCNT_MAX) { 132 *refcnt += SHREFCNT_SECURE_STEP; 133 assert(*refcnt < SHREFCNT_MAX); 134 } 135 } else { 136 *refcnt |= SHREFCNT_NONSECURE_FLAG; 137 } 138 139 return rc; 140 } 141 142 /* Return 1 if refcnt decrements to 0, else return 0 */ 143 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 144 { 145 int rc = 0; 146 147 if (secure) { 148 if (*refcnt < SHREFCNT_MAX) { 149 if (*refcnt < SHREFCNT_SECURE_STEP) 150 panic(); 151 152 *refcnt -= SHREFCNT_SECURE_STEP; 153 rc = !*refcnt; 154 } 155 } else { 156 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 157 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 158 } 159 160 return rc; 161 } 162 163 static inline int incr_refcnt(unsigned int *refcnt) 164 { 165 return incr_shrefcnt(refcnt, true); 166 } 167 168 static inline int decr_refcnt(unsigned int *refcnt) 169 { 170 return decr_shrefcnt(refcnt, true); 171 } 172 173 /* 174 * Shared peripherals and resources registration 175 * 176 * Resources listed in enum stm32mp_shres assigned at run-time to the 177 * non-secure world, to the secure world or shared by both worlds. 178 * In the later case, there must exist a secure service in OP-TEE 179 * for the non-secure world to access the resource. 180 * 181 * Resources may be a peripheral, a bus, a clock or a memory. 182 * 183 * Shared resources driver API functions allows drivers to register the 184 * resource as secure, non-secure or shared and to get the resource 185 * assignation state. 186 */ 187 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 188 189 enum stm32mp_shres { 190 STM32MP1_SHRES_GPIOZ_0 = 0, 191 STM32MP1_SHRES_GPIOZ_1, 192 STM32MP1_SHRES_GPIOZ_2, 193 STM32MP1_SHRES_GPIOZ_3, 194 STM32MP1_SHRES_GPIOZ_4, 195 STM32MP1_SHRES_GPIOZ_5, 196 STM32MP1_SHRES_GPIOZ_6, 197 STM32MP1_SHRES_GPIOZ_7, 198 STM32MP1_SHRES_IWDG1, 199 STM32MP1_SHRES_USART1, 200 STM32MP1_SHRES_SPI6, 201 STM32MP1_SHRES_I2C4, 202 STM32MP1_SHRES_RNG1, 203 STM32MP1_SHRES_HASH1, 204 STM32MP1_SHRES_CRYP1, 205 STM32MP1_SHRES_I2C6, 206 STM32MP1_SHRES_RTC, 207 STM32MP1_SHRES_MCU, 208 STM32MP1_SHRES_HSI, 209 STM32MP1_SHRES_LSI, 210 STM32MP1_SHRES_HSE, 211 STM32MP1_SHRES_LSE, 212 STM32MP1_SHRES_CSI, 213 STM32MP1_SHRES_PLL1, 214 STM32MP1_SHRES_PLL1_P, 215 STM32MP1_SHRES_PLL1_Q, 216 STM32MP1_SHRES_PLL1_R, 217 STM32MP1_SHRES_PLL2, 218 STM32MP1_SHRES_PLL2_P, 219 STM32MP1_SHRES_PLL2_Q, 220 STM32MP1_SHRES_PLL2_R, 221 STM32MP1_SHRES_PLL3, 222 STM32MP1_SHRES_PLL3_P, 223 STM32MP1_SHRES_PLL3_Q, 224 STM32MP1_SHRES_PLL3_R, 225 STM32MP1_SHRES_COUNT 226 }; 227 228 /* Register resource @id as a secure peripheral */ 229 void stm32mp_register_secure_periph(enum stm32mp_shres id); 230 231 /* Register resource @id as a non-secure peripheral */ 232 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 233 234 /* 235 * Register resource identified by @base as a secure peripheral 236 * @base: IOMEM physical base address of the resource 237 */ 238 void stm32mp_register_secure_periph_iomem(vaddr_t base); 239 240 /* 241 * Register resource identified by @base as a non-secure peripheral 242 * @base: IOMEM physical base address of the resource 243 */ 244 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 245 246 /* 247 * Register GPIO resource as a secure peripheral 248 * @bank: Bank of the target GPIO 249 * @pin: Bit position of the target GPIO in the bank 250 */ 251 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 252 253 /* 254 * Register GPIO resource as a non-secure peripheral 255 * @bank: Bank of the target GPIO 256 * @pin: Bit position of the target GPIO in the bank 257 */ 258 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 259 260 /* Return true if and only if resource @id is registered as secure */ 261 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 262 263 /* Return true if and only if GPIO bank @bank is registered as secure */ 264 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 265 266 /* Return true if and only if GPIO bank @bank is registered as shared */ 267 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 268 269 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 270 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 271 272 /* Return true if and only if @clock_id is shareable */ 273 bool stm32mp_clock_is_shareable(unsigned long clock_id); 274 275 /* Return true if and only if @clock_id is shared by secure and non-secure */ 276 bool stm32mp_clock_is_shared(unsigned long clock_id); 277 278 /* Return true if and only if @clock_id is assigned to non-secure world */ 279 bool stm32mp_clock_is_non_secure(unsigned long clock_id); 280 281 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 282 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 283 284 #endif /*__STM32_UTIL_H__*/ 285