1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2022, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/pinctrl.h> 12 #include <drivers/stm32_bsec.h> 13 #include <kernel/panic.h> 14 #include <stdint.h> 15 #include <tee_api_types.h> 16 #include <types_ext.h> 17 18 /* Backup registers and RAM utils */ 19 vaddr_t stm32mp_bkpreg(unsigned int idx); 20 21 /* 22 * SYSCFG IO compensation. 23 * These functions assume non-secure world is suspended. 24 */ 25 void stm32mp_syscfg_enable_io_compensation(void); 26 void stm32mp_syscfg_disable_io_compensation(void); 27 28 /* Platform util for the RCC drivers */ 29 vaddr_t stm32_rcc_base(void); 30 31 /* Platform util for the GIC */ 32 vaddr_t get_gicd_base(void); 33 34 /* 35 * Platform util functions for the GPIO driver 36 * @bank: Target GPIO bank ID as per DT bindings 37 * 38 * Platform shall implement these functions to provide to stm32_gpio 39 * driver the resource reference for a target GPIO bank. That are 40 * memory mapped interface base address, interface offset (see below) 41 * and clock identifier. 42 * 43 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 44 * check DT configuration matches platform implementation of the banks 45 * description. 46 */ 47 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 48 49 /* Platform util for PMIC support */ 50 bool stm32mp_with_pmic(void); 51 52 /* Power management service */ 53 #ifdef CFG_PSCI_ARM32 54 void stm32mp_register_online_cpu(void); 55 #else 56 static inline void stm32mp_register_online_cpu(void) 57 { 58 } 59 #endif 60 61 /* 62 * Generic spinlock function that bypass spinlock if MMU is disabled or 63 * lock is NULL. 64 */ 65 uint32_t may_spin_lock(unsigned int *lock); 66 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 67 68 /* Helper from platform RCC clock driver */ 69 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id); 70 71 #ifdef CFG_STM32MP1_SHARED_RESOURCES 72 /* Return true if @clock_id is shared by secure and non-secure worlds */ 73 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 74 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 75 static inline bool stm32mp_nsec_can_access_clock(unsigned long clock_id 76 __unused) 77 { 78 return true; 79 } 80 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 81 82 extern const struct clk_ops stm32mp1_clk_ops; 83 84 #if defined(CFG_STPMIC1) 85 /* Return true if non-secure world can manipulate regulator @pmic_regu_name */ 86 bool stm32mp_nsec_can_access_pmic_regu(const char *pmic_regu_name); 87 #else 88 static inline bool stm32mp_nsec_can_access_pmic_regu(const char *name __unused) 89 { 90 return false; 91 } 92 #endif 93 94 #ifdef CFG_STM32MP1_SHARED_RESOURCES 95 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 96 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 97 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 98 static inline bool stm32mp_nsec_can_access_reset(unsigned int reset_id __unused) 99 { 100 return true; 101 } 102 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 103 104 /* Return rstctrl instance related to RCC reset controller DT binding ID */ 105 struct rstctrl *stm32mp_rcc_reset_id_to_rstctrl(unsigned int binding_id); 106 107 /* 108 * Structure and API function for BSEC driver to get some platform data. 109 * 110 * @base: BSEC interface registers physical base address 111 * @upper_start: Base ID for the BSEC upper words in the platform 112 * @max_id: Max value for BSEC word ID for the platform 113 */ 114 struct stm32_bsec_static_cfg { 115 paddr_t base; 116 unsigned int upper_start; 117 unsigned int max_id; 118 }; 119 120 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 121 122 /* 123 * Shared reference counter: increments by 2 on secure increment 124 * request, decrements by 2 on secure decrement request. Bit #0 125 * is set to 1 on non-secure increment request and reset to 0 on 126 * non-secure decrement request. These counters initialize to 127 * either 0, 1 or 2 upon their expect default state. 128 * Counters saturate to UINT_MAX / 2. 129 */ 130 #define SHREFCNT_NONSECURE_FLAG 0x1ul 131 #define SHREFCNT_SECURE_STEP 0x2ul 132 #define SHREFCNT_MAX (UINT_MAX / 2) 133 134 /* Return 1 if refcnt increments from 0, else return 0 */ 135 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 136 { 137 int rc = !*refcnt; 138 139 if (secure) { 140 if (*refcnt < SHREFCNT_MAX) { 141 *refcnt += SHREFCNT_SECURE_STEP; 142 assert(*refcnt < SHREFCNT_MAX); 143 } 144 } else { 145 *refcnt |= SHREFCNT_NONSECURE_FLAG; 146 } 147 148 return rc; 149 } 150 151 /* Return 1 if refcnt decrements to 0, else return 0 */ 152 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 153 { 154 int rc = 0; 155 156 if (secure) { 157 if (*refcnt < SHREFCNT_MAX) { 158 if (*refcnt < SHREFCNT_SECURE_STEP) 159 panic(); 160 161 *refcnt -= SHREFCNT_SECURE_STEP; 162 rc = !*refcnt; 163 } 164 } else { 165 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 166 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 167 } 168 169 return rc; 170 } 171 172 static inline int incr_refcnt(unsigned int *refcnt) 173 { 174 return incr_shrefcnt(refcnt, true); 175 } 176 177 static inline int decr_refcnt(unsigned int *refcnt) 178 { 179 return decr_shrefcnt(refcnt, true); 180 } 181 182 /* 183 * Shared peripherals and resources registration 184 * 185 * Resources listed in enum stm32mp_shres assigned at run-time to the 186 * non-secure world, to the secure world or shared by both worlds. 187 * In the later case, there must exist a secure service in OP-TEE 188 * for the non-secure world to access the resource. 189 * 190 * Resources may be a peripheral, a bus, a clock or a memory. 191 * 192 * Shared resources driver API functions allows drivers to register the 193 * resource as secure, non-secure or shared and to get the resource 194 * assignation state. 195 */ 196 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 197 198 enum stm32mp_shres { 199 STM32MP1_SHRES_GPIOZ_0 = 0, 200 STM32MP1_SHRES_GPIOZ_1, 201 STM32MP1_SHRES_GPIOZ_2, 202 STM32MP1_SHRES_GPIOZ_3, 203 STM32MP1_SHRES_GPIOZ_4, 204 STM32MP1_SHRES_GPIOZ_5, 205 STM32MP1_SHRES_GPIOZ_6, 206 STM32MP1_SHRES_GPIOZ_7, 207 STM32MP1_SHRES_IWDG1, 208 STM32MP1_SHRES_USART1, 209 STM32MP1_SHRES_SPI6, 210 STM32MP1_SHRES_I2C4, 211 STM32MP1_SHRES_RNG1, 212 STM32MP1_SHRES_HASH1, 213 STM32MP1_SHRES_CRYP1, 214 STM32MP1_SHRES_I2C6, 215 STM32MP1_SHRES_RTC, 216 STM32MP1_SHRES_MCU, 217 STM32MP1_SHRES_PLL3, 218 STM32MP1_SHRES_MDMA, 219 STM32MP1_SHRES_SRAM1, 220 STM32MP1_SHRES_SRAM2, 221 STM32MP1_SHRES_SRAM3, 222 STM32MP1_SHRES_SRAM4, 223 224 STM32MP1_SHRES_COUNT 225 }; 226 227 #ifdef CFG_STM32MP1_SHARED_RESOURCES 228 /* Register resource @id as a secure peripheral */ 229 void stm32mp_register_secure_periph(enum stm32mp_shres id); 230 231 /* Register resource @id as a non-secure peripheral */ 232 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 233 234 /* 235 * Register resource identified by @base as a secure peripheral 236 * @base: IOMEM physical base address of the resource 237 */ 238 void stm32mp_register_secure_periph_iomem(vaddr_t base); 239 240 /* 241 * Register resource identified by @base as a non-secure peripheral 242 * @base: IOMEM physical base address of the resource 243 */ 244 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 245 246 /* 247 * Register GPIO resource as a secure peripheral 248 * @bank: Bank of the target GPIO 249 * @pin: Bit position of the target GPIO in the bank 250 */ 251 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 252 253 /* 254 * Register GPIO resource as a non-secure peripheral 255 * @bank: Bank of the target GPIO 256 * @pin: Bit position of the target GPIO in the bank 257 */ 258 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 259 260 /* 261 * Register pin resource of a pin control state as a secure peripheral 262 * @bank: Bank of the target GPIO 263 * @pin: Bit position of the target GPIO in the bank 264 */ 265 void stm32mp_register_secure_pinctrl(struct pinctrl_state *pinctrl); 266 267 /* 268 * Register pin resource of a pin control state as a non-secure peripheral 269 * @bank: Bank of the target GPIO 270 * @pin: Bit position of the target GPIO in the bank 271 */ 272 void stm32mp_register_non_secure_pinctrl(struct pinctrl_state *pinctrl); 273 274 /* Return true if and only if resource @id is registered as secure */ 275 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 276 277 /* Return true if and only if GPIO bank @bank is registered as secure */ 278 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 279 280 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 281 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 282 283 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 284 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 285 286 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 287 288 static inline void stm32mp_register_secure_periph(enum stm32mp_shres id 289 __unused) 290 { 291 } 292 293 static inline void stm32mp_register_non_secure_periph(enum stm32mp_shres id 294 __unused) 295 { 296 } 297 298 static inline void stm32mp_register_secure_periph_iomem(vaddr_t base __unused) 299 { 300 } 301 302 static inline void stm32mp_register_non_secure_periph_iomem(vaddr_t base 303 __unused) 304 { 305 } 306 307 static inline void stm32mp_register_secure_gpio(unsigned int bank __unused, 308 unsigned int pin __unused) 309 { 310 } 311 312 static inline void stm32mp_register_non_secure_gpio(unsigned int bank __unused, 313 unsigned int pin __unused) 314 { 315 } 316 317 static inline void 318 stm32mp_register_secure_pinctrl(struct pinctrl_state *pinctrl __unused) 319 { 320 } 321 322 static inline void 323 stm32mp_register_non_secure_pinctrl(struct pinctrl_state *pinctrl __unused) 324 { 325 } 326 327 static inline bool stm32mp_periph_is_secure(enum stm32mp_shres id __unused) 328 { 329 return true; 330 } 331 332 static inline bool stm32mp_gpio_bank_is_secure(unsigned int bank __unused) 333 { 334 return true; 335 } 336 337 static inline bool stm32mp_gpio_bank_is_non_secure(unsigned int bank __unused) 338 { 339 return false; 340 } 341 342 static inline void stm32mp_register_clock_parents_secure(unsigned long clock_id 343 __unused) 344 { 345 } 346 347 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 348 #endif /*__STM32_UTIL_H__*/ 349