1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/stm32_bsec.h> 11 #include <kernel/panic.h> 12 #include <stdint.h> 13 #include <types_ext.h> 14 15 /* Backup registers and RAM utils */ 16 vaddr_t stm32mp_bkpreg(unsigned int idx); 17 18 /* Platform util for the GIC */ 19 vaddr_t get_gicc_base(void); 20 vaddr_t get_gicd_base(void); 21 22 /* 23 * Platform util functions for the GPIO driver 24 * @bank: Target GPIO bank ID as per DT bindings 25 * 26 * Platform shall implement these functions to provide to stm32_gpio 27 * driver the resource reference for a target GPIO bank. That are 28 * memory mapped interface base address, interface offset (see below) 29 * and clock identifier. 30 * 31 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 32 * check DT configuration matches platform implementation of the banks 33 * description. 34 */ 35 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 36 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 37 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 38 39 /* Power management service */ 40 #ifdef CFG_PSCI_ARM32 41 void stm32mp_register_online_cpu(void); 42 #else 43 static inline void stm32mp_register_online_cpu(void) 44 { 45 } 46 #endif 47 48 /* 49 * Generic spinlock function that bypass spinlock if MMU is disabled or 50 * lock is NULL. 51 */ 52 uint32_t may_spin_lock(unsigned int *lock); 53 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 54 55 /* 56 * Util for clock gating and to get clock rate for stm32 and platform drivers 57 * @id: Target clock ID, ID used in clock DT bindings 58 */ 59 void stm32_clock_enable(unsigned long id); 60 void stm32_clock_disable(unsigned long id); 61 unsigned long stm32_clock_get_rate(unsigned long id); 62 bool stm32_clock_is_enabled(unsigned long id); 63 64 /* 65 * Util for reset signal assertion/desassertion for stm32 and platform drivers 66 * @id: Target peripheral ID, ID used in reset DT bindings 67 */ 68 void stm32_reset_assert(unsigned int id); 69 void stm32_reset_deassert(unsigned int id); 70 71 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 72 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 73 74 /* 75 * Structure and API function for BSEC driver to get some platform data. 76 * 77 * @base: BSEC interface registers physical base address 78 * @upper_start: Base ID for the BSEC upper words in the platform 79 * @max_id: Max value for BSEC word ID for the platform 80 * @closed_device_id: BSEC word ID storing the "closed_device" OTP bit 81 * @closed_device_position: Bit position of "closed_device" bit in the OTP word 82 */ 83 struct stm32_bsec_static_cfg { 84 paddr_t base; 85 unsigned int upper_start; 86 unsigned int max_id; 87 unsigned int closed_device_id; 88 unsigned int closed_device_position; 89 }; 90 91 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 92 93 /* 94 * Return true if platform is in closed_device mode 95 */ 96 bool stm32mp_is_closed_device(void); 97 98 /* 99 * Shared registers support: common lock for accessing SoC registers 100 * shared between several drivers. 101 */ 102 void io_mask32_stm32shregs(vaddr_t va, uint32_t value, uint32_t mask); 103 104 static inline void io_setbits32_stm32shregs(vaddr_t va, uint32_t value) 105 { 106 io_mask32_stm32shregs(va, value, value); 107 } 108 109 static inline void io_clrbits32_stm32shregs(vaddr_t va, uint32_t value) 110 { 111 io_mask32_stm32shregs(va, 0, value); 112 } 113 114 void io_clrsetbits32_stm32shregs(vaddr_t va, uint32_t clr, uint32_t set); 115 116 /* 117 * Shared reference counter: increments by 2 on secure increment 118 * request, decrements by 2 on secure decrement request. Bit #0 119 * is set to 1 on non-secure increment request and reset to 0 on 120 * non-secure decrement request. These counters initialize to 121 * either 0, 1 or 2 upon their expect default state. 122 * Counters saturate to UINT_MAX / 2. 123 */ 124 #define SHREFCNT_NONSECURE_FLAG 0x1ul 125 #define SHREFCNT_SECURE_STEP 0x2ul 126 #define SHREFCNT_MAX (UINT_MAX / 2) 127 128 /* Return 1 if refcnt increments from 0, else return 0 */ 129 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 130 { 131 int rc = !*refcnt; 132 133 if (secure) { 134 if (*refcnt < SHREFCNT_MAX) { 135 *refcnt += SHREFCNT_SECURE_STEP; 136 assert(*refcnt < SHREFCNT_MAX); 137 } 138 } else { 139 *refcnt |= SHREFCNT_NONSECURE_FLAG; 140 } 141 142 return rc; 143 } 144 145 /* Return 1 if refcnt decrements to 0, else return 0 */ 146 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 147 { 148 int rc = 0; 149 150 if (secure) { 151 if (*refcnt < SHREFCNT_MAX) { 152 if (*refcnt < SHREFCNT_SECURE_STEP) 153 panic(); 154 155 *refcnt -= SHREFCNT_SECURE_STEP; 156 rc = !*refcnt; 157 } 158 } else { 159 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 160 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 161 } 162 163 return rc; 164 } 165 166 static inline int incr_refcnt(unsigned int *refcnt) 167 { 168 return incr_shrefcnt(refcnt, true); 169 } 170 171 static inline int decr_refcnt(unsigned int *refcnt) 172 { 173 return decr_shrefcnt(refcnt, true); 174 } 175 176 /* 177 * Shared peripherals and resources registration 178 * 179 * Resources listed in enum stm32mp_shres assigned at run-time to the 180 * non-secure world, to the secure world or shared by both worlds. 181 * In the later case, there must exist a secure service in OP-TEE 182 * for the non-secure world to access the resource. 183 * 184 * Resources may be a peripheral, a bus, a clock or a memory. 185 * 186 * Shared resources driver API functions allows drivers to register the 187 * resource as secure, non-secure or shared and to get the resource 188 * assignation state. 189 */ 190 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 191 192 enum stm32mp_shres { 193 STM32MP1_SHRES_GPIOZ_0 = 0, 194 STM32MP1_SHRES_GPIOZ_1, 195 STM32MP1_SHRES_GPIOZ_2, 196 STM32MP1_SHRES_GPIOZ_3, 197 STM32MP1_SHRES_GPIOZ_4, 198 STM32MP1_SHRES_GPIOZ_5, 199 STM32MP1_SHRES_GPIOZ_6, 200 STM32MP1_SHRES_GPIOZ_7, 201 STM32MP1_SHRES_IWDG1, 202 STM32MP1_SHRES_USART1, 203 STM32MP1_SHRES_SPI6, 204 STM32MP1_SHRES_I2C4, 205 STM32MP1_SHRES_RNG1, 206 STM32MP1_SHRES_HASH1, 207 STM32MP1_SHRES_CRYP1, 208 STM32MP1_SHRES_I2C6, 209 STM32MP1_SHRES_RTC, 210 STM32MP1_SHRES_MCU, 211 STM32MP1_SHRES_HSI, 212 STM32MP1_SHRES_LSI, 213 STM32MP1_SHRES_HSE, 214 STM32MP1_SHRES_LSE, 215 STM32MP1_SHRES_CSI, 216 STM32MP1_SHRES_PLL1, 217 STM32MP1_SHRES_PLL1_P, 218 STM32MP1_SHRES_PLL1_Q, 219 STM32MP1_SHRES_PLL1_R, 220 STM32MP1_SHRES_PLL2, 221 STM32MP1_SHRES_PLL2_P, 222 STM32MP1_SHRES_PLL2_Q, 223 STM32MP1_SHRES_PLL2_R, 224 STM32MP1_SHRES_PLL3, 225 STM32MP1_SHRES_PLL3_P, 226 STM32MP1_SHRES_PLL3_Q, 227 STM32MP1_SHRES_PLL3_R, 228 STM32MP1_SHRES_MDMA, 229 STM32MP1_SHRES_COUNT 230 }; 231 232 /* Register resource @id as a secure peripheral */ 233 void stm32mp_register_secure_periph(enum stm32mp_shres id); 234 235 /* Register resource @id as a non-secure peripheral */ 236 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 237 238 /* 239 * Register resource identified by @base as a secure peripheral 240 * @base: IOMEM physical base address of the resource 241 */ 242 void stm32mp_register_secure_periph_iomem(vaddr_t base); 243 244 /* 245 * Register resource identified by @base as a non-secure peripheral 246 * @base: IOMEM physical base address of the resource 247 */ 248 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 249 250 /* 251 * Register GPIO resource as a secure peripheral 252 * @bank: Bank of the target GPIO 253 * @pin: Bit position of the target GPIO in the bank 254 */ 255 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 256 257 /* 258 * Register GPIO resource as a non-secure peripheral 259 * @bank: Bank of the target GPIO 260 * @pin: Bit position of the target GPIO in the bank 261 */ 262 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 263 264 /* Return true if and only if resource @id is registered as secure */ 265 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 266 267 /* Return true if and only if GPIO bank @bank is registered as secure */ 268 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 269 270 /* Return true if and only if GPIO bank @bank is registered as shared */ 271 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 272 273 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 274 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 275 276 /* Return true if and only if @clock_id is shareable */ 277 bool stm32mp_clock_is_shareable(unsigned long clock_id); 278 279 /* Return true if and only if @clock_id is shared by secure and non-secure */ 280 bool stm32mp_clock_is_shared(unsigned long clock_id); 281 282 /* Return true if and only if @clock_id is assigned to non-secure world */ 283 bool stm32mp_clock_is_non_secure(unsigned long clock_id); 284 285 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 286 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 287 288 #endif /*__STM32_UTIL_H__*/ 289