1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/stm32_bsec.h> 12 #include <kernel/panic.h> 13 #include <stdint.h> 14 #include <types_ext.h> 15 16 /* Backup registers and RAM utils */ 17 vaddr_t stm32mp_bkpreg(unsigned int idx); 18 19 /* 20 * SYSCFG IO compensation. 21 * These functions assume non-secure world is suspended. 22 */ 23 void stm32mp_syscfg_enable_io_compensation(void); 24 void stm32mp_syscfg_disable_io_compensation(void); 25 26 /* Platform util for the RCC drivers */ 27 vaddr_t stm32_rcc_base(void); 28 29 /* Platform util for the GIC */ 30 vaddr_t get_gicd_base(void); 31 32 /* 33 * Platform util functions for the GPIO driver 34 * @bank: Target GPIO bank ID as per DT bindings 35 * 36 * Platform shall implement these functions to provide to stm32_gpio 37 * driver the resource reference for a target GPIO bank. That are 38 * memory mapped interface base address, interface offset (see below) 39 * and clock identifier. 40 * 41 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 42 * check DT configuration matches platform implementation of the banks 43 * description. 44 */ 45 vaddr_t stm32_get_gpio_bank_base(unsigned int bank); 46 unsigned int stm32_get_gpio_bank_offset(unsigned int bank); 47 unsigned int stm32_get_gpio_bank_clock(unsigned int bank); 48 struct clk *stm32_get_gpio_bank_clk(unsigned int bank); 49 50 /* Platform util for PMIC support */ 51 bool stm32mp_with_pmic(void); 52 53 /* Power management service */ 54 #ifdef CFG_PSCI_ARM32 55 void stm32mp_register_online_cpu(void); 56 #else 57 static inline void stm32mp_register_online_cpu(void) 58 { 59 } 60 #endif 61 62 /* 63 * Generic spinlock function that bypass spinlock if MMU is disabled or 64 * lock is NULL. 65 */ 66 uint32_t may_spin_lock(unsigned int *lock); 67 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 68 69 /* Helper from platform RCC drivers */ 70 struct rstctrl *stm32mp_rcc_reset_id_to_rstctrl(unsigned int binding_id); 71 72 /* 73 * Util for clock gating and to get clock rate for stm32 and platform drivers 74 * @id: Target clock ID, ID used in clock DT bindings 75 */ 76 void stm32_clock_enable(unsigned long id); 77 void stm32_clock_disable(unsigned long id); 78 unsigned long stm32_clock_get_rate(unsigned long id); 79 bool stm32_clock_is_enabled(unsigned long id); 80 81 /* Helper from platform RCC clock driver */ 82 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id); 83 84 /* Return true if @clock_id is shared by secure and non-secure worlds */ 85 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 86 87 extern const struct clk_ops stm32mp1_clk_ops; 88 89 #if defined(CFG_STPMIC1) 90 /* Return true if non-secure world can manipulate regulator @pmic_regu_name */ 91 bool stm32mp_nsec_can_access_pmic_regu(const char *pmic_regu_name); 92 #else 93 static inline bool stm32mp_nsec_can_access_pmic_regu(const char *name __unused) 94 { 95 return false; 96 } 97 #endif 98 99 /* 100 * Util for reset signal assertion/desassertion for stm32 and platform drivers 101 * @id: Target peripheral ID, ID used in reset DT bindings 102 * @to_us: Timeout out in microsecond, or 0 if not waiting signal state 103 */ 104 TEE_Result stm32_reset_assert(unsigned int id, unsigned int timeout_us); 105 TEE_Result stm32_reset_deassert(unsigned int id, unsigned int timeout_us); 106 107 /* Specific reset to manage the MCU hold boot */ 108 void stm32_reset_assert_deassert_mcu(bool assert_not_deassert); 109 110 static inline void stm32_reset_set(unsigned int id) 111 { 112 (void)stm32_reset_assert(id, 0); 113 } 114 115 static inline void stm32_reset_release(unsigned int id) 116 { 117 (void)stm32_reset_deassert(id, 0); 118 } 119 120 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 121 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 122 123 /* 124 * Structure and API function for BSEC driver to get some platform data. 125 * 126 * @base: BSEC interface registers physical base address 127 * @upper_start: Base ID for the BSEC upper words in the platform 128 * @max_id: Max value for BSEC word ID for the platform 129 */ 130 struct stm32_bsec_static_cfg { 131 paddr_t base; 132 unsigned int upper_start; 133 unsigned int max_id; 134 }; 135 136 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 137 138 /* 139 * Return true if platform is in closed_device mode 140 */ 141 bool stm32mp_is_closed_device(void); 142 143 /* 144 * Shared registers support: common lock for accessing SoC registers 145 * shared between several drivers. 146 */ 147 void io_mask32_stm32shregs(vaddr_t va, uint32_t value, uint32_t mask); 148 149 static inline void io_setbits32_stm32shregs(vaddr_t va, uint32_t value) 150 { 151 io_mask32_stm32shregs(va, value, value); 152 } 153 154 static inline void io_clrbits32_stm32shregs(vaddr_t va, uint32_t value) 155 { 156 io_mask32_stm32shregs(va, 0, value); 157 } 158 159 void io_clrsetbits32_stm32shregs(vaddr_t va, uint32_t clr, uint32_t set); 160 161 /* 162 * Shared reference counter: increments by 2 on secure increment 163 * request, decrements by 2 on secure decrement request. Bit #0 164 * is set to 1 on non-secure increment request and reset to 0 on 165 * non-secure decrement request. These counters initialize to 166 * either 0, 1 or 2 upon their expect default state. 167 * Counters saturate to UINT_MAX / 2. 168 */ 169 #define SHREFCNT_NONSECURE_FLAG 0x1ul 170 #define SHREFCNT_SECURE_STEP 0x2ul 171 #define SHREFCNT_MAX (UINT_MAX / 2) 172 173 /* Return 1 if refcnt increments from 0, else return 0 */ 174 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 175 { 176 int rc = !*refcnt; 177 178 if (secure) { 179 if (*refcnt < SHREFCNT_MAX) { 180 *refcnt += SHREFCNT_SECURE_STEP; 181 assert(*refcnt < SHREFCNT_MAX); 182 } 183 } else { 184 *refcnt |= SHREFCNT_NONSECURE_FLAG; 185 } 186 187 return rc; 188 } 189 190 /* Return 1 if refcnt decrements to 0, else return 0 */ 191 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 192 { 193 int rc = 0; 194 195 if (secure) { 196 if (*refcnt < SHREFCNT_MAX) { 197 if (*refcnt < SHREFCNT_SECURE_STEP) 198 panic(); 199 200 *refcnt -= SHREFCNT_SECURE_STEP; 201 rc = !*refcnt; 202 } 203 } else { 204 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 205 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 206 } 207 208 return rc; 209 } 210 211 static inline int incr_refcnt(unsigned int *refcnt) 212 { 213 return incr_shrefcnt(refcnt, true); 214 } 215 216 static inline int decr_refcnt(unsigned int *refcnt) 217 { 218 return decr_shrefcnt(refcnt, true); 219 } 220 221 /* 222 * Shared peripherals and resources registration 223 * 224 * Resources listed in enum stm32mp_shres assigned at run-time to the 225 * non-secure world, to the secure world or shared by both worlds. 226 * In the later case, there must exist a secure service in OP-TEE 227 * for the non-secure world to access the resource. 228 * 229 * Resources may be a peripheral, a bus, a clock or a memory. 230 * 231 * Shared resources driver API functions allows drivers to register the 232 * resource as secure, non-secure or shared and to get the resource 233 * assignation state. 234 */ 235 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 236 237 enum stm32mp_shres { 238 STM32MP1_SHRES_GPIOZ_0 = 0, 239 STM32MP1_SHRES_GPIOZ_1, 240 STM32MP1_SHRES_GPIOZ_2, 241 STM32MP1_SHRES_GPIOZ_3, 242 STM32MP1_SHRES_GPIOZ_4, 243 STM32MP1_SHRES_GPIOZ_5, 244 STM32MP1_SHRES_GPIOZ_6, 245 STM32MP1_SHRES_GPIOZ_7, 246 STM32MP1_SHRES_IWDG1, 247 STM32MP1_SHRES_USART1, 248 STM32MP1_SHRES_SPI6, 249 STM32MP1_SHRES_I2C4, 250 STM32MP1_SHRES_RNG1, 251 STM32MP1_SHRES_HASH1, 252 STM32MP1_SHRES_CRYP1, 253 STM32MP1_SHRES_I2C6, 254 STM32MP1_SHRES_RTC, 255 STM32MP1_SHRES_MCU, 256 STM32MP1_SHRES_PLL3, 257 STM32MP1_SHRES_MDMA, 258 259 STM32MP1_SHRES_COUNT 260 }; 261 262 /* Register resource @id as a secure peripheral */ 263 void stm32mp_register_secure_periph(enum stm32mp_shres id); 264 265 /* Register resource @id as a non-secure peripheral */ 266 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 267 268 /* 269 * Register resource identified by @base as a secure peripheral 270 * @base: IOMEM physical base address of the resource 271 */ 272 void stm32mp_register_secure_periph_iomem(vaddr_t base); 273 274 /* 275 * Register resource identified by @base as a non-secure peripheral 276 * @base: IOMEM physical base address of the resource 277 */ 278 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 279 280 /* 281 * Register GPIO resource as a secure peripheral 282 * @bank: Bank of the target GPIO 283 * @pin: Bit position of the target GPIO in the bank 284 */ 285 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 286 287 /* 288 * Register GPIO resource as a non-secure peripheral 289 * @bank: Bank of the target GPIO 290 * @pin: Bit position of the target GPIO in the bank 291 */ 292 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 293 294 /* Return true if and only if resource @id is registered as secure */ 295 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 296 297 /* Return true if and only if GPIO bank @bank is registered as secure */ 298 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 299 300 /* Return true if and only if GPIO bank @bank is registered as shared */ 301 bool stm32mp_gpio_bank_is_shared(unsigned int bank); 302 303 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 304 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 305 306 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 307 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 308 309 #endif /*__STM32_UTIL_H__*/ 310