1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <confine_array_index.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/rstctrl.h> 11 #include <drivers/scmi-msg.h> 12 #include <drivers/scmi.h> 13 #include <drivers/stm32mp1_pmic.h> 14 #include <drivers/stm32mp1_pwr.h> 15 #include <drivers/stpmic1.h> 16 #include <dt-bindings/clock/stm32mp1-clks.h> 17 #include <dt-bindings/regulator/st,stm32mp15-regulator.h> 18 #include <dt-bindings/reset/stm32mp1-resets.h> 19 #include <initcall.h> 20 #include <mm/core_memprot.h> 21 #include <mm/core_mmu.h> 22 #include <platform_config.h> 23 #include <stdint.h> 24 #include <speculation_barrier.h> 25 #include <stm32_util.h> 26 #include <string.h> 27 #include <tee_api_defines.h> 28 #include <util.h> 29 30 #define TIMEOUT_US_1MS 1000 31 32 #define SCMI_CLOCK_NAME_SIZE 16 33 #define SCMI_RD_NAME_SIZE 16 34 #define SCMI_VOLTD_NAME_SIZE 16 35 36 /* 37 * struct stm32_scmi_clk - Data for the exposed clock 38 * @clock_id: Clock identifier in RCC clock driver 39 * @name: Clock string ID exposed to channel 40 * @enabled: State of the SCMI clock 41 */ 42 struct stm32_scmi_clk { 43 unsigned long clock_id; 44 struct clk *clk; 45 const char *name; 46 bool enabled; 47 }; 48 49 /* 50 * struct stm32_scmi_rd - Data for the exposed reset controller 51 * @reset_id: Reset identifier in RCC reset driver 52 * @name: Reset string ID exposed to channel 53 * @rstctrl: Reset controller device 54 */ 55 struct stm32_scmi_rd { 56 unsigned long reset_id; 57 const char *name; 58 struct rstctrl *rstctrl; 59 }; 60 61 enum voltd_device { 62 VOLTD_PWR, 63 VOLTD_PMIC, 64 }; 65 66 /* 67 * struct stm32_scmi_voltd - Data for the exposed voltage domains 68 * @name: Power regulator string ID exposed to channel 69 * @priv_id: Internal string ID for the regulator 70 * @priv_dev: Internal ID for the device implementing the regulator 71 */ 72 struct stm32_scmi_voltd { 73 const char *name; 74 const char *priv_id; 75 enum voltd_device priv_dev; 76 77 }; 78 79 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 80 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 81 #define SMT_BUFFER0_BASE SMT_BUFFER_BASE 82 #define SMT_BUFFER1_BASE (SMT_BUFFER_BASE + 0x200) 83 84 #if (SMT_BUFFER1_BASE + SMT_BUF_SLOT_SIZE > \ 85 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 86 #error "SCMI shared memory mismatch" 87 #endif 88 89 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 90 CFG_STM32MP1_SCMI_SHM_SIZE); 91 92 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 93 [_scmi_id] = { \ 94 .clock_id = _id, \ 95 .name = _name, \ 96 .enabled = _init_enabled, \ 97 } 98 99 static struct stm32_scmi_clk stm32_scmi0_clock[] = { 100 CLOCK_CELL(CK_SCMI0_HSE, CK_HSE, "ck_hse", true), 101 CLOCK_CELL(CK_SCMI0_HSI, CK_HSI, "ck_hsi", true), 102 CLOCK_CELL(CK_SCMI0_CSI, CK_CSI, "ck_csi", true), 103 CLOCK_CELL(CK_SCMI0_LSE, CK_LSE, "ck_lse", true), 104 CLOCK_CELL(CK_SCMI0_LSI, CK_LSI, "ck_lsi", true), 105 CLOCK_CELL(CK_SCMI0_PLL2_Q, PLL2_Q, "pll2_q", true), 106 CLOCK_CELL(CK_SCMI0_PLL2_R, PLL2_R, "pll2_r", true), 107 CLOCK_CELL(CK_SCMI0_MPU, CK_MPU, "ck_mpu", true), 108 CLOCK_CELL(CK_SCMI0_AXI, CK_AXI, "ck_axi", true), 109 CLOCK_CELL(CK_SCMI0_BSEC, BSEC, "bsec", true), 110 CLOCK_CELL(CK_SCMI0_CRYP1, CRYP1, "cryp1", false), 111 CLOCK_CELL(CK_SCMI0_GPIOZ, GPIOZ, "gpioz", false), 112 CLOCK_CELL(CK_SCMI0_HASH1, HASH1, "hash1", false), 113 CLOCK_CELL(CK_SCMI0_I2C4, I2C4_K, "i2c4_k", false), 114 CLOCK_CELL(CK_SCMI0_I2C6, I2C6_K, "i2c6_k", false), 115 CLOCK_CELL(CK_SCMI0_IWDG1, IWDG1, "iwdg1", false), 116 CLOCK_CELL(CK_SCMI0_RNG1, RNG1_K, "rng1_k", true), 117 CLOCK_CELL(CK_SCMI0_RTC, RTC, "ck_rtc", true), 118 CLOCK_CELL(CK_SCMI0_RTCAPB, RTCAPB, "rtcapb", true), 119 CLOCK_CELL(CK_SCMI0_SPI6, SPI6_K, "spi6_k", false), 120 CLOCK_CELL(CK_SCMI0_USART1, USART1_K, "usart1_k", false), 121 }; 122 123 static struct stm32_scmi_clk stm32_scmi1_clock[] = { 124 CLOCK_CELL(CK_SCMI1_PLL3_Q, PLL3_Q, "pll3_q", true), 125 CLOCK_CELL(CK_SCMI1_PLL3_R, PLL3_R, "pll3_r", true), 126 CLOCK_CELL(CK_SCMI1_MCU, CK_MCU, "ck_mcu", false), 127 }; 128 129 #define RESET_CELL(_scmi_id, _id, _name) \ 130 [_scmi_id] = { \ 131 .reset_id = _id, \ 132 .name = _name, \ 133 } 134 135 static struct stm32_scmi_rd stm32_scmi0_reset_domain[] = { 136 RESET_CELL(RST_SCMI0_SPI6, SPI6_R, "spi6"), 137 RESET_CELL(RST_SCMI0_I2C4, I2C4_R, "i2c4"), 138 RESET_CELL(RST_SCMI0_I2C6, I2C6_R, "i2c6"), 139 RESET_CELL(RST_SCMI0_USART1, USART1_R, "usart1"), 140 RESET_CELL(RST_SCMI0_STGEN, STGEN_R, "stgen"), 141 RESET_CELL(RST_SCMI0_GPIOZ, GPIOZ_R, "gpioz"), 142 RESET_CELL(RST_SCMI0_CRYP1, CRYP1_R, "cryp1"), 143 RESET_CELL(RST_SCMI0_HASH1, HASH1_R, "hash1"), 144 RESET_CELL(RST_SCMI0_RNG1, RNG1_R, "rng1"), 145 RESET_CELL(RST_SCMI0_MDMA, MDMA_R, "mdma"), 146 RESET_CELL(RST_SCMI0_MCU, MCU_R, "mcu"), 147 RESET_CELL(RST_SCMI0_MCU_HOLD_BOOT, MCU_HOLD_BOOT_R, "mcu_hold_boot"), 148 }; 149 150 #define VOLTD_CELL(_scmi_id, _dev_id, _priv_id, _name) \ 151 [_scmi_id] = { \ 152 .priv_id = (_priv_id), \ 153 .priv_dev = (_dev_id), \ 154 .name = (_name), \ 155 } 156 157 #define PWR_REG11_NAME_ID "0" 158 #define PWR_REG18_NAME_ID "1" 159 #define PWR_USB33_NAME_ID "2" 160 161 struct stm32_scmi_voltd scmi0_voltage_domain[] = { 162 VOLTD_CELL(VOLTD_SCMI0_REG11, VOLTD_PWR, PWR_REG11_NAME_ID, "reg11"), 163 VOLTD_CELL(VOLTD_SCMI0_REG18, VOLTD_PWR, PWR_REG18_NAME_ID, "reg18"), 164 VOLTD_CELL(VOLTD_SCMI0_USB33, VOLTD_PWR, PWR_USB33_NAME_ID, "usb33"), 165 }; 166 167 struct channel_resources { 168 struct scmi_msg_channel *channel; 169 struct stm32_scmi_clk *clock; 170 size_t clock_count; 171 struct stm32_scmi_rd *rd; 172 size_t rd_count; 173 struct stm32_scmi_voltd *voltd; 174 size_t voltd_count; 175 }; 176 177 static const struct channel_resources scmi_channel[] = { 178 [0] = { 179 .channel = &(struct scmi_msg_channel){ 180 .shm_addr = { .pa = SMT_BUFFER0_BASE }, 181 .shm_size = SMT_BUF_SLOT_SIZE, 182 }, 183 .clock = stm32_scmi0_clock, 184 .clock_count = ARRAY_SIZE(stm32_scmi0_clock), 185 .rd = stm32_scmi0_reset_domain, 186 .rd_count = ARRAY_SIZE(stm32_scmi0_reset_domain), 187 .voltd = scmi0_voltage_domain, 188 .voltd_count = ARRAY_SIZE(scmi0_voltage_domain), 189 }, 190 [1] = { 191 .channel = &(struct scmi_msg_channel){ 192 .shm_addr = { .pa = SMT_BUFFER1_BASE }, 193 .shm_size = SMT_BUF_SLOT_SIZE, 194 }, 195 .clock = stm32_scmi1_clock, 196 .clock_count = ARRAY_SIZE(stm32_scmi1_clock), 197 }, 198 }; 199 200 static const struct channel_resources *find_resource(unsigned int channel_id) 201 { 202 assert(channel_id < ARRAY_SIZE(scmi_channel)); 203 204 return scmi_channel + channel_id; 205 } 206 207 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int channel_id) 208 { 209 const size_t max_id = ARRAY_SIZE(scmi_channel); 210 unsigned int confined_id = confine_array_index(channel_id, max_id); 211 212 if (channel_id >= max_id) 213 return NULL; 214 215 return find_resource(confined_id)->channel; 216 } 217 218 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 219 { 220 unsigned int n = 0; 221 unsigned int count = 0; 222 const size_t channel_count = ARRAY_SIZE(scmi_channel); 223 224 for (n = 0; n < channel_count; n++) 225 if (scmi_channel[n].clock_count) 226 break; 227 if (n < channel_count) 228 count++; 229 230 for (n = 0; n < channel_count; n++) 231 if (scmi_channel[n].rd_count) 232 break; 233 if (n < channel_count) 234 count++; 235 236 for (n = 0; n < channel_count; n++) 237 if (scmi_channel[n].voltd_count) 238 break; 239 if (n < channel_count) 240 count++; 241 242 return count; 243 } 244 245 static const char vendor[] = "ST"; 246 static const char sub_vendor[] = ""; 247 248 const char *plat_scmi_vendor_name(void) 249 { 250 return vendor; 251 } 252 253 const char *plat_scmi_sub_vendor_name(void) 254 { 255 return sub_vendor; 256 } 257 258 /* Currently supporting Clocks and Reset Domains */ 259 static const uint8_t plat_protocol_list[] = { 260 SCMI_PROTOCOL_ID_CLOCK, 261 SCMI_PROTOCOL_ID_RESET_DOMAIN, 262 SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, 263 0 /* Null termination */ 264 }; 265 266 size_t plat_scmi_protocol_count(void) 267 { 268 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 269 270 assert(count == plat_scmi_protocol_count_paranoid()); 271 272 return count; 273 } 274 275 const uint8_t *plat_scmi_protocol_list(unsigned int channel_id __unused) 276 { 277 assert(plat_scmi_protocol_count_paranoid() == 278 (ARRAY_SIZE(plat_protocol_list) - 1)); 279 280 return plat_protocol_list; 281 } 282 283 /* 284 * Platform SCMI clocks 285 */ 286 static struct stm32_scmi_clk *find_clock(unsigned int channel_id, 287 unsigned int scmi_id) 288 { 289 const struct channel_resources *resource = find_resource(channel_id); 290 size_t n = 0; 291 292 if (resource) { 293 for (n = 0; n < resource->clock_count; n++) 294 if (n == scmi_id) 295 return &resource->clock[n]; 296 } 297 298 return NULL; 299 } 300 301 size_t plat_scmi_clock_count(unsigned int channel_id) 302 { 303 const struct channel_resources *resource = find_resource(channel_id); 304 305 if (!resource) 306 return 0; 307 308 return resource->clock_count; 309 } 310 311 const char *plat_scmi_clock_get_name(unsigned int channel_id, 312 unsigned int scmi_id) 313 { 314 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 315 316 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 317 return NULL; 318 319 return clock->name; 320 } 321 322 int32_t plat_scmi_clock_rates_array(unsigned int channel_id, 323 unsigned int scmi_id, size_t start_index, 324 unsigned long *array, size_t *nb_elts) 325 { 326 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 327 328 if (!clock) 329 return SCMI_NOT_FOUND; 330 331 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 332 return SCMI_DENIED; 333 334 /* Exposed clocks are currently fixed rate clocks */ 335 if (start_index) 336 return SCMI_INVALID_PARAMETERS; 337 338 if (!array) 339 *nb_elts = 1; 340 else if (*nb_elts == 1) 341 *array = clk_get_rate(clock->clk); 342 else 343 return SCMI_GENERIC_ERROR; 344 345 return SCMI_SUCCESS; 346 } 347 348 unsigned long plat_scmi_clock_get_rate(unsigned int channel_id, 349 unsigned int scmi_id) 350 { 351 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 352 353 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 354 return 0; 355 356 return clk_get_rate(clock->clk); 357 } 358 359 int32_t plat_scmi_clock_get_state(unsigned int channel_id, unsigned int scmi_id) 360 { 361 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 362 363 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 364 return 0; 365 366 return (int32_t)clock->enabled; 367 } 368 369 int32_t plat_scmi_clock_set_state(unsigned int channel_id, unsigned int scmi_id, 370 bool enable_not_disable) 371 { 372 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 373 374 if (!clock) 375 return SCMI_NOT_FOUND; 376 377 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 378 return SCMI_DENIED; 379 380 if (enable_not_disable) { 381 if (!clock->enabled) { 382 DMSG("SCMI clock %u enable", scmi_id); 383 clk_enable(clock->clk); 384 clock->enabled = true; 385 } 386 } else { 387 if (clock->enabled) { 388 DMSG("SCMI clock %u disable", scmi_id); 389 clk_disable(clock->clk); 390 clock->enabled = false; 391 } 392 } 393 394 return SCMI_SUCCESS; 395 } 396 397 /* 398 * Platform SCMI reset domains 399 */ 400 static struct stm32_scmi_rd *find_rd(unsigned int channel_id, 401 unsigned int scmi_id) 402 { 403 const struct channel_resources *resource = find_resource(channel_id); 404 size_t n = 0; 405 406 if (resource) { 407 for (n = 0; n < resource->rd_count; n++) 408 if (n == scmi_id) 409 return &resource->rd[n]; 410 } 411 412 return NULL; 413 } 414 415 const char *plat_scmi_rd_get_name(unsigned int channel_id, unsigned int scmi_id) 416 { 417 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 418 419 if (!rd) 420 return NULL; 421 422 return rd->name; 423 } 424 425 size_t plat_scmi_rd_count(unsigned int channel_id) 426 { 427 const struct channel_resources *resource = find_resource(channel_id); 428 429 if (!resource) 430 return 0; 431 432 return resource->rd_count; 433 } 434 435 int32_t plat_scmi_rd_autonomous(unsigned int channel_id, unsigned int scmi_id, 436 uint32_t state) 437 { 438 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 439 440 if (!rd) 441 return SCMI_NOT_FOUND; 442 443 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 444 return SCMI_DENIED; 445 assert(rd->rstctrl); 446 447 if (rd->reset_id == MCU_HOLD_BOOT_R) 448 return SCMI_NOT_SUPPORTED; 449 450 /* Supports only reset with context loss */ 451 if (state) 452 return SCMI_NOT_SUPPORTED; 453 454 DMSG("SCMI reset %u cycle", scmi_id); 455 456 if (rstctrl_assert_to(rd->rstctrl, TIMEOUT_US_1MS)) 457 return SCMI_HARDWARE_ERROR; 458 459 if (rstctrl_deassert_to(rd->rstctrl, TIMEOUT_US_1MS)) 460 return SCMI_HARDWARE_ERROR; 461 462 return SCMI_SUCCESS; 463 } 464 465 int32_t plat_scmi_rd_set_state(unsigned int channel_id, unsigned int scmi_id, 466 bool assert_not_deassert) 467 { 468 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 469 TEE_Result res = TEE_ERROR_GENERIC; 470 471 if (!rd) 472 return SCMI_NOT_FOUND; 473 474 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 475 return SCMI_DENIED; 476 assert(rd->rstctrl); 477 478 if (assert_not_deassert) { 479 DMSG("SCMI reset %u set", scmi_id); 480 res = rstctrl_assert(rd->rstctrl); 481 } else { 482 DMSG("SCMI reset %u release", scmi_id); 483 res = rstctrl_deassert(rd->rstctrl); 484 } 485 486 if (res) 487 return SCMI_HARDWARE_ERROR; 488 489 return SCMI_SUCCESS; 490 } 491 492 /* 493 * Platform SCMI voltage domains 494 */ 495 static struct stm32_scmi_voltd *find_voltd(unsigned int channel_id, 496 unsigned int scmi_id) 497 { 498 const struct channel_resources *resource = find_resource(channel_id); 499 size_t n = 0; 500 501 if (resource) { 502 for (n = 0; n < resource->voltd_count; n++) 503 if (n == scmi_id) 504 return &resource->voltd[n]; 505 } 506 507 return NULL; 508 } 509 510 size_t plat_scmi_voltd_count(unsigned int channel_id) 511 { 512 const struct channel_resources *resource = find_resource(channel_id); 513 514 if (!resource) 515 return 0; 516 517 return resource->voltd_count; 518 } 519 520 const char *plat_scmi_voltd_get_name(unsigned int channel_id, 521 unsigned int scmi_id) 522 { 523 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 524 525 /* Currently non-secure is allowed to access all PWR regulators */ 526 if (!voltd) 527 return NULL; 528 529 return voltd->name; 530 } 531 532 static enum pwr_regulator pwr_scmi_to_regu_id(struct stm32_scmi_voltd *voltd) 533 { 534 if (!strcmp(voltd->priv_id, PWR_REG11_NAME_ID)) 535 return PWR_REG11; 536 if (!strcmp(voltd->priv_id, PWR_REG18_NAME_ID)) 537 return PWR_REG18; 538 if (!strcmp(voltd->priv_id, PWR_USB33_NAME_ID)) 539 return PWR_USB33; 540 541 panic(); 542 } 543 544 static long pwr_get_level(struct stm32_scmi_voltd *voltd) 545 { 546 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 547 548 return (long)stm32mp1_pwr_regulator_mv(regu_id) * 1000; 549 } 550 551 static int32_t pwr_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 552 { 553 if (level_uv != pwr_get_level(voltd)) 554 return SCMI_INVALID_PARAMETERS; 555 556 return SCMI_SUCCESS; 557 } 558 559 static int32_t pwr_describe_levels(struct stm32_scmi_voltd *voltd, 560 size_t start_index, long *microvolt, 561 size_t *nb_elts) 562 { 563 if (start_index) 564 return SCMI_INVALID_PARAMETERS; 565 566 if (!microvolt) { 567 *nb_elts = 1; 568 return SCMI_SUCCESS; 569 } 570 571 if (*nb_elts < 1) 572 return SCMI_GENERIC_ERROR; 573 574 *nb_elts = 1; 575 *microvolt = pwr_get_level(voltd); 576 577 return SCMI_SUCCESS; 578 } 579 580 static uint32_t pwr_get_state(struct stm32_scmi_voltd *voltd) 581 { 582 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 583 584 if (stm32mp1_pwr_regulator_is_enabled(regu_id)) 585 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 586 587 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 588 } 589 590 static void pwr_set_state(struct stm32_scmi_voltd *voltd, bool enable) 591 { 592 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 593 594 DMSG("%sable PWR %s (was %s)", enable ? "En" : "Dis", voltd->name, 595 stm32mp1_pwr_regulator_is_enabled(regu_id) ? "on" : "off"); 596 597 stm32mp1_pwr_regulator_set_state(regu_id, enable); 598 } 599 600 static int32_t pmic_describe_levels(struct stm32_scmi_voltd *voltd, 601 size_t start_index, long *microvolt, 602 size_t *nb_elts) 603 { 604 const uint16_t *levels = NULL; 605 size_t full_count = 0; 606 size_t out_count = 0; 607 size_t i = 0; 608 609 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 610 return SCMI_DENIED; 611 612 stpmic1_regulator_levels_mv(voltd->priv_id, &levels, &full_count); 613 614 if (!microvolt) { 615 *nb_elts = full_count - start_index; 616 return SCMI_SUCCESS; 617 } 618 619 if (SUB_OVERFLOW(full_count, start_index, &out_count)) 620 return SCMI_GENERIC_ERROR; 621 622 out_count = MIN(out_count, *nb_elts); 623 624 FMSG("%zu levels: start %zu requested %zu output %zu", 625 full_count, start_index, *nb_elts, out_count); 626 627 for (i = 0; i < out_count; i++) 628 microvolt[i] = levels[start_index + i] * 1000; 629 630 *nb_elts = out_count; 631 632 return SCMI_SUCCESS; 633 } 634 635 static long pmic_get_level(struct stm32_scmi_voltd *voltd) 636 { 637 unsigned long level_mv = 0; 638 639 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 640 return 0; 641 642 stm32mp_get_pmic(); 643 level_mv = stpmic1_regulator_voltage_get(voltd->priv_id); 644 stm32mp_put_pmic(); 645 646 return (long)level_mv * 1000; 647 } 648 649 static int32_t pmic_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 650 { 651 int rc = 0; 652 unsigned int level_mv = 0; 653 654 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 655 return SCMI_DENIED; 656 657 if (level_uv < 0 || level_uv > (UINT16_MAX * 1000)) 658 return SCMI_INVALID_PARAMETERS; 659 660 level_mv = (unsigned int)level_uv / 1000; 661 662 DMSG("Set STPMIC1 regulator %s level to %dmV", voltd->name, level_mv); 663 664 stm32mp_get_pmic(); 665 rc = stpmic1_regulator_voltage_set(voltd->priv_id, level_mv); 666 stm32mp_put_pmic(); 667 668 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 669 } 670 671 static uint32_t pmic_get_state(struct stm32_scmi_voltd *voltd) 672 { 673 bool enabled = false; 674 675 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 676 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 677 678 stm32mp_get_pmic(); 679 enabled = stpmic1_is_regulator_enabled(voltd->priv_id); 680 stm32mp_put_pmic(); 681 682 if (enabled) 683 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 684 685 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 686 } 687 688 static int32_t pmic_set_state(struct stm32_scmi_voltd *voltd, bool enable) 689 { 690 int rc = 0; 691 692 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 693 return SCMI_DENIED; 694 695 stm32mp_get_pmic(); 696 697 DMSG("%sable STPMIC1 %s (was %s)", enable ? "En" : "Dis", voltd->name, 698 stpmic1_is_regulator_enabled(voltd->priv_id) ? "on" : "off"); 699 700 if (enable) 701 rc = stpmic1_regulator_enable(voltd->priv_id); 702 else 703 rc = stpmic1_regulator_disable(voltd->priv_id); 704 705 stm32mp_put_pmic(); 706 707 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 708 } 709 710 int32_t plat_scmi_voltd_levels_array(unsigned int channel_id, 711 unsigned int scmi_id, size_t start_index, 712 long *levels, size_t *nb_elts) 713 714 { 715 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 716 717 if (!voltd) 718 return SCMI_NOT_FOUND; 719 720 switch (voltd->priv_dev) { 721 case VOLTD_PWR: 722 return pwr_describe_levels(voltd, start_index, levels, nb_elts); 723 case VOLTD_PMIC: 724 return pmic_describe_levels(voltd, start_index, levels, 725 nb_elts); 726 default: 727 return SCMI_GENERIC_ERROR; 728 } 729 } 730 731 long plat_scmi_voltd_get_level(unsigned int channel_id, unsigned int scmi_id) 732 { 733 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 734 735 if (!voltd) 736 return 0; 737 738 switch (voltd->priv_dev) { 739 case VOLTD_PWR: 740 return pwr_get_level(voltd); 741 case VOLTD_PMIC: 742 return pmic_get_level(voltd); 743 default: 744 panic(); 745 } 746 } 747 748 int32_t plat_scmi_voltd_set_level(unsigned int channel_id, unsigned int scmi_id, 749 long level) 750 { 751 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 752 753 if (!voltd) 754 return SCMI_NOT_FOUND; 755 756 switch (voltd->priv_dev) { 757 case VOLTD_PWR: 758 return pwr_set_level(voltd, level); 759 case VOLTD_PMIC: 760 return pmic_set_level(voltd, level); 761 default: 762 return SCMI_GENERIC_ERROR; 763 } 764 } 765 766 int32_t plat_scmi_voltd_get_config(unsigned int channel_id, 767 unsigned int scmi_id, uint32_t *config) 768 { 769 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 770 771 if (!voltd) 772 return SCMI_NOT_FOUND; 773 774 switch (voltd->priv_dev) { 775 case VOLTD_PWR: 776 *config = pwr_get_state(voltd); 777 break; 778 case VOLTD_PMIC: 779 *config = pmic_get_state(voltd); 780 break; 781 default: 782 return SCMI_GENERIC_ERROR; 783 } 784 785 return SCMI_SUCCESS; 786 } 787 788 int32_t plat_scmi_voltd_set_config(unsigned int channel_id, 789 unsigned int scmi_id, uint32_t config) 790 { 791 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 792 int32_t rc = SCMI_SUCCESS; 793 794 if (!voltd) 795 return SCMI_NOT_FOUND; 796 797 switch (voltd->priv_dev) { 798 case VOLTD_PWR: 799 pwr_set_state(voltd, config); 800 break; 801 case VOLTD_PMIC: 802 rc = pmic_set_state(voltd, config); 803 break; 804 default: 805 return SCMI_GENERIC_ERROR; 806 } 807 808 return rc; 809 } 810 811 /* 812 * Initialize platform SCMI resources 813 */ 814 static TEE_Result stm32mp1_init_scmi_server(void) 815 { 816 size_t i = 0; 817 size_t j = 0; 818 819 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 820 const struct channel_resources *res = scmi_channel + i; 821 struct scmi_msg_channel *chan = res->channel; 822 823 /* Enforce non-secure shm mapped as device memory */ 824 chan->shm_addr.va = (vaddr_t)phys_to_virt(chan->shm_addr.pa, 825 MEM_AREA_IO_NSEC, 1); 826 assert(chan->shm_addr.va); 827 828 scmi_smt_init_agent_channel(chan); 829 830 for (j = 0; j < res->clock_count; j++) { 831 struct stm32_scmi_clk *clk = &res->clock[j]; 832 833 if (!clk->name || 834 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 835 panic("SCMI clock name invalid"); 836 837 clk->clk = stm32mp_rcc_clock_id_to_clk(clk->clock_id); 838 assert(clk->clk); 839 840 /* Sync SCMI clocks with their targeted initial state */ 841 if (clk->enabled && 842 stm32mp_nsec_can_access_clock(clk->clock_id)) 843 clk_enable(clk->clk); 844 } 845 846 for (j = 0; j < res->rd_count; j++) { 847 struct stm32_scmi_rd *rd = &res->rd[j]; 848 struct rstctrl *rstctrl = NULL; 849 850 if (!rd->name || 851 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 852 panic("SCMI reset domain name invalid"); 853 854 if (stm32mp_nsec_can_access_clock(rd->reset_id)) 855 continue; 856 857 rstctrl = stm32mp_rcc_reset_id_to_rstctrl(rd->reset_id); 858 assert(rstctrl); 859 if (rstctrl_get_exclusive(rstctrl)) 860 panic(); 861 rd->rstctrl = rstctrl; 862 } 863 864 for (j = 0; j < res->voltd_count; j++) { 865 struct stm32_scmi_voltd *voltd = &res->voltd[j]; 866 867 if (!voltd->name || 868 strlen(voltd->name) >= SCMI_VOLTD_NAME_SIZE) 869 panic("SCMI voltage domain name invalid"); 870 } 871 } 872 873 return TEE_SUCCESS; 874 } 875 876 driver_init_late(stm32mp1_init_scmi_server); 877