1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019-2022, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <confine_array_index.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/rstctrl.h> 11 #include <drivers/scmi-msg.h> 12 #include <drivers/scmi.h> 13 #include <drivers/stm32mp1_pmic.h> 14 #include <drivers/stm32mp1_pwr.h> 15 #include <drivers/stpmic1.h> 16 #include <drivers/stpmic1_regulator.h> 17 #include <drivers/stm32mp_dt_bindings.h> 18 #include <initcall.h> 19 #include <mm/core_memprot.h> 20 #include <mm/core_mmu.h> 21 #include <platform_config.h> 22 #include <stdint.h> 23 #include <speculation_barrier.h> 24 #include <stm32_util.h> 25 #include <string.h> 26 #include <tee_api_defines.h> 27 #include <util.h> 28 29 #define TIMEOUT_US_1MS 1000 30 31 #define SCMI_CLOCK_NAME_SIZE 16 32 #define SCMI_RD_NAME_SIZE 16 33 #define SCMI_VOLTD_NAME_SIZE 16 34 35 /* 36 * struct stm32_scmi_clk - Data for the exposed clock 37 * @clock_id: Clock identifier in RCC clock driver 38 * @name: Clock string ID exposed to channel 39 * @enabled: State of the SCMI clock 40 */ 41 struct stm32_scmi_clk { 42 unsigned long clock_id; 43 struct clk *clk; 44 const char *name; 45 bool enabled; 46 }; 47 48 /* 49 * struct stm32_scmi_rd - Data for the exposed reset controller 50 * @reset_id: Reset identifier in RCC reset driver 51 * @name: Reset string ID exposed to channel 52 * @rstctrl: Reset controller device 53 */ 54 struct stm32_scmi_rd { 55 unsigned long reset_id; 56 const char *name; 57 struct rstctrl *rstctrl; 58 }; 59 60 enum voltd_device { 61 VOLTD_PWR, 62 VOLTD_PMIC, 63 }; 64 65 /* 66 * struct stm32_scmi_voltd - Data for the exposed voltage domains 67 * @name: Power regulator string ID exposed to channel 68 * @priv_id: Internal string ID for the regulator 69 * @priv_dev: Internal ID for the device implementing the regulator 70 */ 71 struct stm32_scmi_voltd { 72 const char *name; 73 const char *priv_id; 74 enum voltd_device priv_dev; 75 76 }; 77 78 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 79 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 80 81 #if (SMT_BUFFER_BASE + SMT_BUF_SLOT_SIZE > \ 82 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 83 #error "SCMI shared memory mismatch" 84 #endif 85 86 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 87 [(_scmi_id)] = { \ 88 .clock_id = (_id), \ 89 .name = (_name), \ 90 .enabled = (_init_enabled), \ 91 } 92 93 #define RESET_CELL(_scmi_id, _id, _name) \ 94 [(_scmi_id)] = { \ 95 .reset_id = (_id), \ 96 .name = (_name), \ 97 } 98 99 #define VOLTD_CELL(_scmi_id, _dev_id, _priv_id, _name) \ 100 [(_scmi_id)] = { \ 101 .priv_id = (_priv_id), \ 102 .priv_dev = (_dev_id), \ 103 .name = (_name), \ 104 } 105 106 #ifdef CFG_STM32MP13 107 static struct stm32_scmi_clk stm32_scmi_clock[] = { 108 CLOCK_CELL(CK_SCMI_HSE, CK_HSE, "ck_hse", true), 109 CLOCK_CELL(CK_SCMI_HSI, CK_HSI, "ck_hsi", true), 110 CLOCK_CELL(CK_SCMI_CSI, CK_CSI, "ck_csi", true), 111 CLOCK_CELL(CK_SCMI_LSE, CK_LSE, "ck_lse", true), 112 CLOCK_CELL(CK_SCMI_LSI, CK_LSI, "ck_lsi", true), 113 CLOCK_CELL(CK_SCMI_HSE_DIV2, CK_HSE_DIV2, "clk-hse-div2", true), 114 CLOCK_CELL(CK_SCMI_PLL2_Q, PLL2_Q, "pll2_q", true), 115 CLOCK_CELL(CK_SCMI_PLL2_R, PLL2_R, "pll2_r", true), 116 CLOCK_CELL(CK_SCMI_PLL3_P, PLL3_P, "pll3_p", true), 117 CLOCK_CELL(CK_SCMI_PLL3_Q, PLL3_Q, "pll3_q", true), 118 CLOCK_CELL(CK_SCMI_PLL3_R, PLL3_R, "pll3_r", true), 119 CLOCK_CELL(CK_SCMI_PLL4_P, PLL4_P, "pll4_p", true), 120 CLOCK_CELL(CK_SCMI_PLL4_Q, PLL4_Q, "pll4_q", true), 121 CLOCK_CELL(CK_SCMI_PLL4_R, PLL4_R, "pll4_r", true), 122 CLOCK_CELL(CK_SCMI_MPU, CK_MPU, "ck_mpu", true), 123 CLOCK_CELL(CK_SCMI_AXI, CK_AXI, "ck_axi", true), 124 CLOCK_CELL(CK_SCMI_MLAHB, CK_MLAHB, "ck_mlahb", true), 125 CLOCK_CELL(CK_SCMI_CKPER, CK_PER, "ck_per", true), 126 CLOCK_CELL(CK_SCMI_PCLK1, PCLK1, "pclk1", true), 127 CLOCK_CELL(CK_SCMI_PCLK2, PCLK2, "pclk2", true), 128 CLOCK_CELL(CK_SCMI_PCLK3, PCLK3, "pclk3", true), 129 CLOCK_CELL(CK_SCMI_PCLK4, PCLK4, "pclk4", true), 130 CLOCK_CELL(CK_SCMI_PCLK5, PCLK5, "pclk5", true), 131 CLOCK_CELL(CK_SCMI_PCLK6, PCLK6, "pclk6", true), 132 CLOCK_CELL(CK_SCMI_CKTIMG1, CK_TIMG1, "timg1_ck", true), 133 CLOCK_CELL(CK_SCMI_CKTIMG2, CK_TIMG2, "timg2_ck", true), 134 CLOCK_CELL(CK_SCMI_CKTIMG3, CK_TIMG3, "timg3_ck", true), 135 CLOCK_CELL(CK_SCMI_RTC, RTC, "ck_rtc", true), 136 CLOCK_CELL(CK_SCMI_RTCAPB, RTCAPB, "rtcapb", true), 137 CLOCK_CELL(CK_SCMI_BSEC, BSEC, "bsec", true), 138 }; 139 #endif 140 141 #ifdef CFG_STM32MP15 142 static struct stm32_scmi_clk stm32_scmi_clock[] = { 143 CLOCK_CELL(CK_SCMI_HSE, CK_HSE, "ck_hse", true), 144 CLOCK_CELL(CK_SCMI_HSI, CK_HSI, "ck_hsi", true), 145 CLOCK_CELL(CK_SCMI_CSI, CK_CSI, "ck_csi", true), 146 CLOCK_CELL(CK_SCMI_LSE, CK_LSE, "ck_lse", true), 147 CLOCK_CELL(CK_SCMI_LSI, CK_LSI, "ck_lsi", true), 148 CLOCK_CELL(CK_SCMI_PLL2_Q, PLL2_Q, "pll2_q", true), 149 CLOCK_CELL(CK_SCMI_PLL2_R, PLL2_R, "pll2_r", true), 150 CLOCK_CELL(CK_SCMI_MPU, CK_MPU, "ck_mpu", true), 151 CLOCK_CELL(CK_SCMI_AXI, CK_AXI, "ck_axi", true), 152 CLOCK_CELL(CK_SCMI_BSEC, BSEC, "bsec", true), 153 CLOCK_CELL(CK_SCMI_CRYP1, CRYP1, "cryp1", false), 154 CLOCK_CELL(CK_SCMI_GPIOZ, GPIOZ, "gpioz", false), 155 CLOCK_CELL(CK_SCMI_HASH1, HASH1, "hash1", false), 156 CLOCK_CELL(CK_SCMI_I2C4, I2C4_K, "i2c4_k", false), 157 CLOCK_CELL(CK_SCMI_I2C6, I2C6_K, "i2c6_k", false), 158 CLOCK_CELL(CK_SCMI_IWDG1, IWDG1, "iwdg1", false), 159 CLOCK_CELL(CK_SCMI_RNG1, RNG1_K, "rng1_k", true), 160 CLOCK_CELL(CK_SCMI_RTC, RTC, "ck_rtc", true), 161 CLOCK_CELL(CK_SCMI_RTCAPB, RTCAPB, "rtcapb", true), 162 CLOCK_CELL(CK_SCMI_SPI6, SPI6_K, "spi6_k", false), 163 CLOCK_CELL(CK_SCMI_USART1, USART1_K, "usart1_k", false), 164 }; 165 #endif 166 167 #ifdef CFG_STM32MP13 168 static struct stm32_scmi_rd stm32_scmi_reset_domain[] = { 169 RESET_CELL(RST_SCMI_LTDC, LTDC_R, "ltdc"), 170 RESET_CELL(RST_SCMI_MDMA, MDMA_R, "mdma"), 171 }; 172 #endif 173 174 #ifdef CFG_STM32MP15 175 static struct stm32_scmi_rd stm32_scmi_reset_domain[] = { 176 RESET_CELL(RST_SCMI_SPI6, SPI6_R, "spi6"), 177 RESET_CELL(RST_SCMI_I2C4, I2C4_R, "i2c4"), 178 RESET_CELL(RST_SCMI_I2C6, I2C6_R, "i2c6"), 179 RESET_CELL(RST_SCMI_USART1, USART1_R, "usart1"), 180 RESET_CELL(RST_SCMI_STGEN, STGEN_R, "stgen"), 181 RESET_CELL(RST_SCMI_GPIOZ, GPIOZ_R, "gpioz"), 182 RESET_CELL(RST_SCMI_CRYP1, CRYP1_R, "cryp1"), 183 RESET_CELL(RST_SCMI_HASH1, HASH1_R, "hash1"), 184 RESET_CELL(RST_SCMI_RNG1, RNG1_R, "rng1"), 185 RESET_CELL(RST_SCMI_MDMA, MDMA_R, "mdma"), 186 RESET_CELL(RST_SCMI_MCU, MCU_R, "mcu"), 187 RESET_CELL(RST_SCMI_MCU_HOLD_BOOT, MCU_HOLD_BOOT_R, "mcu_hold_boot"), 188 }; 189 #endif 190 191 #define PWR_REG11_NAME_ID "0" 192 #define PWR_REG18_NAME_ID "1" 193 #define PWR_USB33_NAME_ID "2" 194 #define PWR_SDMMC1_IO_NAME_ID "3" 195 #define PWR_SDMMC2_IO_NAME_ID "4" 196 #define PWR_VREFBUF_NAME_ID "5" 197 198 #ifdef CFG_STM32MP13 199 struct stm32_scmi_voltd scmi_voltage_domain[] = { 200 VOLTD_CELL(VOLTD_SCMI_REG11, VOLTD_PWR, PWR_REG11_NAME_ID, "reg11"), 201 VOLTD_CELL(VOLTD_SCMI_REG18, VOLTD_PWR, PWR_REG18_NAME_ID, "reg18"), 202 VOLTD_CELL(VOLTD_SCMI_USB33, VOLTD_PWR, PWR_USB33_NAME_ID, "usb33"), 203 VOLTD_CELL(VOLTD_SCMI_SDMMC1_IO, VOLTD_PWR, PWR_SDMMC1_IO_NAME_ID, 204 "sdmmc1"), 205 VOLTD_CELL(VOLTD_SCMI_SDMMC2_IO, VOLTD_PWR, PWR_SDMMC2_IO_NAME_ID, 206 "sdmmc2"), 207 VOLTD_CELL(VOLTD_SCMI_VREFBUF, VOLTD_PWR, PWR_VREFBUF_NAME_ID, 208 "vrefbuf"), 209 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK1, VOLTD_PMIC, "buck1", "buck1"), 210 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK2, VOLTD_PMIC, "buck2", "buck2"), 211 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK3, VOLTD_PMIC, "buck3", "buck3"), 212 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK4, VOLTD_PMIC, "buck4", "buck4"), 213 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO1, VOLTD_PMIC, "ldo1", "ldo1"), 214 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO2, VOLTD_PMIC, "ldo2", "ldo2"), 215 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO3, VOLTD_PMIC, "ldo3", "ldo3"), 216 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO4, VOLTD_PMIC, "ldo4", "ldo4"), 217 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO5, VOLTD_PMIC, "ldo5", "ldo5"), 218 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO6, VOLTD_PMIC, "ldo6", "ldo6"), 219 VOLTD_CELL(VOLTD_SCMI_STPMIC1_VREFDDR, VOLTD_PMIC, "vref_ddr", 220 "vref_ddr"), 221 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BOOST, VOLTD_PMIC, "boost", "bst_out"), 222 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW1, VOLTD_PMIC, "pwr_sw1", 223 "pwr_sw1"), 224 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW2, VOLTD_PMIC, "pwr_sw2", 225 "pwr_sw2"), 226 }; 227 #endif 228 229 #ifdef CFG_STM32MP15 230 struct stm32_scmi_voltd scmi_voltage_domain[] = { 231 VOLTD_CELL(VOLTD_SCMI_REG11, VOLTD_PWR, PWR_REG11_NAME_ID, "reg11"), 232 VOLTD_CELL(VOLTD_SCMI_REG18, VOLTD_PWR, PWR_REG18_NAME_ID, "reg18"), 233 VOLTD_CELL(VOLTD_SCMI_USB33, VOLTD_PWR, PWR_USB33_NAME_ID, "usb33"), 234 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK1, VOLTD_PMIC, "buck1", "vddcore"), 235 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK2, VOLTD_PMIC, "buck2", "vdd_ddr"), 236 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK3, VOLTD_PMIC, "buck3", "vdd"), 237 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK4, VOLTD_PMIC, "buck4", "v3v3"), 238 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO1, VOLTD_PMIC, "ldo1", "v1v8_audio"), 239 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO2, VOLTD_PMIC, "ldo2", "v3v3_hdmi"), 240 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO3, VOLTD_PMIC, "ldo3", "vtt_ddr"), 241 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO4, VOLTD_PMIC, "ldo4", "vdd_usb"), 242 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO5, VOLTD_PMIC, "ldo5", "vdda"), 243 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO6, VOLTD_PMIC, "ldo6", "v1v2_hdmi"), 244 VOLTD_CELL(VOLTD_SCMI_STPMIC1_VREFDDR, VOLTD_PMIC, "vref_ddr", 245 "vref_ddr"), 246 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BOOST, VOLTD_PMIC, "boost", "bst_out"), 247 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW1, VOLTD_PMIC, "pwr_sw1", 248 "vbus_otg"), 249 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW2, VOLTD_PMIC, "pwr_sw2", 250 "vbus_sw"), 251 }; 252 #endif 253 254 struct channel_resources { 255 struct scmi_msg_channel *channel; 256 struct stm32_scmi_clk *clock; 257 size_t clock_count; 258 struct stm32_scmi_rd *rd; 259 size_t rd_count; 260 struct stm32_scmi_voltd *voltd; 261 size_t voltd_count; 262 }; 263 264 static const struct channel_resources scmi_channel[] = { 265 [0] = { 266 .channel = &(struct scmi_msg_channel){ 267 .shm_addr = { .pa = SMT_BUFFER_BASE }, 268 .shm_size = SMT_BUF_SLOT_SIZE, 269 }, 270 .clock = stm32_scmi_clock, 271 .clock_count = ARRAY_SIZE(stm32_scmi_clock), 272 .rd = stm32_scmi_reset_domain, 273 .rd_count = ARRAY_SIZE(stm32_scmi_reset_domain), 274 .voltd = scmi_voltage_domain, 275 .voltd_count = ARRAY_SIZE(scmi_voltage_domain), 276 }, 277 }; 278 279 static const struct channel_resources *find_resource(unsigned int channel_id) 280 { 281 assert(channel_id < ARRAY_SIZE(scmi_channel)); 282 283 return scmi_channel + channel_id; 284 } 285 286 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int channel_id) 287 { 288 const size_t max_id = ARRAY_SIZE(scmi_channel); 289 unsigned int confined_id = confine_array_index(channel_id, max_id); 290 291 if (channel_id >= max_id) 292 return NULL; 293 294 return find_resource(confined_id)->channel; 295 } 296 297 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 298 { 299 unsigned int n = 0; 300 unsigned int count = 0; 301 const size_t channel_count = ARRAY_SIZE(scmi_channel); 302 303 for (n = 0; n < channel_count; n++) 304 if (scmi_channel[n].clock_count) 305 break; 306 if (n < channel_count) 307 count++; 308 309 for (n = 0; n < channel_count; n++) 310 if (scmi_channel[n].rd_count) 311 break; 312 if (n < channel_count) 313 count++; 314 315 for (n = 0; n < channel_count; n++) 316 if (scmi_channel[n].voltd_count) 317 break; 318 if (n < channel_count) 319 count++; 320 321 return count; 322 } 323 324 static const char vendor[] = "ST"; 325 static const char sub_vendor[] = ""; 326 327 const char *plat_scmi_vendor_name(void) 328 { 329 return vendor; 330 } 331 332 const char *plat_scmi_sub_vendor_name(void) 333 { 334 return sub_vendor; 335 } 336 337 /* Currently supporting Clocks and Reset Domains */ 338 static const uint8_t plat_protocol_list[] = { 339 SCMI_PROTOCOL_ID_CLOCK, 340 SCMI_PROTOCOL_ID_RESET_DOMAIN, 341 SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, 342 0 /* Null termination */ 343 }; 344 345 size_t plat_scmi_protocol_count(void) 346 { 347 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 348 349 assert(count == plat_scmi_protocol_count_paranoid()); 350 351 return count; 352 } 353 354 const uint8_t *plat_scmi_protocol_list(unsigned int channel_id __unused) 355 { 356 assert(plat_scmi_protocol_count_paranoid() == 357 (ARRAY_SIZE(plat_protocol_list) - 1)); 358 359 return plat_protocol_list; 360 } 361 362 /* 363 * Platform SCMI clocks 364 */ 365 static struct stm32_scmi_clk *find_clock(unsigned int channel_id, 366 unsigned int scmi_id) 367 { 368 const struct channel_resources *resource = find_resource(channel_id); 369 size_t n = 0; 370 371 if (resource) { 372 for (n = 0; n < resource->clock_count; n++) 373 if (n == scmi_id) 374 return &resource->clock[n]; 375 } 376 377 return NULL; 378 } 379 380 size_t plat_scmi_clock_count(unsigned int channel_id) 381 { 382 const struct channel_resources *resource = find_resource(channel_id); 383 384 if (!resource) 385 return 0; 386 387 return resource->clock_count; 388 } 389 390 const char *plat_scmi_clock_get_name(unsigned int channel_id, 391 unsigned int scmi_id) 392 { 393 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 394 395 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 396 return NULL; 397 398 return clock->name; 399 } 400 401 int32_t plat_scmi_clock_rates_array(unsigned int channel_id, 402 unsigned int scmi_id, size_t start_index, 403 unsigned long *array, size_t *nb_elts) 404 { 405 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 406 407 if (!clock) 408 return SCMI_NOT_FOUND; 409 410 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 411 return SCMI_DENIED; 412 413 /* Exposed clocks are currently fixed rate clocks */ 414 if (start_index) 415 return SCMI_INVALID_PARAMETERS; 416 417 if (!array) 418 *nb_elts = 1; 419 else if (*nb_elts == 1) 420 *array = clk_get_rate(clock->clk); 421 else 422 return SCMI_GENERIC_ERROR; 423 424 return SCMI_SUCCESS; 425 } 426 427 unsigned long plat_scmi_clock_get_rate(unsigned int channel_id, 428 unsigned int scmi_id) 429 { 430 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 431 432 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 433 return 0; 434 435 return clk_get_rate(clock->clk); 436 } 437 438 int32_t plat_scmi_clock_get_state(unsigned int channel_id, unsigned int scmi_id) 439 { 440 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 441 442 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 443 return 0; 444 445 return (int32_t)clock->enabled; 446 } 447 448 int32_t plat_scmi_clock_set_state(unsigned int channel_id, unsigned int scmi_id, 449 bool enable_not_disable) 450 { 451 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 452 453 if (!clock) 454 return SCMI_NOT_FOUND; 455 456 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 457 return SCMI_DENIED; 458 459 if (enable_not_disable) { 460 if (!clock->enabled) { 461 DMSG("SCMI clock %u enable", scmi_id); 462 clk_enable(clock->clk); 463 clock->enabled = true; 464 } 465 } else { 466 if (clock->enabled) { 467 DMSG("SCMI clock %u disable", scmi_id); 468 clk_disable(clock->clk); 469 clock->enabled = false; 470 } 471 } 472 473 return SCMI_SUCCESS; 474 } 475 476 /* 477 * Platform SCMI reset domains 478 */ 479 static struct stm32_scmi_rd *find_rd(unsigned int channel_id, 480 unsigned int scmi_id) 481 { 482 const struct channel_resources *resource = find_resource(channel_id); 483 size_t n = 0; 484 485 if (resource) { 486 for (n = 0; n < resource->rd_count; n++) 487 if (n == scmi_id) 488 return &resource->rd[n]; 489 } 490 491 return NULL; 492 } 493 494 const char *plat_scmi_rd_get_name(unsigned int channel_id, unsigned int scmi_id) 495 { 496 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 497 498 if (!rd) 499 return NULL; 500 501 return rd->name; 502 } 503 504 size_t plat_scmi_rd_count(unsigned int channel_id) 505 { 506 const struct channel_resources *resource = find_resource(channel_id); 507 508 if (!resource) 509 return 0; 510 511 return resource->rd_count; 512 } 513 514 int32_t plat_scmi_rd_autonomous(unsigned int channel_id, unsigned int scmi_id, 515 uint32_t state) 516 { 517 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 518 519 if (!rd) 520 return SCMI_NOT_FOUND; 521 522 if (!rd->rstctrl || !stm32mp_nsec_can_access_reset(rd->reset_id)) 523 return SCMI_DENIED; 524 assert(rd->rstctrl); 525 526 #ifdef CFG_STM32MP15 527 if (rd->reset_id == MCU_HOLD_BOOT_R) 528 return SCMI_NOT_SUPPORTED; 529 #endif 530 531 /* Supports only reset with context loss */ 532 if (state) 533 return SCMI_NOT_SUPPORTED; 534 535 DMSG("SCMI reset %u cycle", scmi_id); 536 537 if (rstctrl_assert_to(rd->rstctrl, TIMEOUT_US_1MS)) 538 return SCMI_HARDWARE_ERROR; 539 540 if (rstctrl_deassert_to(rd->rstctrl, TIMEOUT_US_1MS)) 541 return SCMI_HARDWARE_ERROR; 542 543 return SCMI_SUCCESS; 544 } 545 546 int32_t plat_scmi_rd_set_state(unsigned int channel_id, unsigned int scmi_id, 547 bool assert_not_deassert) 548 { 549 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 550 TEE_Result res = TEE_ERROR_GENERIC; 551 552 if (!rd) 553 return SCMI_NOT_FOUND; 554 555 if (!rd->rstctrl || !stm32mp_nsec_can_access_reset(rd->reset_id)) 556 return SCMI_DENIED; 557 assert(rd->rstctrl); 558 559 if (assert_not_deassert) { 560 DMSG("SCMI reset %u set", scmi_id); 561 res = rstctrl_assert(rd->rstctrl); 562 } else { 563 DMSG("SCMI reset %u release", scmi_id); 564 res = rstctrl_deassert(rd->rstctrl); 565 } 566 567 if (res) 568 return SCMI_HARDWARE_ERROR; 569 570 return SCMI_SUCCESS; 571 } 572 573 /* 574 * Platform SCMI voltage domains 575 */ 576 static struct stm32_scmi_voltd *find_voltd(unsigned int channel_id, 577 unsigned int scmi_id) 578 { 579 const struct channel_resources *resource = find_resource(channel_id); 580 size_t n = 0; 581 582 if (resource) { 583 for (n = 0; n < resource->voltd_count; n++) 584 if (n == scmi_id) 585 return &resource->voltd[n]; 586 } 587 588 return NULL; 589 } 590 591 size_t plat_scmi_voltd_count(unsigned int channel_id) 592 { 593 const struct channel_resources *resource = find_resource(channel_id); 594 595 if (!resource) 596 return 0; 597 598 return resource->voltd_count; 599 } 600 601 const char *plat_scmi_voltd_get_name(unsigned int channel_id, 602 unsigned int scmi_id) 603 { 604 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 605 606 /* Currently non-secure is allowed to access all PWR regulators */ 607 if (!voltd) 608 return NULL; 609 610 return voltd->name; 611 } 612 613 static enum pwr_regulator pwr_scmi_to_regu_id(struct stm32_scmi_voltd *voltd) 614 { 615 if (!strcmp(voltd->priv_id, PWR_REG11_NAME_ID)) 616 return PWR_REG11; 617 if (!strcmp(voltd->priv_id, PWR_REG18_NAME_ID)) 618 return PWR_REG18; 619 if (!strcmp(voltd->priv_id, PWR_USB33_NAME_ID)) 620 return PWR_USB33; 621 622 panic(); 623 } 624 625 static long pwr_get_level(struct stm32_scmi_voltd *voltd) 626 { 627 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 628 629 return (long)stm32mp1_pwr_regulator_mv(regu_id) * 1000; 630 } 631 632 static int32_t pwr_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 633 { 634 if (level_uv != pwr_get_level(voltd)) 635 return SCMI_INVALID_PARAMETERS; 636 637 return SCMI_SUCCESS; 638 } 639 640 static int32_t pwr_describe_levels(struct stm32_scmi_voltd *voltd, 641 size_t start_index, long *microvolt, 642 size_t *nb_elts) 643 { 644 if (start_index) 645 return SCMI_INVALID_PARAMETERS; 646 647 if (!microvolt) { 648 *nb_elts = 1; 649 return SCMI_SUCCESS; 650 } 651 652 if (*nb_elts < 1) 653 return SCMI_GENERIC_ERROR; 654 655 *nb_elts = 1; 656 *microvolt = pwr_get_level(voltd); 657 658 return SCMI_SUCCESS; 659 } 660 661 static uint32_t pwr_get_state(struct stm32_scmi_voltd *voltd) 662 { 663 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 664 665 if (stm32mp1_pwr_regulator_is_enabled(regu_id)) 666 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 667 668 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 669 } 670 671 static void pwr_set_state(struct stm32_scmi_voltd *voltd, bool enable) 672 { 673 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 674 675 DMSG("%sable PWR %s (was %s)", enable ? "En" : "Dis", voltd->name, 676 stm32mp1_pwr_regulator_is_enabled(regu_id) ? "on" : "off"); 677 678 stm32mp1_pwr_regulator_set_state(regu_id, enable); 679 } 680 681 static int32_t pmic_describe_levels(struct stm32_scmi_voltd *voltd, 682 size_t start_index, long *microvolt, 683 size_t *nb_elts) 684 { 685 const uint16_t *levels = NULL; 686 size_t full_count = 0; 687 size_t out_count = 0; 688 size_t i = 0; 689 690 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 691 return SCMI_DENIED; 692 693 stpmic1_regulator_levels_mv(voltd->priv_id, &levels, &full_count); 694 695 if (!microvolt) { 696 *nb_elts = full_count - start_index; 697 return SCMI_SUCCESS; 698 } 699 700 if (SUB_OVERFLOW(full_count, start_index, &out_count)) 701 return SCMI_GENERIC_ERROR; 702 703 out_count = MIN(out_count, *nb_elts); 704 705 FMSG("%zu levels: start %zu requested %zu output %zu", 706 full_count, start_index, *nb_elts, out_count); 707 708 for (i = 0; i < out_count; i++) 709 microvolt[i] = levels[start_index + i] * 1000; 710 711 *nb_elts = out_count; 712 713 return SCMI_SUCCESS; 714 } 715 716 static long pmic_get_level(struct stm32_scmi_voltd *voltd) 717 { 718 unsigned long level_mv = 0; 719 720 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 721 return 0; 722 723 stm32mp_get_pmic(); 724 level_mv = stpmic1_regulator_voltage_get(voltd->priv_id); 725 stm32mp_put_pmic(); 726 727 return (long)level_mv * 1000; 728 } 729 730 static int32_t pmic_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 731 { 732 int rc = 0; 733 unsigned int level_mv = 0; 734 735 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 736 return SCMI_DENIED; 737 738 if (level_uv < 0 || level_uv > (UINT16_MAX * 1000)) 739 return SCMI_INVALID_PARAMETERS; 740 741 level_mv = (unsigned int)level_uv / 1000; 742 743 DMSG("Set STPMIC1 regulator %s level to %dmV", voltd->name, level_mv); 744 745 stm32mp_get_pmic(); 746 rc = stpmic1_regulator_voltage_set(voltd->priv_id, level_mv); 747 stm32mp_put_pmic(); 748 749 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 750 } 751 752 static uint32_t pmic_get_state(struct stm32_scmi_voltd *voltd) 753 { 754 bool enabled = false; 755 756 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 757 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 758 759 stm32mp_get_pmic(); 760 enabled = stpmic1_is_regulator_enabled(voltd->priv_id); 761 stm32mp_put_pmic(); 762 763 if (enabled) 764 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 765 766 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 767 } 768 769 static int32_t pmic_set_state(struct stm32_scmi_voltd *voltd, bool enable) 770 { 771 int rc = 0; 772 773 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 774 return SCMI_DENIED; 775 776 stm32mp_get_pmic(); 777 778 DMSG("%sable STPMIC1 %s (was %s)", enable ? "En" : "Dis", voltd->name, 779 stpmic1_is_regulator_enabled(voltd->priv_id) ? "on" : "off"); 780 781 if (enable) 782 rc = stpmic1_regulator_enable(voltd->priv_id); 783 else 784 rc = stpmic1_regulator_disable(voltd->priv_id); 785 786 stm32mp_put_pmic(); 787 788 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 789 } 790 791 int32_t plat_scmi_voltd_levels_array(unsigned int channel_id, 792 unsigned int scmi_id, size_t start_index, 793 long *levels, size_t *nb_elts) 794 795 { 796 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 797 798 if (!voltd) 799 return SCMI_NOT_FOUND; 800 801 switch (voltd->priv_dev) { 802 case VOLTD_PWR: 803 return pwr_describe_levels(voltd, start_index, levels, nb_elts); 804 case VOLTD_PMIC: 805 return pmic_describe_levels(voltd, start_index, levels, 806 nb_elts); 807 default: 808 return SCMI_GENERIC_ERROR; 809 } 810 } 811 812 int32_t plat_scmi_voltd_get_level(unsigned int channel_id, unsigned int scmi_id, 813 long *level) 814 { 815 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 816 long voltage = 0; 817 818 if (!voltd) 819 return SCMI_INVALID_PARAMETERS; 820 821 switch (voltd->priv_dev) { 822 case VOLTD_PWR: 823 *level = pwr_get_level(voltd); 824 return SCMI_SUCCESS; 825 case VOLTD_PMIC: 826 voltage = pmic_get_level(voltd); 827 if (voltage > 0) { 828 *level = voltage; 829 return SCMI_SUCCESS; 830 } else { 831 return SCMI_GENERIC_ERROR; 832 } 833 default: 834 panic(); 835 } 836 } 837 838 int32_t plat_scmi_voltd_set_level(unsigned int channel_id, unsigned int scmi_id, 839 long level) 840 { 841 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 842 843 if (!voltd) 844 return SCMI_NOT_FOUND; 845 846 switch (voltd->priv_dev) { 847 case VOLTD_PWR: 848 return pwr_set_level(voltd, level); 849 case VOLTD_PMIC: 850 return pmic_set_level(voltd, level); 851 default: 852 return SCMI_GENERIC_ERROR; 853 } 854 } 855 856 int32_t plat_scmi_voltd_get_config(unsigned int channel_id, 857 unsigned int scmi_id, uint32_t *config) 858 { 859 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 860 861 if (!voltd) 862 return SCMI_NOT_FOUND; 863 864 switch (voltd->priv_dev) { 865 case VOLTD_PWR: 866 *config = pwr_get_state(voltd); 867 break; 868 case VOLTD_PMIC: 869 *config = pmic_get_state(voltd); 870 break; 871 default: 872 return SCMI_GENERIC_ERROR; 873 } 874 875 return SCMI_SUCCESS; 876 } 877 878 int32_t plat_scmi_voltd_set_config(unsigned int channel_id, 879 unsigned int scmi_id, uint32_t config) 880 { 881 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 882 int32_t rc = SCMI_SUCCESS; 883 884 if (!voltd) 885 return SCMI_NOT_FOUND; 886 887 switch (voltd->priv_dev) { 888 case VOLTD_PWR: 889 pwr_set_state(voltd, config); 890 break; 891 case VOLTD_PMIC: 892 rc = pmic_set_state(voltd, config); 893 break; 894 default: 895 return SCMI_GENERIC_ERROR; 896 } 897 898 return rc; 899 } 900 901 /* 902 * Initialize platform SCMI resources 903 */ 904 static TEE_Result stm32mp1_init_scmi_server(void) 905 { 906 size_t i = 0; 907 size_t j = 0; 908 909 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 910 const struct channel_resources *res = scmi_channel + i; 911 struct scmi_msg_channel *chan = res->channel; 912 913 /* Enforce non-secure shm mapped as device memory */ 914 chan->shm_addr.va = (vaddr_t)phys_to_virt(chan->shm_addr.pa, 915 MEM_AREA_IO_NSEC, 1); 916 assert(chan->shm_addr.va); 917 918 scmi_smt_init_agent_channel(chan); 919 920 for (j = 0; j < res->clock_count; j++) { 921 struct stm32_scmi_clk *clk = &res->clock[j]; 922 923 if (!clk->name || 924 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 925 panic("SCMI clock name invalid"); 926 927 clk->clk = stm32mp_rcc_clock_id_to_clk(clk->clock_id); 928 assert(clk->clk); 929 930 /* Sync SCMI clocks with their targeted initial state */ 931 if (clk->enabled && 932 stm32mp_nsec_can_access_clock(clk->clock_id)) 933 clk_enable(clk->clk); 934 } 935 936 for (j = 0; j < res->rd_count; j++) { 937 struct stm32_scmi_rd *rd = &res->rd[j]; 938 struct rstctrl *rstctrl = NULL; 939 940 if (!rd->name || 941 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 942 panic("SCMI reset domain name invalid"); 943 944 if (stm32mp_nsec_can_access_clock(rd->reset_id)) 945 continue; 946 947 rstctrl = stm32mp_rcc_reset_id_to_rstctrl(rd->reset_id); 948 assert(rstctrl); 949 if (rstctrl_get_exclusive(rstctrl)) 950 continue; 951 952 rd->rstctrl = rstctrl; 953 } 954 955 for (j = 0; j < res->voltd_count; j++) { 956 struct stm32_scmi_voltd *voltd = &res->voltd[j]; 957 958 if (!voltd->name || 959 strlen(voltd->name) >= SCMI_VOLTD_NAME_SIZE) 960 panic("SCMI voltage domain name invalid"); 961 } 962 } 963 964 return TEE_SUCCESS; 965 } 966 967 driver_init_late(stm32mp1_init_scmi_server); 968