1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <confine_array_index.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/scmi-msg.h> 11 #include <drivers/scmi.h> 12 #include <drivers/stm32mp1_pmic.h> 13 #include <drivers/stm32mp1_pwr.h> 14 #include <drivers/stpmic1.h> 15 #include <dt-bindings/clock/stm32mp1-clks.h> 16 #include <dt-bindings/regulator/st,stm32mp15-regulator.h> 17 #include <dt-bindings/reset/stm32mp1-resets.h> 18 #include <initcall.h> 19 #include <mm/core_memprot.h> 20 #include <mm/core_mmu.h> 21 #include <platform_config.h> 22 #include <stdint.h> 23 #include <speculation_barrier.h> 24 #include <stm32_util.h> 25 #include <string.h> 26 #include <tee_api_defines.h> 27 #include <util.h> 28 29 #define TIMEOUT_US_1MS 1000 30 31 #define SCMI_CLOCK_NAME_SIZE 16 32 #define SCMI_RD_NAME_SIZE 16 33 #define SCMI_VOLTD_NAME_SIZE 16 34 35 /* 36 * struct stm32_scmi_clk - Data for the exposed clock 37 * @clock_id: Clock identifier in RCC clock driver 38 * @name: Clock string ID exposed to channel 39 * @enabled: State of the SCMI clock 40 */ 41 struct stm32_scmi_clk { 42 unsigned long clock_id; 43 struct clk *clk; 44 const char *name; 45 bool enabled; 46 }; 47 48 /* 49 * struct stm32_scmi_rd - Data for the exposed reset controller 50 * @reset_id: Reset identifier in RCC reset driver 51 * @name: Reset string ID exposed to channel 52 */ 53 struct stm32_scmi_rd { 54 unsigned long reset_id; 55 const char *name; 56 }; 57 58 enum voltd_device { 59 VOLTD_PWR, 60 VOLTD_PMIC, 61 }; 62 63 /* 64 * struct stm32_scmi_voltd - Data for the exposed voltage domains 65 * @name: Power regulator string ID exposed to channel 66 * @priv_id: Internal string ID for the regulator 67 * @priv_dev: Internal ID for the device implementing the regulator 68 */ 69 struct stm32_scmi_voltd { 70 const char *name; 71 const char *priv_id; 72 enum voltd_device priv_dev; 73 74 }; 75 76 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 77 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 78 #define SMT_BUFFER0_BASE SMT_BUFFER_BASE 79 #define SMT_BUFFER1_BASE (SMT_BUFFER_BASE + 0x200) 80 81 #if (SMT_BUFFER1_BASE + SMT_BUF_SLOT_SIZE > \ 82 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 83 #error "SCMI shared memory mismatch" 84 #endif 85 86 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 87 CFG_STM32MP1_SCMI_SHM_SIZE); 88 89 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 90 [_scmi_id] = { \ 91 .clock_id = _id, \ 92 .name = _name, \ 93 .enabled = _init_enabled, \ 94 } 95 96 static struct stm32_scmi_clk stm32_scmi0_clock[] = { 97 CLOCK_CELL(CK_SCMI0_HSE, CK_HSE, "ck_hse", true), 98 CLOCK_CELL(CK_SCMI0_HSI, CK_HSI, "ck_hsi", true), 99 CLOCK_CELL(CK_SCMI0_CSI, CK_CSI, "ck_csi", true), 100 CLOCK_CELL(CK_SCMI0_LSE, CK_LSE, "ck_lse", true), 101 CLOCK_CELL(CK_SCMI0_LSI, CK_LSI, "ck_lsi", true), 102 CLOCK_CELL(CK_SCMI0_PLL2_Q, PLL2_Q, "pll2_q", true), 103 CLOCK_CELL(CK_SCMI0_PLL2_R, PLL2_R, "pll2_r", true), 104 CLOCK_CELL(CK_SCMI0_MPU, CK_MPU, "ck_mpu", true), 105 CLOCK_CELL(CK_SCMI0_AXI, CK_AXI, "ck_axi", true), 106 CLOCK_CELL(CK_SCMI0_BSEC, BSEC, "bsec", true), 107 CLOCK_CELL(CK_SCMI0_CRYP1, CRYP1, "cryp1", false), 108 CLOCK_CELL(CK_SCMI0_GPIOZ, GPIOZ, "gpioz", false), 109 CLOCK_CELL(CK_SCMI0_HASH1, HASH1, "hash1", false), 110 CLOCK_CELL(CK_SCMI0_I2C4, I2C4_K, "i2c4_k", false), 111 CLOCK_CELL(CK_SCMI0_I2C6, I2C6_K, "i2c6_k", false), 112 CLOCK_CELL(CK_SCMI0_IWDG1, IWDG1, "iwdg1", false), 113 CLOCK_CELL(CK_SCMI0_RNG1, RNG1_K, "rng1_k", true), 114 CLOCK_CELL(CK_SCMI0_RTC, RTC, "ck_rtc", true), 115 CLOCK_CELL(CK_SCMI0_RTCAPB, RTCAPB, "rtcapb", true), 116 CLOCK_CELL(CK_SCMI0_SPI6, SPI6_K, "spi6_k", false), 117 CLOCK_CELL(CK_SCMI0_USART1, USART1_K, "usart1_k", false), 118 }; 119 120 static struct stm32_scmi_clk stm32_scmi1_clock[] = { 121 CLOCK_CELL(CK_SCMI1_PLL3_Q, PLL3_Q, "pll3_q", true), 122 CLOCK_CELL(CK_SCMI1_PLL3_R, PLL3_R, "pll3_r", true), 123 CLOCK_CELL(CK_SCMI1_MCU, CK_MCU, "ck_mcu", false), 124 }; 125 126 #define RESET_CELL(_scmi_id, _id, _name) \ 127 [_scmi_id] = { \ 128 .reset_id = _id, \ 129 .name = _name, \ 130 } 131 132 static struct stm32_scmi_rd stm32_scmi0_reset_domain[] = { 133 RESET_CELL(RST_SCMI0_SPI6, SPI6_R, "spi6"), 134 RESET_CELL(RST_SCMI0_I2C4, I2C4_R, "i2c4"), 135 RESET_CELL(RST_SCMI0_I2C6, I2C6_R, "i2c6"), 136 RESET_CELL(RST_SCMI0_USART1, USART1_R, "usart1"), 137 RESET_CELL(RST_SCMI0_STGEN, STGEN_R, "stgen"), 138 RESET_CELL(RST_SCMI0_GPIOZ, GPIOZ_R, "gpioz"), 139 RESET_CELL(RST_SCMI0_CRYP1, CRYP1_R, "cryp1"), 140 RESET_CELL(RST_SCMI0_HASH1, HASH1_R, "hash1"), 141 RESET_CELL(RST_SCMI0_RNG1, RNG1_R, "rng1"), 142 RESET_CELL(RST_SCMI0_MDMA, MDMA_R, "mdma"), 143 RESET_CELL(RST_SCMI0_MCU, MCU_R, "mcu"), 144 RESET_CELL(RST_SCMI0_MCU_HOLD_BOOT, MCU_HOLD_BOOT_R, "mcu_hold_boot"), 145 }; 146 147 #define VOLTD_CELL(_scmi_id, _dev_id, _priv_id, _name) \ 148 [_scmi_id] = { \ 149 .priv_id = (_priv_id), \ 150 .priv_dev = (_dev_id), \ 151 .name = (_name), \ 152 } 153 154 #define PWR_REG11_NAME_ID "0" 155 #define PWR_REG18_NAME_ID "1" 156 #define PWR_USB33_NAME_ID "2" 157 158 struct stm32_scmi_voltd scmi0_voltage_domain[] = { 159 VOLTD_CELL(VOLTD_SCMI0_REG11, VOLTD_PWR, PWR_REG11_NAME_ID, "reg11"), 160 VOLTD_CELL(VOLTD_SCMI0_REG18, VOLTD_PWR, PWR_REG18_NAME_ID, "reg18"), 161 VOLTD_CELL(VOLTD_SCMI0_USB33, VOLTD_PWR, PWR_USB33_NAME_ID, "usb33"), 162 }; 163 164 struct channel_resources { 165 struct scmi_msg_channel *channel; 166 struct stm32_scmi_clk *clock; 167 size_t clock_count; 168 struct stm32_scmi_rd *rd; 169 size_t rd_count; 170 struct stm32_scmi_voltd *voltd; 171 size_t voltd_count; 172 }; 173 174 static const struct channel_resources scmi_channel[] = { 175 [0] = { 176 .channel = &(struct scmi_msg_channel){ 177 .shm_addr = { .pa = SMT_BUFFER0_BASE }, 178 .shm_size = SMT_BUF_SLOT_SIZE, 179 }, 180 .clock = stm32_scmi0_clock, 181 .clock_count = ARRAY_SIZE(stm32_scmi0_clock), 182 .rd = stm32_scmi0_reset_domain, 183 .rd_count = ARRAY_SIZE(stm32_scmi0_reset_domain), 184 .voltd = scmi0_voltage_domain, 185 .voltd_count = ARRAY_SIZE(scmi0_voltage_domain), 186 }, 187 [1] = { 188 .channel = &(struct scmi_msg_channel){ 189 .shm_addr = { .pa = SMT_BUFFER1_BASE }, 190 .shm_size = SMT_BUF_SLOT_SIZE, 191 }, 192 .clock = stm32_scmi1_clock, 193 .clock_count = ARRAY_SIZE(stm32_scmi1_clock), 194 }, 195 }; 196 197 static const struct channel_resources *find_resource(unsigned int channel_id) 198 { 199 assert(channel_id < ARRAY_SIZE(scmi_channel)); 200 201 return scmi_channel + channel_id; 202 } 203 204 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int channel_id) 205 { 206 const size_t max_id = ARRAY_SIZE(scmi_channel); 207 unsigned int confined_id = confine_array_index(channel_id, max_id); 208 209 if (channel_id >= max_id) 210 return NULL; 211 212 return find_resource(confined_id)->channel; 213 } 214 215 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 216 { 217 unsigned int n = 0; 218 unsigned int count = 0; 219 const size_t channel_count = ARRAY_SIZE(scmi_channel); 220 221 for (n = 0; n < channel_count; n++) 222 if (scmi_channel[n].clock_count) 223 break; 224 if (n < channel_count) 225 count++; 226 227 for (n = 0; n < channel_count; n++) 228 if (scmi_channel[n].rd_count) 229 break; 230 if (n < channel_count) 231 count++; 232 233 for (n = 0; n < channel_count; n++) 234 if (scmi_channel[n].voltd_count) 235 break; 236 if (n < channel_count) 237 count++; 238 239 return count; 240 } 241 242 static const char vendor[] = "ST"; 243 static const char sub_vendor[] = ""; 244 245 const char *plat_scmi_vendor_name(void) 246 { 247 return vendor; 248 } 249 250 const char *plat_scmi_sub_vendor_name(void) 251 { 252 return sub_vendor; 253 } 254 255 /* Currently supporting Clocks and Reset Domains */ 256 static const uint8_t plat_protocol_list[] = { 257 SCMI_PROTOCOL_ID_CLOCK, 258 SCMI_PROTOCOL_ID_RESET_DOMAIN, 259 SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, 260 0 /* Null termination */ 261 }; 262 263 size_t plat_scmi_protocol_count(void) 264 { 265 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 266 267 assert(count == plat_scmi_protocol_count_paranoid()); 268 269 return count; 270 } 271 272 const uint8_t *plat_scmi_protocol_list(unsigned int channel_id __unused) 273 { 274 assert(plat_scmi_protocol_count_paranoid() == 275 (ARRAY_SIZE(plat_protocol_list) - 1)); 276 277 return plat_protocol_list; 278 } 279 280 /* 281 * Platform SCMI clocks 282 */ 283 static struct stm32_scmi_clk *find_clock(unsigned int channel_id, 284 unsigned int scmi_id) 285 { 286 const struct channel_resources *resource = find_resource(channel_id); 287 size_t n = 0; 288 289 if (resource) { 290 for (n = 0; n < resource->clock_count; n++) 291 if (n == scmi_id) 292 return &resource->clock[n]; 293 } 294 295 return NULL; 296 } 297 298 size_t plat_scmi_clock_count(unsigned int channel_id) 299 { 300 const struct channel_resources *resource = find_resource(channel_id); 301 302 if (!resource) 303 return 0; 304 305 return resource->clock_count; 306 } 307 308 const char *plat_scmi_clock_get_name(unsigned int channel_id, 309 unsigned int scmi_id) 310 { 311 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 312 313 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 314 return NULL; 315 316 return clock->name; 317 } 318 319 int32_t plat_scmi_clock_rates_array(unsigned int channel_id, 320 unsigned int scmi_id, size_t start_index, 321 unsigned long *array, size_t *nb_elts) 322 { 323 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 324 325 if (!clock) 326 return SCMI_NOT_FOUND; 327 328 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 329 return SCMI_DENIED; 330 331 /* Exposed clocks are currently fixed rate clocks */ 332 if (start_index) 333 return SCMI_INVALID_PARAMETERS; 334 335 if (!array) 336 *nb_elts = 1; 337 else if (*nb_elts == 1) 338 *array = clk_get_rate(clock->clk); 339 else 340 return SCMI_GENERIC_ERROR; 341 342 return SCMI_SUCCESS; 343 } 344 345 unsigned long plat_scmi_clock_get_rate(unsigned int channel_id, 346 unsigned int scmi_id) 347 { 348 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 349 350 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 351 return 0; 352 353 return clk_get_rate(clock->clk); 354 } 355 356 int32_t plat_scmi_clock_get_state(unsigned int channel_id, unsigned int scmi_id) 357 { 358 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 359 360 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 361 return 0; 362 363 return (int32_t)clock->enabled; 364 } 365 366 int32_t plat_scmi_clock_set_state(unsigned int channel_id, unsigned int scmi_id, 367 bool enable_not_disable) 368 { 369 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 370 371 if (!clock) 372 return SCMI_NOT_FOUND; 373 374 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 375 return SCMI_DENIED; 376 377 if (enable_not_disable) { 378 if (!clock->enabled) { 379 DMSG("SCMI clock %u enable", scmi_id); 380 clk_enable(clock->clk); 381 clock->enabled = true; 382 } 383 } else { 384 if (clock->enabled) { 385 DMSG("SCMI clock %u disable", scmi_id); 386 clk_disable(clock->clk); 387 clock->enabled = false; 388 } 389 } 390 391 return SCMI_SUCCESS; 392 } 393 394 /* 395 * Platform SCMI reset domains 396 */ 397 static struct stm32_scmi_rd *find_rd(unsigned int channel_id, 398 unsigned int scmi_id) 399 { 400 const struct channel_resources *resource = find_resource(channel_id); 401 size_t n = 0; 402 403 if (resource) { 404 for (n = 0; n < resource->rd_count; n++) 405 if (n == scmi_id) 406 return &resource->rd[n]; 407 } 408 409 return NULL; 410 } 411 412 const char *plat_scmi_rd_get_name(unsigned int channel_id, unsigned int scmi_id) 413 { 414 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 415 416 if (!rd) 417 return NULL; 418 419 return rd->name; 420 } 421 422 size_t plat_scmi_rd_count(unsigned int channel_id) 423 { 424 const struct channel_resources *resource = find_resource(channel_id); 425 426 if (!resource) 427 return 0; 428 429 return resource->rd_count; 430 } 431 432 int32_t plat_scmi_rd_autonomous(unsigned int channel_id, unsigned int scmi_id, 433 uint32_t state) 434 { 435 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 436 437 if (!rd) 438 return SCMI_NOT_FOUND; 439 440 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 441 return SCMI_DENIED; 442 443 if (rd->reset_id == MCU_HOLD_BOOT_R) 444 return SCMI_NOT_SUPPORTED; 445 446 /* Supports only reset with context loss */ 447 if (state) 448 return SCMI_NOT_SUPPORTED; 449 450 DMSG("SCMI reset %u cycle", scmi_id); 451 452 if (stm32_reset_assert(rd->reset_id, TIMEOUT_US_1MS)) 453 return SCMI_HARDWARE_ERROR; 454 455 if (stm32_reset_deassert(rd->reset_id, TIMEOUT_US_1MS)) 456 return SCMI_HARDWARE_ERROR; 457 458 return SCMI_SUCCESS; 459 } 460 461 int32_t plat_scmi_rd_set_state(unsigned int channel_id, unsigned int scmi_id, 462 bool assert_not_deassert) 463 { 464 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 465 466 if (!rd) 467 return SCMI_NOT_FOUND; 468 469 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 470 return SCMI_DENIED; 471 472 if (rd->reset_id == MCU_HOLD_BOOT_R) { 473 DMSG("SCMI MCU hold boot %s", 474 assert_not_deassert ? "set" : "release"); 475 stm32_reset_assert_deassert_mcu(assert_not_deassert); 476 return SCMI_SUCCESS; 477 } 478 479 if (assert_not_deassert) { 480 DMSG("SCMI reset %u set", scmi_id); 481 stm32_reset_set(rd->reset_id); 482 } else { 483 DMSG("SCMI reset %u release", scmi_id); 484 stm32_reset_release(rd->reset_id); 485 } 486 487 return SCMI_SUCCESS; 488 } 489 490 /* 491 * Platform SCMI voltage domains 492 */ 493 static struct stm32_scmi_voltd *find_voltd(unsigned int channel_id, 494 unsigned int scmi_id) 495 { 496 const struct channel_resources *resource = find_resource(channel_id); 497 size_t n = 0; 498 499 if (resource) { 500 for (n = 0; n < resource->voltd_count; n++) 501 if (n == scmi_id) 502 return &resource->voltd[n]; 503 } 504 505 return NULL; 506 } 507 508 size_t plat_scmi_voltd_count(unsigned int channel_id) 509 { 510 const struct channel_resources *resource = find_resource(channel_id); 511 512 if (!resource) 513 return 0; 514 515 return resource->voltd_count; 516 } 517 518 const char *plat_scmi_voltd_get_name(unsigned int channel_id, 519 unsigned int scmi_id) 520 { 521 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 522 523 /* Currently non-secure is allowed to access all PWR regulators */ 524 if (!voltd) 525 return NULL; 526 527 return voltd->name; 528 } 529 530 static enum pwr_regulator pwr_scmi_to_regu_id(struct stm32_scmi_voltd *voltd) 531 { 532 if (!strcmp(voltd->priv_id, PWR_REG11_NAME_ID)) 533 return PWR_REG11; 534 if (!strcmp(voltd->priv_id, PWR_REG18_NAME_ID)) 535 return PWR_REG18; 536 if (!strcmp(voltd->priv_id, PWR_USB33_NAME_ID)) 537 return PWR_USB33; 538 539 panic(); 540 } 541 542 static long pwr_get_level(struct stm32_scmi_voltd *voltd) 543 { 544 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 545 546 return (long)stm32mp1_pwr_regulator_mv(regu_id) * 1000; 547 } 548 549 static int32_t pwr_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 550 { 551 if (level_uv != pwr_get_level(voltd)) 552 return SCMI_INVALID_PARAMETERS; 553 554 return SCMI_SUCCESS; 555 } 556 557 static int32_t pwr_describe_levels(struct stm32_scmi_voltd *voltd, 558 size_t start_index, long *microvolt, 559 size_t *nb_elts) 560 { 561 if (start_index) 562 return SCMI_INVALID_PARAMETERS; 563 564 if (!microvolt) { 565 *nb_elts = 1; 566 return SCMI_SUCCESS; 567 } 568 569 if (*nb_elts < 1) 570 return SCMI_GENERIC_ERROR; 571 572 *nb_elts = 1; 573 *microvolt = pwr_get_level(voltd); 574 575 return SCMI_SUCCESS; 576 } 577 578 static uint32_t pwr_get_state(struct stm32_scmi_voltd *voltd) 579 { 580 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 581 582 if (stm32mp1_pwr_regulator_is_enabled(regu_id)) 583 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 584 585 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 586 } 587 588 static void pwr_set_state(struct stm32_scmi_voltd *voltd, bool enable) 589 { 590 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 591 592 DMSG("%sable PWR %s (was %s)", enable ? "En" : "Dis", voltd->name, 593 stm32mp1_pwr_regulator_is_enabled(regu_id) ? "on" : "off"); 594 595 stm32mp1_pwr_regulator_set_state(regu_id, enable); 596 } 597 598 static int32_t pmic_describe_levels(struct stm32_scmi_voltd *voltd, 599 size_t start_index, long *microvolt, 600 size_t *nb_elts) 601 { 602 const uint16_t *levels = NULL; 603 size_t full_count = 0; 604 size_t out_count = 0; 605 size_t i = 0; 606 607 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 608 return SCMI_DENIED; 609 610 stpmic1_regulator_levels_mv(voltd->priv_id, &levels, &full_count); 611 612 if (!microvolt) { 613 *nb_elts = full_count - start_index; 614 return SCMI_SUCCESS; 615 } 616 617 if (SUB_OVERFLOW(full_count, start_index, &out_count)) 618 return SCMI_GENERIC_ERROR; 619 620 out_count = MIN(out_count, *nb_elts); 621 622 FMSG("%zu levels: start %zu requested %zu output %zu", 623 full_count, start_index, *nb_elts, out_count); 624 625 for (i = 0; i < out_count; i++) 626 microvolt[i] = levels[start_index + i] * 1000; 627 628 *nb_elts = out_count; 629 630 return SCMI_SUCCESS; 631 } 632 633 static long pmic_get_level(struct stm32_scmi_voltd *voltd) 634 { 635 unsigned long level_mv = 0; 636 637 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 638 return 0; 639 640 stm32mp_get_pmic(); 641 level_mv = stpmic1_regulator_voltage_get(voltd->priv_id); 642 stm32mp_put_pmic(); 643 644 return (long)level_mv * 1000; 645 } 646 647 static int32_t pmic_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 648 { 649 int rc = 0; 650 unsigned int level_mv = 0; 651 652 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 653 return SCMI_DENIED; 654 655 if (level_uv < 0 || level_uv > (UINT16_MAX * 1000)) 656 return SCMI_INVALID_PARAMETERS; 657 658 level_mv = (unsigned int)level_uv / 1000; 659 660 DMSG("Set STPMIC1 regulator %s level to %dmV", voltd->name, level_mv); 661 662 stm32mp_get_pmic(); 663 rc = stpmic1_regulator_voltage_set(voltd->priv_id, level_mv); 664 stm32mp_put_pmic(); 665 666 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 667 } 668 669 static uint32_t pmic_get_state(struct stm32_scmi_voltd *voltd) 670 { 671 bool enabled = false; 672 673 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 674 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 675 676 stm32mp_get_pmic(); 677 enabled = stpmic1_is_regulator_enabled(voltd->priv_id); 678 stm32mp_put_pmic(); 679 680 if (enabled) 681 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 682 683 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 684 } 685 686 static int32_t pmic_set_state(struct stm32_scmi_voltd *voltd, bool enable) 687 { 688 int rc = 0; 689 690 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 691 return SCMI_DENIED; 692 693 stm32mp_get_pmic(); 694 695 DMSG("%sable STPMIC1 %s (was %s)", enable ? "En" : "Dis", voltd->name, 696 stpmic1_is_regulator_enabled(voltd->priv_id) ? "on" : "off"); 697 698 if (enable) 699 rc = stpmic1_regulator_enable(voltd->priv_id); 700 else 701 rc = stpmic1_regulator_disable(voltd->priv_id); 702 703 stm32mp_put_pmic(); 704 705 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 706 } 707 708 int32_t plat_scmi_voltd_levels_array(unsigned int channel_id, 709 unsigned int scmi_id, size_t start_index, 710 long *levels, size_t *nb_elts) 711 712 { 713 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 714 715 if (!voltd) 716 return SCMI_NOT_FOUND; 717 718 switch (voltd->priv_dev) { 719 case VOLTD_PWR: 720 return pwr_describe_levels(voltd, start_index, levels, nb_elts); 721 case VOLTD_PMIC: 722 return pmic_describe_levels(voltd, start_index, levels, 723 nb_elts); 724 default: 725 return SCMI_GENERIC_ERROR; 726 } 727 } 728 729 long plat_scmi_voltd_get_level(unsigned int channel_id, unsigned int scmi_id) 730 { 731 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 732 733 if (!voltd) 734 return 0; 735 736 switch (voltd->priv_dev) { 737 case VOLTD_PWR: 738 return pwr_get_level(voltd); 739 case VOLTD_PMIC: 740 return pmic_get_level(voltd); 741 default: 742 panic(); 743 } 744 } 745 746 int32_t plat_scmi_voltd_set_level(unsigned int channel_id, unsigned int scmi_id, 747 long level) 748 { 749 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 750 751 if (!voltd) 752 return SCMI_NOT_FOUND; 753 754 switch (voltd->priv_dev) { 755 case VOLTD_PWR: 756 return pwr_set_level(voltd, level); 757 case VOLTD_PMIC: 758 return pmic_set_level(voltd, level); 759 default: 760 return SCMI_GENERIC_ERROR; 761 } 762 } 763 764 int32_t plat_scmi_voltd_get_config(unsigned int channel_id, 765 unsigned int scmi_id, uint32_t *config) 766 { 767 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 768 769 if (!voltd) 770 return SCMI_NOT_FOUND; 771 772 switch (voltd->priv_dev) { 773 case VOLTD_PWR: 774 *config = pwr_get_state(voltd); 775 break; 776 case VOLTD_PMIC: 777 *config = pmic_get_state(voltd); 778 break; 779 default: 780 return SCMI_GENERIC_ERROR; 781 } 782 783 return SCMI_SUCCESS; 784 } 785 786 int32_t plat_scmi_voltd_set_config(unsigned int channel_id, 787 unsigned int scmi_id, uint32_t config) 788 { 789 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 790 int32_t rc = SCMI_SUCCESS; 791 792 if (!voltd) 793 return SCMI_NOT_FOUND; 794 795 switch (voltd->priv_dev) { 796 case VOLTD_PWR: 797 pwr_set_state(voltd, config); 798 break; 799 case VOLTD_PMIC: 800 rc = pmic_set_state(voltd, config); 801 break; 802 default: 803 return SCMI_GENERIC_ERROR; 804 } 805 806 return rc; 807 } 808 809 /* 810 * Initialize platform SCMI resources 811 */ 812 static TEE_Result stm32mp1_init_scmi_server(void) 813 { 814 size_t i = 0; 815 size_t j = 0; 816 817 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 818 const struct channel_resources *res = scmi_channel + i; 819 struct scmi_msg_channel *chan = res->channel; 820 821 /* Enforce non-secure shm mapped as device memory */ 822 chan->shm_addr.va = (vaddr_t)phys_to_virt(chan->shm_addr.pa, 823 MEM_AREA_IO_NSEC, 1); 824 assert(chan->shm_addr.va); 825 826 scmi_smt_init_agent_channel(chan); 827 828 for (j = 0; j < res->clock_count; j++) { 829 struct stm32_scmi_clk *clk = &res->clock[j]; 830 831 if (!clk->name || 832 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 833 panic("SCMI clock name invalid"); 834 835 clk->clk = stm32mp_rcc_clock_id_to_clk(clk->clock_id); 836 assert(clk->clk); 837 838 /* Sync SCMI clocks with their targeted initial state */ 839 if (clk->enabled && 840 stm32mp_nsec_can_access_clock(clk->clock_id)) 841 clk_enable(clk->clk); 842 } 843 844 for (j = 0; j < res->rd_count; j++) { 845 struct stm32_scmi_rd *rd = &res->rd[j]; 846 847 if (!rd->name || 848 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 849 panic("SCMI reset domain name invalid"); 850 } 851 852 for (j = 0; j < res->voltd_count; j++) { 853 struct stm32_scmi_voltd *voltd = &res->voltd[j]; 854 855 if (!voltd->name || 856 strlen(voltd->name) >= SCMI_VOLTD_NAME_SIZE) 857 panic("SCMI voltage domain name invalid"); 858 } 859 } 860 861 return TEE_SUCCESS; 862 } 863 864 driver_init_late(stm32mp1_init_scmi_server); 865