1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <confine_array_index.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/rstctrl.h> 11 #include <drivers/scmi-msg.h> 12 #include <drivers/scmi.h> 13 #include <drivers/stm32mp1_pmic.h> 14 #include <drivers/stm32mp1_pwr.h> 15 #include <drivers/stpmic1.h> 16 #include <drivers/stpmic1_regulator.h> 17 #include <dt-bindings/clock/stm32mp1-clks.h> 18 #include <dt-bindings/regulator/st,stm32mp15-regulator.h> 19 #include <dt-bindings/reset/stm32mp1-resets.h> 20 #include <initcall.h> 21 #include <mm/core_memprot.h> 22 #include <mm/core_mmu.h> 23 #include <platform_config.h> 24 #include <stdint.h> 25 #include <speculation_barrier.h> 26 #include <stm32_util.h> 27 #include <string.h> 28 #include <tee_api_defines.h> 29 #include <util.h> 30 31 #define TIMEOUT_US_1MS 1000 32 33 #define SCMI_CLOCK_NAME_SIZE 16 34 #define SCMI_RD_NAME_SIZE 16 35 #define SCMI_VOLTD_NAME_SIZE 16 36 37 /* 38 * struct stm32_scmi_clk - Data for the exposed clock 39 * @clock_id: Clock identifier in RCC clock driver 40 * @name: Clock string ID exposed to channel 41 * @enabled: State of the SCMI clock 42 */ 43 struct stm32_scmi_clk { 44 unsigned long clock_id; 45 struct clk *clk; 46 const char *name; 47 bool enabled; 48 }; 49 50 /* 51 * struct stm32_scmi_rd - Data for the exposed reset controller 52 * @reset_id: Reset identifier in RCC reset driver 53 * @name: Reset string ID exposed to channel 54 * @rstctrl: Reset controller device 55 */ 56 struct stm32_scmi_rd { 57 unsigned long reset_id; 58 const char *name; 59 struct rstctrl *rstctrl; 60 }; 61 62 enum voltd_device { 63 VOLTD_PWR, 64 VOLTD_PMIC, 65 }; 66 67 /* 68 * struct stm32_scmi_voltd - Data for the exposed voltage domains 69 * @name: Power regulator string ID exposed to channel 70 * @priv_id: Internal string ID for the regulator 71 * @priv_dev: Internal ID for the device implementing the regulator 72 */ 73 struct stm32_scmi_voltd { 74 const char *name; 75 const char *priv_id; 76 enum voltd_device priv_dev; 77 78 }; 79 80 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 81 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 82 #define SMT_BUFFER0_BASE SMT_BUFFER_BASE 83 #define SMT_BUFFER1_BASE (SMT_BUFFER_BASE + 0x200) 84 85 #if (SMT_BUFFER1_BASE + SMT_BUF_SLOT_SIZE > \ 86 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 87 #error "SCMI shared memory mismatch" 88 #endif 89 90 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 91 CFG_STM32MP1_SCMI_SHM_SIZE); 92 93 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 94 [_scmi_id] = { \ 95 .clock_id = _id, \ 96 .name = _name, \ 97 .enabled = _init_enabled, \ 98 } 99 100 static struct stm32_scmi_clk stm32_scmi0_clock[] = { 101 CLOCK_CELL(CK_SCMI0_HSE, CK_HSE, "ck_hse", true), 102 CLOCK_CELL(CK_SCMI0_HSI, CK_HSI, "ck_hsi", true), 103 CLOCK_CELL(CK_SCMI0_CSI, CK_CSI, "ck_csi", true), 104 CLOCK_CELL(CK_SCMI0_LSE, CK_LSE, "ck_lse", true), 105 CLOCK_CELL(CK_SCMI0_LSI, CK_LSI, "ck_lsi", true), 106 CLOCK_CELL(CK_SCMI0_PLL2_Q, PLL2_Q, "pll2_q", true), 107 CLOCK_CELL(CK_SCMI0_PLL2_R, PLL2_R, "pll2_r", true), 108 CLOCK_CELL(CK_SCMI0_MPU, CK_MPU, "ck_mpu", true), 109 CLOCK_CELL(CK_SCMI0_AXI, CK_AXI, "ck_axi", true), 110 CLOCK_CELL(CK_SCMI0_BSEC, BSEC, "bsec", true), 111 CLOCK_CELL(CK_SCMI0_CRYP1, CRYP1, "cryp1", false), 112 CLOCK_CELL(CK_SCMI0_GPIOZ, GPIOZ, "gpioz", false), 113 CLOCK_CELL(CK_SCMI0_HASH1, HASH1, "hash1", false), 114 CLOCK_CELL(CK_SCMI0_I2C4, I2C4_K, "i2c4_k", false), 115 CLOCK_CELL(CK_SCMI0_I2C6, I2C6_K, "i2c6_k", false), 116 CLOCK_CELL(CK_SCMI0_IWDG1, IWDG1, "iwdg1", false), 117 CLOCK_CELL(CK_SCMI0_RNG1, RNG1_K, "rng1_k", true), 118 CLOCK_CELL(CK_SCMI0_RTC, RTC, "ck_rtc", true), 119 CLOCK_CELL(CK_SCMI0_RTCAPB, RTCAPB, "rtcapb", true), 120 CLOCK_CELL(CK_SCMI0_SPI6, SPI6_K, "spi6_k", false), 121 CLOCK_CELL(CK_SCMI0_USART1, USART1_K, "usart1_k", false), 122 }; 123 124 static struct stm32_scmi_clk stm32_scmi1_clock[] = { 125 CLOCK_CELL(CK_SCMI1_PLL3_Q, PLL3_Q, "pll3_q", true), 126 CLOCK_CELL(CK_SCMI1_PLL3_R, PLL3_R, "pll3_r", true), 127 CLOCK_CELL(CK_SCMI1_MCU, CK_MCU, "ck_mcu", false), 128 }; 129 130 #define RESET_CELL(_scmi_id, _id, _name) \ 131 [_scmi_id] = { \ 132 .reset_id = _id, \ 133 .name = _name, \ 134 } 135 136 static struct stm32_scmi_rd stm32_scmi0_reset_domain[] = { 137 RESET_CELL(RST_SCMI0_SPI6, SPI6_R, "spi6"), 138 RESET_CELL(RST_SCMI0_I2C4, I2C4_R, "i2c4"), 139 RESET_CELL(RST_SCMI0_I2C6, I2C6_R, "i2c6"), 140 RESET_CELL(RST_SCMI0_USART1, USART1_R, "usart1"), 141 RESET_CELL(RST_SCMI0_STGEN, STGEN_R, "stgen"), 142 RESET_CELL(RST_SCMI0_GPIOZ, GPIOZ_R, "gpioz"), 143 RESET_CELL(RST_SCMI0_CRYP1, CRYP1_R, "cryp1"), 144 RESET_CELL(RST_SCMI0_HASH1, HASH1_R, "hash1"), 145 RESET_CELL(RST_SCMI0_RNG1, RNG1_R, "rng1"), 146 RESET_CELL(RST_SCMI0_MDMA, MDMA_R, "mdma"), 147 RESET_CELL(RST_SCMI0_MCU, MCU_R, "mcu"), 148 RESET_CELL(RST_SCMI0_MCU_HOLD_BOOT, MCU_HOLD_BOOT_R, "mcu_hold_boot"), 149 }; 150 151 #define VOLTD_CELL(_scmi_id, _dev_id, _priv_id, _name) \ 152 [_scmi_id] = { \ 153 .priv_id = (_priv_id), \ 154 .priv_dev = (_dev_id), \ 155 .name = (_name), \ 156 } 157 158 #define PWR_REG11_NAME_ID "0" 159 #define PWR_REG18_NAME_ID "1" 160 #define PWR_USB33_NAME_ID "2" 161 162 struct stm32_scmi_voltd scmi0_voltage_domain[] = { 163 VOLTD_CELL(VOLTD_SCMI0_REG11, VOLTD_PWR, PWR_REG11_NAME_ID, "reg11"), 164 VOLTD_CELL(VOLTD_SCMI0_REG18, VOLTD_PWR, PWR_REG18_NAME_ID, "reg18"), 165 VOLTD_CELL(VOLTD_SCMI0_USB33, VOLTD_PWR, PWR_USB33_NAME_ID, "usb33"), 166 VOLTD_CELL(VOLTD_SCMI0_STPMIC1_BUCK1, VOLTD_PMIC, "buck1", "vddcore"), 167 VOLTD_CELL(VOLTD_SCMI0_STPMIC1_BUCK2, VOLTD_PMIC, "buck2", "vdd_ddr"), 168 VOLTD_CELL(VOLTD_SCMI0_STPMIC1_BUCK3, VOLTD_PMIC, "buck3", "vdd"), 169 VOLTD_CELL(VOLTD_SCMI0_STPMIC1_BUCK4, VOLTD_PMIC, "buck4", "v3v3"), 170 VOLTD_CELL(VOLTD_SCMI0_STPMIC1_LDO1, VOLTD_PMIC, "ldo1", "v1v8_audio"), 171 VOLTD_CELL(VOLTD_SCMI0_STPMIC1_LDO2, VOLTD_PMIC, "ldo2", "v3v3_hdmi"), 172 VOLTD_CELL(VOLTD_SCMI0_STPMIC1_LDO3, VOLTD_PMIC, "ldo3", "vtt_ddr"), 173 VOLTD_CELL(VOLTD_SCMI0_STPMIC1_LDO4, VOLTD_PMIC, "ldo4", "vdd_usb"), 174 VOLTD_CELL(VOLTD_SCMI0_STPMIC1_LDO5, VOLTD_PMIC, "ldo5", "vdda"), 175 VOLTD_CELL(VOLTD_SCMI0_STPMIC1_LDO6, VOLTD_PMIC, "ldo6", "v1v2_hdmi"), 176 VOLTD_CELL(VOLTD_SCMI0_STPMIC1_VREFDDR, VOLTD_PMIC, "vref_ddr", 177 "vref_ddr"), 178 VOLTD_CELL(VOLTD_SCMI0_STPMIC1_BOOST, VOLTD_PMIC, "boost", "bst_out"), 179 VOLTD_CELL(VOLTD_SCMI0_STPMIC1_PWR_SW1, VOLTD_PMIC, "pwr_sw1", 180 "vbus_otg"), 181 VOLTD_CELL(VOLTD_SCMI0_STPMIC1_PWR_SW2, VOLTD_PMIC, "pwr_sw2", 182 "vbus_sw"), 183 }; 184 185 struct channel_resources { 186 struct scmi_msg_channel *channel; 187 struct stm32_scmi_clk *clock; 188 size_t clock_count; 189 struct stm32_scmi_rd *rd; 190 size_t rd_count; 191 struct stm32_scmi_voltd *voltd; 192 size_t voltd_count; 193 }; 194 195 static const struct channel_resources scmi_channel[] = { 196 [0] = { 197 .channel = &(struct scmi_msg_channel){ 198 .shm_addr = { .pa = SMT_BUFFER0_BASE }, 199 .shm_size = SMT_BUF_SLOT_SIZE, 200 }, 201 .clock = stm32_scmi0_clock, 202 .clock_count = ARRAY_SIZE(stm32_scmi0_clock), 203 .rd = stm32_scmi0_reset_domain, 204 .rd_count = ARRAY_SIZE(stm32_scmi0_reset_domain), 205 .voltd = scmi0_voltage_domain, 206 .voltd_count = ARRAY_SIZE(scmi0_voltage_domain), 207 }, 208 [1] = { 209 .channel = &(struct scmi_msg_channel){ 210 .shm_addr = { .pa = SMT_BUFFER1_BASE }, 211 .shm_size = SMT_BUF_SLOT_SIZE, 212 }, 213 .clock = stm32_scmi1_clock, 214 .clock_count = ARRAY_SIZE(stm32_scmi1_clock), 215 }, 216 }; 217 218 static const struct channel_resources *find_resource(unsigned int channel_id) 219 { 220 assert(channel_id < ARRAY_SIZE(scmi_channel)); 221 222 return scmi_channel + channel_id; 223 } 224 225 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int channel_id) 226 { 227 const size_t max_id = ARRAY_SIZE(scmi_channel); 228 unsigned int confined_id = confine_array_index(channel_id, max_id); 229 230 if (channel_id >= max_id) 231 return NULL; 232 233 return find_resource(confined_id)->channel; 234 } 235 236 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 237 { 238 unsigned int n = 0; 239 unsigned int count = 0; 240 const size_t channel_count = ARRAY_SIZE(scmi_channel); 241 242 for (n = 0; n < channel_count; n++) 243 if (scmi_channel[n].clock_count) 244 break; 245 if (n < channel_count) 246 count++; 247 248 for (n = 0; n < channel_count; n++) 249 if (scmi_channel[n].rd_count) 250 break; 251 if (n < channel_count) 252 count++; 253 254 for (n = 0; n < channel_count; n++) 255 if (scmi_channel[n].voltd_count) 256 break; 257 if (n < channel_count) 258 count++; 259 260 return count; 261 } 262 263 static const char vendor[] = "ST"; 264 static const char sub_vendor[] = ""; 265 266 const char *plat_scmi_vendor_name(void) 267 { 268 return vendor; 269 } 270 271 const char *plat_scmi_sub_vendor_name(void) 272 { 273 return sub_vendor; 274 } 275 276 /* Currently supporting Clocks and Reset Domains */ 277 static const uint8_t plat_protocol_list[] = { 278 SCMI_PROTOCOL_ID_CLOCK, 279 SCMI_PROTOCOL_ID_RESET_DOMAIN, 280 SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, 281 0 /* Null termination */ 282 }; 283 284 size_t plat_scmi_protocol_count(void) 285 { 286 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 287 288 assert(count == plat_scmi_protocol_count_paranoid()); 289 290 return count; 291 } 292 293 const uint8_t *plat_scmi_protocol_list(unsigned int channel_id __unused) 294 { 295 assert(plat_scmi_protocol_count_paranoid() == 296 (ARRAY_SIZE(plat_protocol_list) - 1)); 297 298 return plat_protocol_list; 299 } 300 301 /* 302 * Platform SCMI clocks 303 */ 304 static struct stm32_scmi_clk *find_clock(unsigned int channel_id, 305 unsigned int scmi_id) 306 { 307 const struct channel_resources *resource = find_resource(channel_id); 308 size_t n = 0; 309 310 if (resource) { 311 for (n = 0; n < resource->clock_count; n++) 312 if (n == scmi_id) 313 return &resource->clock[n]; 314 } 315 316 return NULL; 317 } 318 319 size_t plat_scmi_clock_count(unsigned int channel_id) 320 { 321 const struct channel_resources *resource = find_resource(channel_id); 322 323 if (!resource) 324 return 0; 325 326 return resource->clock_count; 327 } 328 329 const char *plat_scmi_clock_get_name(unsigned int channel_id, 330 unsigned int scmi_id) 331 { 332 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 333 334 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 335 return NULL; 336 337 return clock->name; 338 } 339 340 int32_t plat_scmi_clock_rates_array(unsigned int channel_id, 341 unsigned int scmi_id, size_t start_index, 342 unsigned long *array, size_t *nb_elts) 343 { 344 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 345 346 if (!clock) 347 return SCMI_NOT_FOUND; 348 349 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 350 return SCMI_DENIED; 351 352 /* Exposed clocks are currently fixed rate clocks */ 353 if (start_index) 354 return SCMI_INVALID_PARAMETERS; 355 356 if (!array) 357 *nb_elts = 1; 358 else if (*nb_elts == 1) 359 *array = clk_get_rate(clock->clk); 360 else 361 return SCMI_GENERIC_ERROR; 362 363 return SCMI_SUCCESS; 364 } 365 366 unsigned long plat_scmi_clock_get_rate(unsigned int channel_id, 367 unsigned int scmi_id) 368 { 369 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 370 371 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 372 return 0; 373 374 return clk_get_rate(clock->clk); 375 } 376 377 int32_t plat_scmi_clock_get_state(unsigned int channel_id, unsigned int scmi_id) 378 { 379 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 380 381 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 382 return 0; 383 384 return (int32_t)clock->enabled; 385 } 386 387 int32_t plat_scmi_clock_set_state(unsigned int channel_id, unsigned int scmi_id, 388 bool enable_not_disable) 389 { 390 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 391 392 if (!clock) 393 return SCMI_NOT_FOUND; 394 395 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 396 return SCMI_DENIED; 397 398 if (enable_not_disable) { 399 if (!clock->enabled) { 400 DMSG("SCMI clock %u enable", scmi_id); 401 clk_enable(clock->clk); 402 clock->enabled = true; 403 } 404 } else { 405 if (clock->enabled) { 406 DMSG("SCMI clock %u disable", scmi_id); 407 clk_disable(clock->clk); 408 clock->enabled = false; 409 } 410 } 411 412 return SCMI_SUCCESS; 413 } 414 415 /* 416 * Platform SCMI reset domains 417 */ 418 static struct stm32_scmi_rd *find_rd(unsigned int channel_id, 419 unsigned int scmi_id) 420 { 421 const struct channel_resources *resource = find_resource(channel_id); 422 size_t n = 0; 423 424 if (resource) { 425 for (n = 0; n < resource->rd_count; n++) 426 if (n == scmi_id) 427 return &resource->rd[n]; 428 } 429 430 return NULL; 431 } 432 433 const char *plat_scmi_rd_get_name(unsigned int channel_id, unsigned int scmi_id) 434 { 435 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 436 437 if (!rd) 438 return NULL; 439 440 return rd->name; 441 } 442 443 size_t plat_scmi_rd_count(unsigned int channel_id) 444 { 445 const struct channel_resources *resource = find_resource(channel_id); 446 447 if (!resource) 448 return 0; 449 450 return resource->rd_count; 451 } 452 453 int32_t plat_scmi_rd_autonomous(unsigned int channel_id, unsigned int scmi_id, 454 uint32_t state) 455 { 456 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 457 458 if (!rd) 459 return SCMI_NOT_FOUND; 460 461 if (!rd->rstctrl || !stm32mp_nsec_can_access_reset(rd->reset_id)) 462 return SCMI_DENIED; 463 assert(rd->rstctrl); 464 465 if (rd->reset_id == MCU_HOLD_BOOT_R) 466 return SCMI_NOT_SUPPORTED; 467 468 /* Supports only reset with context loss */ 469 if (state) 470 return SCMI_NOT_SUPPORTED; 471 472 DMSG("SCMI reset %u cycle", scmi_id); 473 474 if (rstctrl_assert_to(rd->rstctrl, TIMEOUT_US_1MS)) 475 return SCMI_HARDWARE_ERROR; 476 477 if (rstctrl_deassert_to(rd->rstctrl, TIMEOUT_US_1MS)) 478 return SCMI_HARDWARE_ERROR; 479 480 return SCMI_SUCCESS; 481 } 482 483 int32_t plat_scmi_rd_set_state(unsigned int channel_id, unsigned int scmi_id, 484 bool assert_not_deassert) 485 { 486 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 487 TEE_Result res = TEE_ERROR_GENERIC; 488 489 if (!rd) 490 return SCMI_NOT_FOUND; 491 492 if (!rd->rstctrl || !stm32mp_nsec_can_access_reset(rd->reset_id)) 493 return SCMI_DENIED; 494 assert(rd->rstctrl); 495 496 if (assert_not_deassert) { 497 DMSG("SCMI reset %u set", scmi_id); 498 res = rstctrl_assert(rd->rstctrl); 499 } else { 500 DMSG("SCMI reset %u release", scmi_id); 501 res = rstctrl_deassert(rd->rstctrl); 502 } 503 504 if (res) 505 return SCMI_HARDWARE_ERROR; 506 507 return SCMI_SUCCESS; 508 } 509 510 /* 511 * Platform SCMI voltage domains 512 */ 513 static struct stm32_scmi_voltd *find_voltd(unsigned int channel_id, 514 unsigned int scmi_id) 515 { 516 const struct channel_resources *resource = find_resource(channel_id); 517 size_t n = 0; 518 519 if (resource) { 520 for (n = 0; n < resource->voltd_count; n++) 521 if (n == scmi_id) 522 return &resource->voltd[n]; 523 } 524 525 return NULL; 526 } 527 528 size_t plat_scmi_voltd_count(unsigned int channel_id) 529 { 530 const struct channel_resources *resource = find_resource(channel_id); 531 532 if (!resource) 533 return 0; 534 535 return resource->voltd_count; 536 } 537 538 const char *plat_scmi_voltd_get_name(unsigned int channel_id, 539 unsigned int scmi_id) 540 { 541 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 542 543 /* Currently non-secure is allowed to access all PWR regulators */ 544 if (!voltd) 545 return NULL; 546 547 return voltd->name; 548 } 549 550 static enum pwr_regulator pwr_scmi_to_regu_id(struct stm32_scmi_voltd *voltd) 551 { 552 if (!strcmp(voltd->priv_id, PWR_REG11_NAME_ID)) 553 return PWR_REG11; 554 if (!strcmp(voltd->priv_id, PWR_REG18_NAME_ID)) 555 return PWR_REG18; 556 if (!strcmp(voltd->priv_id, PWR_USB33_NAME_ID)) 557 return PWR_USB33; 558 559 panic(); 560 } 561 562 static long pwr_get_level(struct stm32_scmi_voltd *voltd) 563 { 564 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 565 566 return (long)stm32mp1_pwr_regulator_mv(regu_id) * 1000; 567 } 568 569 static int32_t pwr_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 570 { 571 if (level_uv != pwr_get_level(voltd)) 572 return SCMI_INVALID_PARAMETERS; 573 574 return SCMI_SUCCESS; 575 } 576 577 static int32_t pwr_describe_levels(struct stm32_scmi_voltd *voltd, 578 size_t start_index, long *microvolt, 579 size_t *nb_elts) 580 { 581 if (start_index) 582 return SCMI_INVALID_PARAMETERS; 583 584 if (!microvolt) { 585 *nb_elts = 1; 586 return SCMI_SUCCESS; 587 } 588 589 if (*nb_elts < 1) 590 return SCMI_GENERIC_ERROR; 591 592 *nb_elts = 1; 593 *microvolt = pwr_get_level(voltd); 594 595 return SCMI_SUCCESS; 596 } 597 598 static uint32_t pwr_get_state(struct stm32_scmi_voltd *voltd) 599 { 600 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 601 602 if (stm32mp1_pwr_regulator_is_enabled(regu_id)) 603 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 604 605 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 606 } 607 608 static void pwr_set_state(struct stm32_scmi_voltd *voltd, bool enable) 609 { 610 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 611 612 DMSG("%sable PWR %s (was %s)", enable ? "En" : "Dis", voltd->name, 613 stm32mp1_pwr_regulator_is_enabled(regu_id) ? "on" : "off"); 614 615 stm32mp1_pwr_regulator_set_state(regu_id, enable); 616 } 617 618 static int32_t pmic_describe_levels(struct stm32_scmi_voltd *voltd, 619 size_t start_index, long *microvolt, 620 size_t *nb_elts) 621 { 622 const uint16_t *levels = NULL; 623 size_t full_count = 0; 624 size_t out_count = 0; 625 size_t i = 0; 626 627 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 628 return SCMI_DENIED; 629 630 stpmic1_regulator_levels_mv(voltd->priv_id, &levels, &full_count); 631 632 if (!microvolt) { 633 *nb_elts = full_count - start_index; 634 return SCMI_SUCCESS; 635 } 636 637 if (SUB_OVERFLOW(full_count, start_index, &out_count)) 638 return SCMI_GENERIC_ERROR; 639 640 out_count = MIN(out_count, *nb_elts); 641 642 FMSG("%zu levels: start %zu requested %zu output %zu", 643 full_count, start_index, *nb_elts, out_count); 644 645 for (i = 0; i < out_count; i++) 646 microvolt[i] = levels[start_index + i] * 1000; 647 648 *nb_elts = out_count; 649 650 return SCMI_SUCCESS; 651 } 652 653 static long pmic_get_level(struct stm32_scmi_voltd *voltd) 654 { 655 unsigned long level_mv = 0; 656 657 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 658 return 0; 659 660 stm32mp_get_pmic(); 661 level_mv = stpmic1_regulator_voltage_get(voltd->priv_id); 662 stm32mp_put_pmic(); 663 664 return (long)level_mv * 1000; 665 } 666 667 static int32_t pmic_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 668 { 669 int rc = 0; 670 unsigned int level_mv = 0; 671 672 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 673 return SCMI_DENIED; 674 675 if (level_uv < 0 || level_uv > (UINT16_MAX * 1000)) 676 return SCMI_INVALID_PARAMETERS; 677 678 level_mv = (unsigned int)level_uv / 1000; 679 680 DMSG("Set STPMIC1 regulator %s level to %dmV", voltd->name, level_mv); 681 682 stm32mp_get_pmic(); 683 rc = stpmic1_regulator_voltage_set(voltd->priv_id, level_mv); 684 stm32mp_put_pmic(); 685 686 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 687 } 688 689 static uint32_t pmic_get_state(struct stm32_scmi_voltd *voltd) 690 { 691 bool enabled = false; 692 693 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 694 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 695 696 stm32mp_get_pmic(); 697 enabled = stpmic1_is_regulator_enabled(voltd->priv_id); 698 stm32mp_put_pmic(); 699 700 if (enabled) 701 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 702 703 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 704 } 705 706 static int32_t pmic_set_state(struct stm32_scmi_voltd *voltd, bool enable) 707 { 708 int rc = 0; 709 710 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 711 return SCMI_DENIED; 712 713 stm32mp_get_pmic(); 714 715 DMSG("%sable STPMIC1 %s (was %s)", enable ? "En" : "Dis", voltd->name, 716 stpmic1_is_regulator_enabled(voltd->priv_id) ? "on" : "off"); 717 718 if (enable) 719 rc = stpmic1_regulator_enable(voltd->priv_id); 720 else 721 rc = stpmic1_regulator_disable(voltd->priv_id); 722 723 stm32mp_put_pmic(); 724 725 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 726 } 727 728 int32_t plat_scmi_voltd_levels_array(unsigned int channel_id, 729 unsigned int scmi_id, size_t start_index, 730 long *levels, size_t *nb_elts) 731 732 { 733 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 734 735 if (!voltd) 736 return SCMI_NOT_FOUND; 737 738 switch (voltd->priv_dev) { 739 case VOLTD_PWR: 740 return pwr_describe_levels(voltd, start_index, levels, nb_elts); 741 case VOLTD_PMIC: 742 return pmic_describe_levels(voltd, start_index, levels, 743 nb_elts); 744 default: 745 return SCMI_GENERIC_ERROR; 746 } 747 } 748 749 long plat_scmi_voltd_get_level(unsigned int channel_id, unsigned int scmi_id) 750 { 751 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 752 753 if (!voltd) 754 return 0; 755 756 switch (voltd->priv_dev) { 757 case VOLTD_PWR: 758 return pwr_get_level(voltd); 759 case VOLTD_PMIC: 760 return pmic_get_level(voltd); 761 default: 762 panic(); 763 } 764 } 765 766 int32_t plat_scmi_voltd_set_level(unsigned int channel_id, unsigned int scmi_id, 767 long level) 768 { 769 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 770 771 if (!voltd) 772 return SCMI_NOT_FOUND; 773 774 switch (voltd->priv_dev) { 775 case VOLTD_PWR: 776 return pwr_set_level(voltd, level); 777 case VOLTD_PMIC: 778 return pmic_set_level(voltd, level); 779 default: 780 return SCMI_GENERIC_ERROR; 781 } 782 } 783 784 int32_t plat_scmi_voltd_get_config(unsigned int channel_id, 785 unsigned int scmi_id, uint32_t *config) 786 { 787 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 788 789 if (!voltd) 790 return SCMI_NOT_FOUND; 791 792 switch (voltd->priv_dev) { 793 case VOLTD_PWR: 794 *config = pwr_get_state(voltd); 795 break; 796 case VOLTD_PMIC: 797 *config = pmic_get_state(voltd); 798 break; 799 default: 800 return SCMI_GENERIC_ERROR; 801 } 802 803 return SCMI_SUCCESS; 804 } 805 806 int32_t plat_scmi_voltd_set_config(unsigned int channel_id, 807 unsigned int scmi_id, uint32_t config) 808 { 809 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 810 int32_t rc = SCMI_SUCCESS; 811 812 if (!voltd) 813 return SCMI_NOT_FOUND; 814 815 switch (voltd->priv_dev) { 816 case VOLTD_PWR: 817 pwr_set_state(voltd, config); 818 break; 819 case VOLTD_PMIC: 820 rc = pmic_set_state(voltd, config); 821 break; 822 default: 823 return SCMI_GENERIC_ERROR; 824 } 825 826 return rc; 827 } 828 829 /* 830 * Initialize platform SCMI resources 831 */ 832 static TEE_Result stm32mp1_init_scmi_server(void) 833 { 834 size_t i = 0; 835 size_t j = 0; 836 837 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 838 const struct channel_resources *res = scmi_channel + i; 839 struct scmi_msg_channel *chan = res->channel; 840 841 /* Enforce non-secure shm mapped as device memory */ 842 chan->shm_addr.va = (vaddr_t)phys_to_virt(chan->shm_addr.pa, 843 MEM_AREA_IO_NSEC, 1); 844 assert(chan->shm_addr.va); 845 846 scmi_smt_init_agent_channel(chan); 847 848 for (j = 0; j < res->clock_count; j++) { 849 struct stm32_scmi_clk *clk = &res->clock[j]; 850 851 if (!clk->name || 852 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 853 panic("SCMI clock name invalid"); 854 855 clk->clk = stm32mp_rcc_clock_id_to_clk(clk->clock_id); 856 assert(clk->clk); 857 858 /* Sync SCMI clocks with their targeted initial state */ 859 if (clk->enabled && 860 stm32mp_nsec_can_access_clock(clk->clock_id)) 861 clk_enable(clk->clk); 862 } 863 864 for (j = 0; j < res->rd_count; j++) { 865 struct stm32_scmi_rd *rd = &res->rd[j]; 866 struct rstctrl *rstctrl = NULL; 867 868 if (!rd->name || 869 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 870 panic("SCMI reset domain name invalid"); 871 872 if (stm32mp_nsec_can_access_clock(rd->reset_id)) 873 continue; 874 875 rstctrl = stm32mp_rcc_reset_id_to_rstctrl(rd->reset_id); 876 assert(rstctrl); 877 if (rstctrl_get_exclusive(rstctrl)) 878 continue; 879 880 rd->rstctrl = rstctrl; 881 } 882 883 for (j = 0; j < res->voltd_count; j++) { 884 struct stm32_scmi_voltd *voltd = &res->voltd[j]; 885 886 if (!voltd->name || 887 strlen(voltd->name) >= SCMI_VOLTD_NAME_SIZE) 888 panic("SCMI voltage domain name invalid"); 889 } 890 } 891 892 return TEE_SUCCESS; 893 } 894 895 driver_init_late(stm32mp1_init_scmi_server); 896