1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <drivers/scmi-msg.h> 8 #include <drivers/scmi.h> 9 #include <dt-bindings/clock/stm32mp1-clks.h> 10 #include <dt-bindings/reset/stm32mp1-resets.h> 11 #include <initcall.h> 12 #include <mm/core_memprot.h> 13 #include <mm/core_mmu.h> 14 #include <platform_config.h> 15 #include <stdint.h> 16 #include <speculation_barrier.h> 17 #include <stm32_util.h> 18 #include <string.h> 19 #include <tee_api_defines.h> 20 #include <util.h> 21 22 #define TIMEOUT_US_1MS 1000 23 24 #define SCMI_CLOCK_NAME_SIZE 16 25 #define SCMI_RD_NAME_SIZE 16 26 #define SCMI_VOLTD_NAME_SIZE 16 27 28 /* 29 * struct stm32_scmi_clk - Data for the exposed clock 30 * @clock_id: Clock identifier in RCC clock driver 31 * @name: Clock string ID exposed to agent 32 * @enabled: State of the SCMI clock 33 */ 34 struct stm32_scmi_clk { 35 unsigned long clock_id; 36 const char *name; 37 bool enabled; 38 }; 39 40 /* 41 * struct stm32_scmi_rd - Data for the exposed reset controller 42 * @reset_id: Reset identifier in RCC reset driver 43 * @name: Reset string ID exposed to agent 44 */ 45 struct stm32_scmi_rd { 46 unsigned long reset_id; 47 const char *name; 48 }; 49 50 enum voltd_device { 51 VOLTD_PWR, 52 }; 53 54 /* 55 * struct stm32_scmi_voltd - Data for the exposed voltage domains 56 * @name: Power regulator string ID exposed to agent 57 * @priv_id: Internal string ID for the regulator 58 * @priv_dev: Internal ID for the device implementing the regulator 59 */ 60 struct stm32_scmi_voltd { 61 const char *name; 62 const char *priv_id; 63 enum voltd_device priv_dev; 64 65 }; 66 67 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 68 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 69 #define SMT_BUFFER0_BASE SMT_BUFFER_BASE 70 #define SMT_BUFFER1_BASE (SMT_BUFFER_BASE + 0x200) 71 72 #if (SMT_BUFFER1_BASE + SMT_BUF_SLOT_SIZE > \ 73 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 74 #error "SCMI shared memory mismatch" 75 #endif 76 77 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 78 CFG_STM32MP1_SCMI_SHM_SIZE); 79 80 static struct scmi_msg_channel scmi_channel[] = { 81 [0] = { 82 .agent_name = "stm32mp1-agent-0", 83 .shm_addr = { .pa = SMT_BUFFER0_BASE, }, 84 .shm_size = SMT_BUF_SLOT_SIZE, 85 }, 86 [1] = { 87 .agent_name = "stm32mp1-agent-1", 88 .shm_addr = { .pa = SMT_BUFFER1_BASE, }, 89 .shm_size = SMT_BUF_SLOT_SIZE, 90 }, 91 }; 92 93 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int agent_id) 94 { 95 assert(agent_id < ARRAY_SIZE(scmi_channel)); 96 97 return &scmi_channel[agent_id]; 98 } 99 100 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 101 [_scmi_id] = { \ 102 .clock_id = _id, \ 103 .name = _name, \ 104 .enabled = _init_enabled, \ 105 } 106 107 struct stm32_scmi_clk stm32_scmi0_clock[] = { 108 CLOCK_CELL(CK_SCMI0_HSE, CK_HSE, "ck_hse", true), 109 CLOCK_CELL(CK_SCMI0_HSI, CK_HSI, "ck_hsi", true), 110 CLOCK_CELL(CK_SCMI0_CSI, CK_CSI, "ck_csi", true), 111 CLOCK_CELL(CK_SCMI0_LSE, CK_LSE, "ck_lse", true), 112 CLOCK_CELL(CK_SCMI0_LSI, CK_LSI, "ck_lsi", true), 113 CLOCK_CELL(CK_SCMI0_PLL2_Q, PLL2_Q, "pll2_q", true), 114 CLOCK_CELL(CK_SCMI0_PLL2_R, PLL2_R, "pll2_r", true), 115 CLOCK_CELL(CK_SCMI0_MPU, CK_MPU, "ck_mpu", true), 116 CLOCK_CELL(CK_SCMI0_AXI, CK_AXI, "ck_axi", true), 117 CLOCK_CELL(CK_SCMI0_BSEC, BSEC, "bsec", true), 118 CLOCK_CELL(CK_SCMI0_CRYP1, CRYP1, "cryp1", false), 119 CLOCK_CELL(CK_SCMI0_GPIOZ, GPIOZ, "gpioz", false), 120 CLOCK_CELL(CK_SCMI0_HASH1, HASH1, "hash1", false), 121 CLOCK_CELL(CK_SCMI0_I2C4, I2C4_K, "i2c4_k", false), 122 CLOCK_CELL(CK_SCMI0_I2C6, I2C6_K, "i2c6_k", false), 123 CLOCK_CELL(CK_SCMI0_IWDG1, IWDG1, "iwdg1", false), 124 CLOCK_CELL(CK_SCMI0_RNG1, RNG1_K, "rng1_k", true), 125 CLOCK_CELL(CK_SCMI0_RTC, RTC, "ck_rtc", true), 126 CLOCK_CELL(CK_SCMI0_RTCAPB, RTCAPB, "rtcapb", true), 127 CLOCK_CELL(CK_SCMI0_SPI6, SPI6_K, "spi6_k", false), 128 CLOCK_CELL(CK_SCMI0_USART1, USART1_K, "usart1_k", false), 129 }; 130 131 struct stm32_scmi_clk stm32_scmi1_clock[] = { 132 CLOCK_CELL(CK_SCMI1_PLL3_Q, PLL3_Q, "pll3_q", true), 133 CLOCK_CELL(CK_SCMI1_PLL3_R, PLL3_R, "pll3_r", true), 134 CLOCK_CELL(CK_SCMI1_MCU, CK_MCU, "ck_mcu", false), 135 }; 136 137 #define RESET_CELL(_scmi_id, _id, _name) \ 138 [_scmi_id] = { \ 139 .reset_id = _id, \ 140 .name = _name, \ 141 } 142 143 struct stm32_scmi_rd stm32_scmi0_reset_domain[] = { 144 RESET_CELL(RST_SCMI0_SPI6, SPI6_R, "spi6"), 145 RESET_CELL(RST_SCMI0_I2C4, I2C4_R, "i2c4"), 146 RESET_CELL(RST_SCMI0_I2C6, I2C6_R, "i2c6"), 147 RESET_CELL(RST_SCMI0_USART1, USART1_R, "usart1"), 148 RESET_CELL(RST_SCMI0_STGEN, STGEN_R, "stgen"), 149 RESET_CELL(RST_SCMI0_GPIOZ, GPIOZ_R, "gpioz"), 150 RESET_CELL(RST_SCMI0_CRYP1, CRYP1_R, "cryp1"), 151 RESET_CELL(RST_SCMI0_HASH1, HASH1_R, "hash1"), 152 RESET_CELL(RST_SCMI0_RNG1, RNG1_R, "rng1"), 153 RESET_CELL(RST_SCMI0_MDMA, MDMA_R, "mdma"), 154 RESET_CELL(RST_SCMI0_MCU, MCU_R, "mcu"), 155 RESET_CELL(RST_SCMI0_MCU_HOLD_BOOT, MCU_HOLD_BOOT_R, "mcu_hold_boot"), 156 }; 157 158 #define VOLTD_CELL(_scmi_id, _dev_id, _priv_id, _name) \ 159 [_scmi_id] = { \ 160 .priv_id = (_priv_id), \ 161 .priv_dev = (_dev_id), \ 162 .name = (_name), \ 163 } 164 165 struct scmi_agent_resources { 166 struct stm32_scmi_clk *clock; 167 size_t clock_count; 168 struct stm32_scmi_rd *rd; 169 size_t rd_count; 170 struct stm32_scmi_pd *pd; 171 size_t pd_count; 172 struct stm32_scmi_perfs *perfs; 173 size_t perfs_count; 174 struct stm32_scmi_voltd *voltd; 175 size_t voltd_count; 176 }; 177 178 const struct scmi_agent_resources agent_resources[] = { 179 [0] = { 180 .clock = stm32_scmi0_clock, 181 .clock_count = ARRAY_SIZE(stm32_scmi0_clock), 182 .rd = stm32_scmi0_reset_domain, 183 .rd_count = ARRAY_SIZE(stm32_scmi0_reset_domain), 184 }, 185 [1] = { 186 .clock = stm32_scmi1_clock, 187 .clock_count = ARRAY_SIZE(stm32_scmi1_clock), 188 }, 189 }; 190 191 static const struct scmi_agent_resources *find_resource(unsigned int agent_id) 192 { 193 assert(agent_id < ARRAY_SIZE(agent_resources)); 194 195 return &agent_resources[agent_id]; 196 } 197 198 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 199 { 200 unsigned int n = 0; 201 unsigned int count = 0; 202 const size_t agent_count = ARRAY_SIZE(agent_resources); 203 204 for (n = 0; n < agent_count; n++) 205 if (agent_resources[n].clock_count) 206 break; 207 if (n < agent_count) 208 count++; 209 210 for (n = 0; n < agent_count; n++) 211 if (agent_resources[n].rd_count) 212 break; 213 if (n < agent_count) 214 count++; 215 216 for (n = 0; n < agent_count; n++) 217 if (agent_resources[n].pd_count) 218 break; 219 if (n < agent_count) 220 count++; 221 222 for (n = 0; n < agent_count; n++) 223 if (agent_resources[n].perfs_count) 224 break; 225 if (n < agent_count) 226 count++; 227 228 for (n = 0; n < agent_count; n++) 229 if (agent_resources[n].voltd_count) 230 break; 231 if (n < agent_count) 232 count++; 233 234 return count; 235 } 236 237 static const char vendor[] = "ST"; 238 static const char sub_vendor[] = ""; 239 240 const char *plat_scmi_vendor_name(void) 241 { 242 return vendor; 243 } 244 245 const char *plat_scmi_sub_vendor_name(void) 246 { 247 return sub_vendor; 248 } 249 250 /* Currently supporting Clocks and Reset Domains */ 251 static const uint8_t plat_protocol_list[] = { 252 SCMI_PROTOCOL_ID_CLOCK, 253 SCMI_PROTOCOL_ID_RESET_DOMAIN, 254 SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, 255 0 /* Null termination */ 256 }; 257 258 size_t plat_scmi_protocol_count(void) 259 { 260 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 261 262 assert(count == plat_scmi_protocol_count_paranoid()); 263 264 return count; 265 } 266 267 const uint8_t *plat_scmi_protocol_list(unsigned int agent_id __unused) 268 { 269 assert(plat_scmi_protocol_count_paranoid() == 270 (ARRAY_SIZE(plat_protocol_list) - 1)); 271 272 return plat_protocol_list; 273 } 274 275 /* 276 * Platform SCMI clocks 277 */ 278 static struct stm32_scmi_clk *find_clock(unsigned int agent_id, 279 unsigned int scmi_id) 280 { 281 const struct scmi_agent_resources *resource = find_resource(agent_id); 282 size_t n = 0; 283 284 if (resource) { 285 for (n = 0; n < resource->clock_count; n++) 286 if (n == scmi_id) 287 return &resource->clock[n]; 288 } 289 290 return NULL; 291 } 292 293 size_t plat_scmi_clock_count(unsigned int agent_id) 294 { 295 const struct scmi_agent_resources *resource = find_resource(agent_id); 296 297 if (!resource) 298 return 0; 299 300 return resource->clock_count; 301 } 302 303 const char *plat_scmi_clock_get_name(unsigned int agent_id, 304 unsigned int scmi_id) 305 { 306 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 307 308 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 309 return NULL; 310 311 return clock->name; 312 } 313 314 int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id, 315 size_t start_index, unsigned long *array, 316 size_t *nb_elts) 317 { 318 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 319 320 if (!clock) 321 return SCMI_NOT_FOUND; 322 323 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 324 return SCMI_DENIED; 325 326 /* Exposed clocks are currently fixed rate clocks */ 327 if (start_index) 328 return SCMI_INVALID_PARAMETERS; 329 330 if (!array) 331 *nb_elts = 1; 332 else if (*nb_elts == 1) 333 *array = stm32_clock_get_rate(clock->clock_id); 334 else 335 return SCMI_GENERIC_ERROR; 336 337 return SCMI_SUCCESS; 338 } 339 340 unsigned long plat_scmi_clock_get_rate(unsigned int agent_id, 341 unsigned int scmi_id) 342 { 343 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 344 345 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 346 return 0; 347 348 return stm32_clock_get_rate(clock->clock_id); 349 } 350 351 int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id) 352 { 353 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 354 355 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 356 return 0; 357 358 return (int32_t)clock->enabled; 359 } 360 361 int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id, 362 bool enable_not_disable) 363 { 364 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 365 366 if (!clock) 367 return SCMI_NOT_FOUND; 368 369 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 370 return SCMI_DENIED; 371 372 if (enable_not_disable) { 373 if (!clock->enabled) { 374 DMSG("SCMI clock %u enable", scmi_id); 375 stm32_clock_enable(clock->clock_id); 376 clock->enabled = true; 377 } 378 } else { 379 if (clock->enabled) { 380 DMSG("SCMI clock %u disable", scmi_id); 381 stm32_clock_disable(clock->clock_id); 382 clock->enabled = false; 383 } 384 } 385 386 return SCMI_SUCCESS; 387 } 388 389 /* 390 * Platform SCMI reset domains 391 */ 392 static struct stm32_scmi_rd *find_rd(unsigned int agent_id, 393 unsigned int scmi_id) 394 { 395 const struct scmi_agent_resources *resource = find_resource(agent_id); 396 size_t n = 0; 397 398 if (resource) { 399 for (n = 0; n < resource->rd_count; n++) 400 if (n == scmi_id) 401 return &resource->rd[n]; 402 } 403 404 return NULL; 405 } 406 407 const char *plat_scmi_rd_get_name(unsigned int agent_id, unsigned int scmi_id) 408 { 409 const struct stm32_scmi_rd *rd = find_rd(agent_id, scmi_id); 410 411 if (!rd) 412 return NULL; 413 414 return rd->name; 415 } 416 417 size_t plat_scmi_rd_count(unsigned int agent_id) 418 { 419 const struct scmi_agent_resources *resource = find_resource(agent_id); 420 421 if (!resource) 422 return 0; 423 424 return resource->rd_count; 425 } 426 427 int32_t plat_scmi_rd_autonomous(unsigned int agent_id, unsigned int scmi_id, 428 uint32_t state) 429 { 430 const struct stm32_scmi_rd *rd = find_rd(agent_id, scmi_id); 431 432 if (!rd) 433 return SCMI_NOT_FOUND; 434 435 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 436 return SCMI_DENIED; 437 438 if (rd->reset_id == MCU_HOLD_BOOT_R) 439 return SCMI_NOT_SUPPORTED; 440 441 /* Supports only reset with context loss */ 442 if (state) 443 return SCMI_NOT_SUPPORTED; 444 445 DMSG("SCMI reset %u cycle", scmi_id); 446 447 if (stm32_reset_assert(rd->reset_id, TIMEOUT_US_1MS)) 448 return SCMI_HARDWARE_ERROR; 449 450 if (stm32_reset_deassert(rd->reset_id, TIMEOUT_US_1MS)) 451 return SCMI_HARDWARE_ERROR; 452 453 return SCMI_SUCCESS; 454 } 455 456 int32_t plat_scmi_rd_set_state(unsigned int agent_id, unsigned int scmi_id, 457 bool assert_not_deassert) 458 { 459 const struct stm32_scmi_rd *rd = find_rd(agent_id, scmi_id); 460 461 if (!rd) 462 return SCMI_NOT_FOUND; 463 464 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 465 return SCMI_DENIED; 466 467 if (rd->reset_id == MCU_HOLD_BOOT_R) { 468 DMSG("SCMI MCU hold boot %s", 469 assert_not_deassert ? "set" : "release"); 470 stm32_reset_assert_deassert_mcu(assert_not_deassert); 471 return SCMI_SUCCESS; 472 } 473 474 if (assert_not_deassert) { 475 DMSG("SCMI reset %u set", scmi_id); 476 stm32_reset_set(rd->reset_id); 477 } else { 478 DMSG("SCMI reset %u release", scmi_id); 479 stm32_reset_release(rd->reset_id); 480 } 481 482 return SCMI_SUCCESS; 483 } 484 485 /* 486 * Platform SCMI voltage domains 487 */ 488 static struct stm32_scmi_voltd *find_voltd(unsigned int agent_id, 489 unsigned int scmi_id) 490 { 491 const struct scmi_agent_resources *resource = find_resource(agent_id); 492 size_t n = 0; 493 494 if (resource) { 495 for (n = 0; n < resource->voltd_count; n++) 496 if (n == scmi_id) 497 return &resource->voltd[n]; 498 } 499 500 return NULL; 501 } 502 503 size_t plat_scmi_voltd_count(unsigned int agent_id) 504 { 505 const struct scmi_agent_resources *resource = find_resource(agent_id); 506 507 if (!resource) 508 return 0; 509 510 return resource->voltd_count; 511 } 512 513 const char *plat_scmi_voltd_get_name(unsigned int agent_id, 514 unsigned int scmi_id) 515 { 516 struct stm32_scmi_voltd *voltd = find_voltd(agent_id, scmi_id); 517 518 /* Currently non-secure is allowed to access all PWR regulators */ 519 if (!voltd) 520 return NULL; 521 522 return voltd->name; 523 } 524 525 int32_t plat_scmi_voltd_levels_array(unsigned int agent_id, 526 unsigned int scmi_id, 527 size_t start_index __unused, 528 long *levels __unused, 529 size_t *nb_elts __unused) 530 531 { 532 struct stm32_scmi_voltd *voltd = find_voltd(agent_id, scmi_id); 533 534 if (!voltd) 535 return SCMI_NOT_FOUND; 536 537 switch (voltd->priv_dev) { 538 default: 539 return SCMI_GENERIC_ERROR; 540 } 541 } 542 543 long plat_scmi_voltd_get_level(unsigned int agent_id, unsigned int scmi_id) 544 { 545 struct stm32_scmi_voltd *voltd = find_voltd(agent_id, scmi_id); 546 547 if (!voltd) 548 return 0; 549 550 switch (voltd->priv_dev) { 551 default: 552 panic(); 553 } 554 } 555 556 int32_t plat_scmi_voltd_set_level(unsigned int agent_id, unsigned int scmi_id, 557 long level __unused) 558 { 559 struct stm32_scmi_voltd *voltd = find_voltd(agent_id, scmi_id); 560 561 if (!voltd) 562 return SCMI_NOT_FOUND; 563 564 switch (voltd->priv_dev) { 565 default: 566 return SCMI_GENERIC_ERROR; 567 } 568 } 569 570 int32_t plat_scmi_voltd_get_config(unsigned int agent_id, unsigned int scmi_id, 571 uint32_t *config __unused) 572 { 573 struct stm32_scmi_voltd *voltd = find_voltd(agent_id, scmi_id); 574 575 if (!voltd) 576 return SCMI_NOT_FOUND; 577 578 switch (voltd->priv_dev) { 579 default: 580 return SCMI_GENERIC_ERROR; 581 } 582 583 return SCMI_SUCCESS; 584 } 585 586 int32_t plat_scmi_voltd_set_config(unsigned int agent_id, unsigned int scmi_id, 587 uint32_t config __unused) 588 { 589 struct stm32_scmi_voltd *voltd = find_voltd(agent_id, scmi_id); 590 int32_t rc = SCMI_SUCCESS; 591 592 if (!voltd) 593 return SCMI_NOT_FOUND; 594 595 switch (voltd->priv_dev) { 596 default: 597 return SCMI_GENERIC_ERROR; 598 } 599 600 return rc; 601 } 602 603 /* 604 * Initialize platform SCMI resources 605 */ 606 static TEE_Result stm32mp1_init_scmi_server(void) 607 { 608 size_t i = 0; 609 size_t j = 0; 610 611 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 612 struct scmi_msg_channel *chan = &scmi_channel[i]; 613 614 /* Enforce non-secure shm mapped as device memory */ 615 chan->shm_addr.va = (vaddr_t)phys_to_virt(chan->shm_addr.pa, 616 MEM_AREA_IO_NSEC); 617 assert(chan->shm_addr.va); 618 619 scmi_smt_init_agent_channel(chan); 620 } 621 622 for (i = 0; i < ARRAY_SIZE(agent_resources); i++) { 623 const struct scmi_agent_resources *res = &agent_resources[i]; 624 625 for (j = 0; j < res->clock_count; j++) { 626 struct stm32_scmi_clk *clk = &res->clock[j]; 627 628 if (!clk->name || 629 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 630 panic("SCMI clock name invalid"); 631 632 /* Sync SCMI clocks with their targeted initial state */ 633 if (clk->enabled && 634 stm32mp_nsec_can_access_clock(clk->clock_id)) 635 stm32_clock_enable(clk->clock_id); 636 } 637 638 for (j = 0; j < res->rd_count; j++) { 639 struct stm32_scmi_rd *rd = &res->rd[j]; 640 641 if (!rd->name || 642 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 643 panic("SCMI reset domain name invalid"); 644 } 645 646 for (j = 0; j < res->voltd_count; j++) { 647 struct stm32_scmi_voltd *voltd = &res->voltd[j]; 648 649 if (!voltd->name || 650 strlen(voltd->name) >= SCMI_VOLTD_NAME_SIZE) 651 panic("SCMI voltage domain name invalid"); 652 } 653 } 654 655 return TEE_SUCCESS; 656 } 657 658 driver_init_late(stm32mp1_init_scmi_server); 659