1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019-2022, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <confine_array_index.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/rstctrl.h> 11 #include <drivers/scmi-msg.h> 12 #include <drivers/scmi.h> 13 #include <drivers/stm32mp1_pmic.h> 14 #include <drivers/stm32mp1_pwr.h> 15 #include <drivers/stpmic1.h> 16 #include <drivers/stpmic1_regulator.h> 17 #include <drivers/stm32mp_dt_bindings.h> 18 #include <initcall.h> 19 #include <mm/core_memprot.h> 20 #include <mm/core_mmu.h> 21 #include <platform_config.h> 22 #include <stdint.h> 23 #include <speculation_barrier.h> 24 #include <stm32_util.h> 25 #include <string.h> 26 #include <tee_api_defines.h> 27 #include <util.h> 28 29 #define TIMEOUT_US_1MS 1000 30 31 #define SCMI_CLOCK_NAME_SIZE 16 32 #define SCMI_RD_NAME_SIZE 16 33 #define SCMI_VOLTD_NAME_SIZE 16 34 35 /* 36 * struct stm32_scmi_clk - Data for the exposed clock 37 * @clock_id: Clock identifier in RCC clock driver 38 * @name: Clock string ID exposed to channel 39 * @enabled: State of the SCMI clock 40 */ 41 struct stm32_scmi_clk { 42 unsigned long clock_id; 43 struct clk *clk; 44 const char *name; 45 bool enabled; 46 }; 47 48 /* 49 * struct stm32_scmi_rd - Data for the exposed reset controller 50 * @reset_id: Reset identifier in RCC reset driver 51 * @name: Reset string ID exposed to channel 52 * @rstctrl: Reset controller device 53 */ 54 struct stm32_scmi_rd { 55 unsigned long reset_id; 56 const char *name; 57 struct rstctrl *rstctrl; 58 }; 59 60 enum voltd_device { 61 VOLTD_PWR, 62 VOLTD_PMIC, 63 }; 64 65 /* 66 * struct stm32_scmi_voltd - Data for the exposed voltage domains 67 * @name: Power regulator string ID exposed to channel 68 * @priv_id: Internal string ID for the regulator 69 * @priv_dev: Internal ID for the device implementing the regulator 70 */ 71 struct stm32_scmi_voltd { 72 const char *name; 73 const char *priv_id; 74 enum voltd_device priv_dev; 75 76 }; 77 78 #if CFG_STM32MP1_SCMI_SHM_BASE 79 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 80 CFG_STM32MP1_SCMI_SHM_SIZE); 81 82 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 83 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 84 85 #if (SMT_BUFFER_BASE + SMT_BUF_SLOT_SIZE > \ 86 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 87 #error "SCMI shared memory mismatch" 88 #endif 89 #endif /*CFG_STM32MP1_SCMI_SHM_BASE*/ 90 91 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 92 [(_scmi_id)] = { \ 93 .clock_id = (_id), \ 94 .name = (_name), \ 95 .enabled = (_init_enabled), \ 96 } 97 98 #define RESET_CELL(_scmi_id, _id, _name) \ 99 [(_scmi_id)] = { \ 100 .reset_id = (_id), \ 101 .name = (_name), \ 102 } 103 104 #define VOLTD_CELL(_scmi_id, _dev_id, _priv_id, _name) \ 105 [(_scmi_id)] = { \ 106 .priv_id = (_priv_id), \ 107 .priv_dev = (_dev_id), \ 108 .name = (_name), \ 109 } 110 111 #ifdef CFG_STM32MP13 112 static struct stm32_scmi_clk stm32_scmi_clock[] = { 113 CLOCK_CELL(CK_SCMI_HSE, CK_HSE, "ck_hse", true), 114 CLOCK_CELL(CK_SCMI_HSI, CK_HSI, "ck_hsi", true), 115 CLOCK_CELL(CK_SCMI_CSI, CK_CSI, "ck_csi", true), 116 CLOCK_CELL(CK_SCMI_LSE, CK_LSE, "ck_lse", true), 117 CLOCK_CELL(CK_SCMI_LSI, CK_LSI, "ck_lsi", true), 118 CLOCK_CELL(CK_SCMI_HSE_DIV2, CK_HSE_DIV2, "clk-hse-div2", true), 119 CLOCK_CELL(CK_SCMI_PLL2_Q, PLL2_Q, "pll2_q", true), 120 CLOCK_CELL(CK_SCMI_PLL2_R, PLL2_R, "pll2_r", true), 121 CLOCK_CELL(CK_SCMI_PLL3_P, PLL3_P, "pll3_p", true), 122 CLOCK_CELL(CK_SCMI_PLL3_Q, PLL3_Q, "pll3_q", true), 123 CLOCK_CELL(CK_SCMI_PLL3_R, PLL3_R, "pll3_r", true), 124 CLOCK_CELL(CK_SCMI_PLL4_P, PLL4_P, "pll4_p", true), 125 CLOCK_CELL(CK_SCMI_PLL4_Q, PLL4_Q, "pll4_q", true), 126 CLOCK_CELL(CK_SCMI_PLL4_R, PLL4_R, "pll4_r", true), 127 CLOCK_CELL(CK_SCMI_MPU, CK_MPU, "ck_mpu", true), 128 CLOCK_CELL(CK_SCMI_AXI, CK_AXI, "ck_axi", true), 129 CLOCK_CELL(CK_SCMI_MLAHB, CK_MLAHB, "ck_mlahb", true), 130 CLOCK_CELL(CK_SCMI_CKPER, CK_PER, "ck_per", true), 131 CLOCK_CELL(CK_SCMI_PCLK1, PCLK1, "pclk1", true), 132 CLOCK_CELL(CK_SCMI_PCLK2, PCLK2, "pclk2", true), 133 CLOCK_CELL(CK_SCMI_PCLK3, PCLK3, "pclk3", true), 134 CLOCK_CELL(CK_SCMI_PCLK4, PCLK4, "pclk4", true), 135 CLOCK_CELL(CK_SCMI_PCLK5, PCLK5, "pclk5", true), 136 CLOCK_CELL(CK_SCMI_PCLK6, PCLK6, "pclk6", true), 137 CLOCK_CELL(CK_SCMI_CKTIMG1, CK_TIMG1, "timg1_ck", true), 138 CLOCK_CELL(CK_SCMI_CKTIMG2, CK_TIMG2, "timg2_ck", true), 139 CLOCK_CELL(CK_SCMI_CKTIMG3, CK_TIMG3, "timg3_ck", true), 140 CLOCK_CELL(CK_SCMI_RTC, RTC, "ck_rtc", true), 141 CLOCK_CELL(CK_SCMI_RTCAPB, RTCAPB, "rtcapb", true), 142 CLOCK_CELL(CK_SCMI_BSEC, BSEC, "bsec", true), 143 }; 144 #endif 145 146 #ifdef CFG_STM32MP15 147 static struct stm32_scmi_clk stm32_scmi_clock[] = { 148 CLOCK_CELL(CK_SCMI_HSE, CK_HSE, "ck_hse", true), 149 CLOCK_CELL(CK_SCMI_HSI, CK_HSI, "ck_hsi", true), 150 CLOCK_CELL(CK_SCMI_CSI, CK_CSI, "ck_csi", true), 151 CLOCK_CELL(CK_SCMI_LSE, CK_LSE, "ck_lse", true), 152 CLOCK_CELL(CK_SCMI_LSI, CK_LSI, "ck_lsi", true), 153 CLOCK_CELL(CK_SCMI_PLL2_Q, PLL2_Q, "pll2_q", true), 154 CLOCK_CELL(CK_SCMI_PLL2_R, PLL2_R, "pll2_r", true), 155 CLOCK_CELL(CK_SCMI_MPU, CK_MPU, "ck_mpu", true), 156 CLOCK_CELL(CK_SCMI_AXI, CK_AXI, "ck_axi", true), 157 CLOCK_CELL(CK_SCMI_BSEC, BSEC, "bsec", true), 158 CLOCK_CELL(CK_SCMI_CRYP1, CRYP1, "cryp1", false), 159 CLOCK_CELL(CK_SCMI_GPIOZ, GPIOZ, "gpioz", false), 160 CLOCK_CELL(CK_SCMI_HASH1, HASH1, "hash1", false), 161 CLOCK_CELL(CK_SCMI_I2C4, I2C4_K, "i2c4_k", false), 162 CLOCK_CELL(CK_SCMI_I2C6, I2C6_K, "i2c6_k", false), 163 CLOCK_CELL(CK_SCMI_IWDG1, IWDG1, "iwdg1", false), 164 CLOCK_CELL(CK_SCMI_RNG1, RNG1_K, "rng1_k", true), 165 CLOCK_CELL(CK_SCMI_RTC, RTC, "ck_rtc", true), 166 CLOCK_CELL(CK_SCMI_RTCAPB, RTCAPB, "rtcapb", true), 167 CLOCK_CELL(CK_SCMI_SPI6, SPI6_K, "spi6_k", false), 168 CLOCK_CELL(CK_SCMI_USART1, USART1_K, "usart1_k", false), 169 }; 170 #endif 171 172 #ifdef CFG_STM32MP13 173 static struct stm32_scmi_rd stm32_scmi_reset_domain[] = { 174 RESET_CELL(RST_SCMI_LTDC, LTDC_R, "ltdc"), 175 RESET_CELL(RST_SCMI_MDMA, MDMA_R, "mdma"), 176 }; 177 #endif 178 179 #ifdef CFG_STM32MP15 180 static struct stm32_scmi_rd stm32_scmi_reset_domain[] = { 181 RESET_CELL(RST_SCMI_SPI6, SPI6_R, "spi6"), 182 RESET_CELL(RST_SCMI_I2C4, I2C4_R, "i2c4"), 183 RESET_CELL(RST_SCMI_I2C6, I2C6_R, "i2c6"), 184 RESET_CELL(RST_SCMI_USART1, USART1_R, "usart1"), 185 RESET_CELL(RST_SCMI_STGEN, STGEN_R, "stgen"), 186 RESET_CELL(RST_SCMI_GPIOZ, GPIOZ_R, "gpioz"), 187 RESET_CELL(RST_SCMI_CRYP1, CRYP1_R, "cryp1"), 188 RESET_CELL(RST_SCMI_HASH1, HASH1_R, "hash1"), 189 RESET_CELL(RST_SCMI_RNG1, RNG1_R, "rng1"), 190 RESET_CELL(RST_SCMI_MDMA, MDMA_R, "mdma"), 191 RESET_CELL(RST_SCMI_MCU, MCU_R, "mcu"), 192 RESET_CELL(RST_SCMI_MCU_HOLD_BOOT, MCU_HOLD_BOOT_R, "mcu_hold_boot"), 193 }; 194 #endif 195 196 #define PWR_REG11_NAME_ID "0" 197 #define PWR_REG18_NAME_ID "1" 198 #define PWR_USB33_NAME_ID "2" 199 #define PWR_SDMMC1_IO_NAME_ID "3" 200 #define PWR_SDMMC2_IO_NAME_ID "4" 201 #define PWR_VREFBUF_NAME_ID "5" 202 203 #ifdef CFG_STM32MP13 204 struct stm32_scmi_voltd scmi_voltage_domain[] = { 205 VOLTD_CELL(VOLTD_SCMI_REG11, VOLTD_PWR, PWR_REG11_NAME_ID, "reg11"), 206 VOLTD_CELL(VOLTD_SCMI_REG18, VOLTD_PWR, PWR_REG18_NAME_ID, "reg18"), 207 VOLTD_CELL(VOLTD_SCMI_USB33, VOLTD_PWR, PWR_USB33_NAME_ID, "usb33"), 208 VOLTD_CELL(VOLTD_SCMI_SDMMC1_IO, VOLTD_PWR, PWR_SDMMC1_IO_NAME_ID, 209 "sdmmc1"), 210 VOLTD_CELL(VOLTD_SCMI_SDMMC2_IO, VOLTD_PWR, PWR_SDMMC2_IO_NAME_ID, 211 "sdmmc2"), 212 VOLTD_CELL(VOLTD_SCMI_VREFBUF, VOLTD_PWR, PWR_VREFBUF_NAME_ID, 213 "vrefbuf"), 214 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK1, VOLTD_PMIC, "buck1", "buck1"), 215 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK2, VOLTD_PMIC, "buck2", "buck2"), 216 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK3, VOLTD_PMIC, "buck3", "buck3"), 217 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK4, VOLTD_PMIC, "buck4", "buck4"), 218 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO1, VOLTD_PMIC, "ldo1", "ldo1"), 219 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO2, VOLTD_PMIC, "ldo2", "ldo2"), 220 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO3, VOLTD_PMIC, "ldo3", "ldo3"), 221 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO4, VOLTD_PMIC, "ldo4", "ldo4"), 222 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO5, VOLTD_PMIC, "ldo5", "ldo5"), 223 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO6, VOLTD_PMIC, "ldo6", "ldo6"), 224 VOLTD_CELL(VOLTD_SCMI_STPMIC1_VREFDDR, VOLTD_PMIC, "vref_ddr", 225 "vref_ddr"), 226 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BOOST, VOLTD_PMIC, "boost", "bst_out"), 227 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW1, VOLTD_PMIC, "pwr_sw1", 228 "pwr_sw1"), 229 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW2, VOLTD_PMIC, "pwr_sw2", 230 "pwr_sw2"), 231 }; 232 #endif 233 234 #ifdef CFG_STM32MP15 235 struct stm32_scmi_voltd scmi_voltage_domain[] = { 236 VOLTD_CELL(VOLTD_SCMI_REG11, VOLTD_PWR, PWR_REG11_NAME_ID, "reg11"), 237 VOLTD_CELL(VOLTD_SCMI_REG18, VOLTD_PWR, PWR_REG18_NAME_ID, "reg18"), 238 VOLTD_CELL(VOLTD_SCMI_USB33, VOLTD_PWR, PWR_USB33_NAME_ID, "usb33"), 239 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK1, VOLTD_PMIC, "buck1", "vddcore"), 240 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK2, VOLTD_PMIC, "buck2", "vdd_ddr"), 241 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK3, VOLTD_PMIC, "buck3", "vdd"), 242 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK4, VOLTD_PMIC, "buck4", "v3v3"), 243 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO1, VOLTD_PMIC, "ldo1", "v1v8_audio"), 244 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO2, VOLTD_PMIC, "ldo2", "v3v3_hdmi"), 245 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO3, VOLTD_PMIC, "ldo3", "vtt_ddr"), 246 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO4, VOLTD_PMIC, "ldo4", "vdd_usb"), 247 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO5, VOLTD_PMIC, "ldo5", "vdda"), 248 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO6, VOLTD_PMIC, "ldo6", "v1v2_hdmi"), 249 VOLTD_CELL(VOLTD_SCMI_STPMIC1_VREFDDR, VOLTD_PMIC, "vref_ddr", 250 "vref_ddr"), 251 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BOOST, VOLTD_PMIC, "boost", "bst_out"), 252 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW1, VOLTD_PMIC, "pwr_sw1", 253 "vbus_otg"), 254 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW2, VOLTD_PMIC, "pwr_sw2", 255 "vbus_sw"), 256 }; 257 #endif 258 259 struct channel_resources { 260 struct scmi_msg_channel *channel; 261 struct stm32_scmi_clk *clock; 262 size_t clock_count; 263 struct stm32_scmi_rd *rd; 264 size_t rd_count; 265 struct stm32_scmi_voltd *voltd; 266 size_t voltd_count; 267 }; 268 269 static const struct channel_resources scmi_channel[] = { 270 [0] = { 271 .channel = &(struct scmi_msg_channel){ 272 #ifdef SMT_BUFFER_BASE 273 .shm_addr = { .pa = SMT_BUFFER_BASE }, 274 .shm_size = SMT_BUF_SLOT_SIZE, 275 #endif 276 }, 277 .clock = stm32_scmi_clock, 278 .clock_count = ARRAY_SIZE(stm32_scmi_clock), 279 .rd = stm32_scmi_reset_domain, 280 .rd_count = ARRAY_SIZE(stm32_scmi_reset_domain), 281 .voltd = scmi_voltage_domain, 282 .voltd_count = ARRAY_SIZE(scmi_voltage_domain), 283 }, 284 }; 285 286 static const struct channel_resources *find_resource(unsigned int channel_id) 287 { 288 assert(channel_id < ARRAY_SIZE(scmi_channel)); 289 290 return scmi_channel + channel_id; 291 } 292 293 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int channel_id) 294 { 295 const size_t max_id = ARRAY_SIZE(scmi_channel); 296 unsigned int confined_id = confine_array_index(channel_id, max_id); 297 298 if (channel_id >= max_id) 299 return NULL; 300 301 return find_resource(confined_id)->channel; 302 } 303 304 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 305 { 306 unsigned int n = 0; 307 unsigned int count = 0; 308 const size_t channel_count = ARRAY_SIZE(scmi_channel); 309 310 for (n = 0; n < channel_count; n++) 311 if (scmi_channel[n].clock_count) 312 break; 313 if (n < channel_count) 314 count++; 315 316 for (n = 0; n < channel_count; n++) 317 if (scmi_channel[n].rd_count) 318 break; 319 if (n < channel_count) 320 count++; 321 322 for (n = 0; n < channel_count; n++) 323 if (scmi_channel[n].voltd_count) 324 break; 325 if (n < channel_count) 326 count++; 327 328 return count; 329 } 330 331 static const char vendor[] = "ST"; 332 static const char sub_vendor[] = ""; 333 334 const char *plat_scmi_vendor_name(void) 335 { 336 return vendor; 337 } 338 339 const char *plat_scmi_sub_vendor_name(void) 340 { 341 return sub_vendor; 342 } 343 344 /* Currently supporting Clocks and Reset Domains */ 345 static const uint8_t plat_protocol_list[] = { 346 SCMI_PROTOCOL_ID_CLOCK, 347 SCMI_PROTOCOL_ID_RESET_DOMAIN, 348 SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, 349 0 /* Null termination */ 350 }; 351 352 size_t plat_scmi_protocol_count(void) 353 { 354 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 355 356 assert(count == plat_scmi_protocol_count_paranoid()); 357 358 return count; 359 } 360 361 const uint8_t *plat_scmi_protocol_list(unsigned int channel_id __unused) 362 { 363 assert(plat_scmi_protocol_count_paranoid() == 364 (ARRAY_SIZE(plat_protocol_list) - 1)); 365 366 return plat_protocol_list; 367 } 368 369 /* 370 * Platform SCMI clocks 371 */ 372 static struct stm32_scmi_clk *find_clock(unsigned int channel_id, 373 unsigned int scmi_id) 374 { 375 const struct channel_resources *resource = find_resource(channel_id); 376 size_t n = 0; 377 378 if (resource) { 379 for (n = 0; n < resource->clock_count; n++) 380 if (n == scmi_id) 381 return &resource->clock[n]; 382 } 383 384 return NULL; 385 } 386 387 size_t plat_scmi_clock_count(unsigned int channel_id) 388 { 389 const struct channel_resources *resource = find_resource(channel_id); 390 391 if (!resource) 392 return 0; 393 394 return resource->clock_count; 395 } 396 397 const char *plat_scmi_clock_get_name(unsigned int channel_id, 398 unsigned int scmi_id) 399 { 400 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 401 402 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 403 return NULL; 404 405 return clock->name; 406 } 407 408 int32_t plat_scmi_clock_rates_array(unsigned int channel_id, 409 unsigned int scmi_id, size_t start_index, 410 unsigned long *array, size_t *nb_elts) 411 { 412 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 413 414 if (!clock) 415 return SCMI_NOT_FOUND; 416 417 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 418 return SCMI_DENIED; 419 420 /* Exposed clocks are currently fixed rate clocks */ 421 if (start_index) 422 return SCMI_INVALID_PARAMETERS; 423 424 if (!array) 425 *nb_elts = 1; 426 else if (*nb_elts == 1) 427 *array = clk_get_rate(clock->clk); 428 else 429 return SCMI_GENERIC_ERROR; 430 431 return SCMI_SUCCESS; 432 } 433 434 unsigned long plat_scmi_clock_get_rate(unsigned int channel_id, 435 unsigned int scmi_id) 436 { 437 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 438 439 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 440 return 0; 441 442 return clk_get_rate(clock->clk); 443 } 444 445 int32_t plat_scmi_clock_get_state(unsigned int channel_id, unsigned int scmi_id) 446 { 447 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 448 449 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 450 return 0; 451 452 return (int32_t)clock->enabled; 453 } 454 455 int32_t plat_scmi_clock_set_state(unsigned int channel_id, unsigned int scmi_id, 456 bool enable_not_disable) 457 { 458 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 459 460 if (!clock) 461 return SCMI_NOT_FOUND; 462 463 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 464 return SCMI_DENIED; 465 466 if (enable_not_disable) { 467 if (!clock->enabled) { 468 DMSG("SCMI clock %u enable", scmi_id); 469 clk_enable(clock->clk); 470 clock->enabled = true; 471 } 472 } else { 473 if (clock->enabled) { 474 DMSG("SCMI clock %u disable", scmi_id); 475 clk_disable(clock->clk); 476 clock->enabled = false; 477 } 478 } 479 480 return SCMI_SUCCESS; 481 } 482 483 /* 484 * Platform SCMI reset domains 485 */ 486 static struct stm32_scmi_rd *find_rd(unsigned int channel_id, 487 unsigned int scmi_id) 488 { 489 const struct channel_resources *resource = find_resource(channel_id); 490 size_t n = 0; 491 492 if (resource) { 493 for (n = 0; n < resource->rd_count; n++) 494 if (n == scmi_id) 495 return &resource->rd[n]; 496 } 497 498 return NULL; 499 } 500 501 const char *plat_scmi_rd_get_name(unsigned int channel_id, unsigned int scmi_id) 502 { 503 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 504 505 if (!rd) 506 return NULL; 507 508 return rd->name; 509 } 510 511 size_t plat_scmi_rd_count(unsigned int channel_id) 512 { 513 const struct channel_resources *resource = find_resource(channel_id); 514 515 if (!resource) 516 return 0; 517 518 return resource->rd_count; 519 } 520 521 int32_t plat_scmi_rd_autonomous(unsigned int channel_id, unsigned int scmi_id, 522 uint32_t state) 523 { 524 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 525 526 if (!rd) 527 return SCMI_NOT_FOUND; 528 529 if (!rd->rstctrl || !stm32mp_nsec_can_access_reset(rd->reset_id)) 530 return SCMI_DENIED; 531 assert(rd->rstctrl); 532 533 #ifdef CFG_STM32MP15 534 if (rd->reset_id == MCU_HOLD_BOOT_R) 535 return SCMI_NOT_SUPPORTED; 536 #endif 537 538 /* Supports only reset with context loss */ 539 if (state) 540 return SCMI_NOT_SUPPORTED; 541 542 DMSG("SCMI reset %u cycle", scmi_id); 543 544 if (rstctrl_assert_to(rd->rstctrl, TIMEOUT_US_1MS)) 545 return SCMI_HARDWARE_ERROR; 546 547 if (rstctrl_deassert_to(rd->rstctrl, TIMEOUT_US_1MS)) 548 return SCMI_HARDWARE_ERROR; 549 550 return SCMI_SUCCESS; 551 } 552 553 int32_t plat_scmi_rd_set_state(unsigned int channel_id, unsigned int scmi_id, 554 bool assert_not_deassert) 555 { 556 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 557 TEE_Result res = TEE_ERROR_GENERIC; 558 559 if (!rd) 560 return SCMI_NOT_FOUND; 561 562 if (!rd->rstctrl || !stm32mp_nsec_can_access_reset(rd->reset_id)) 563 return SCMI_DENIED; 564 assert(rd->rstctrl); 565 566 if (assert_not_deassert) { 567 DMSG("SCMI reset %u set", scmi_id); 568 res = rstctrl_assert(rd->rstctrl); 569 } else { 570 DMSG("SCMI reset %u release", scmi_id); 571 res = rstctrl_deassert(rd->rstctrl); 572 } 573 574 if (res) 575 return SCMI_HARDWARE_ERROR; 576 577 return SCMI_SUCCESS; 578 } 579 580 /* 581 * Platform SCMI voltage domains 582 */ 583 static struct stm32_scmi_voltd *find_voltd(unsigned int channel_id, 584 unsigned int scmi_id) 585 { 586 const struct channel_resources *resource = find_resource(channel_id); 587 size_t n = 0; 588 589 if (resource) { 590 for (n = 0; n < resource->voltd_count; n++) 591 if (n == scmi_id) 592 return &resource->voltd[n]; 593 } 594 595 return NULL; 596 } 597 598 size_t plat_scmi_voltd_count(unsigned int channel_id) 599 { 600 const struct channel_resources *resource = find_resource(channel_id); 601 602 if (!resource) 603 return 0; 604 605 return resource->voltd_count; 606 } 607 608 const char *plat_scmi_voltd_get_name(unsigned int channel_id, 609 unsigned int scmi_id) 610 { 611 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 612 613 /* Currently non-secure is allowed to access all PWR regulators */ 614 if (!voltd) 615 return NULL; 616 617 return voltd->name; 618 } 619 620 static enum pwr_regulator pwr_scmi_to_regu_id(struct stm32_scmi_voltd *voltd) 621 { 622 if (!strcmp(voltd->priv_id, PWR_REG11_NAME_ID)) 623 return PWR_REG11; 624 if (!strcmp(voltd->priv_id, PWR_REG18_NAME_ID)) 625 return PWR_REG18; 626 if (!strcmp(voltd->priv_id, PWR_USB33_NAME_ID)) 627 return PWR_USB33; 628 629 panic(); 630 } 631 632 static long pwr_get_level(struct stm32_scmi_voltd *voltd) 633 { 634 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 635 636 return (long)stm32mp1_pwr_regulator_mv(regu_id) * 1000; 637 } 638 639 static int32_t pwr_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 640 { 641 if (level_uv != pwr_get_level(voltd)) 642 return SCMI_INVALID_PARAMETERS; 643 644 return SCMI_SUCCESS; 645 } 646 647 static int32_t pwr_describe_levels(struct stm32_scmi_voltd *voltd, 648 size_t start_index, long *microvolt, 649 size_t *nb_elts) 650 { 651 if (start_index) 652 return SCMI_INVALID_PARAMETERS; 653 654 if (!microvolt) { 655 *nb_elts = 1; 656 return SCMI_SUCCESS; 657 } 658 659 if (*nb_elts < 1) 660 return SCMI_GENERIC_ERROR; 661 662 *nb_elts = 1; 663 *microvolt = pwr_get_level(voltd); 664 665 return SCMI_SUCCESS; 666 } 667 668 static uint32_t pwr_get_state(struct stm32_scmi_voltd *voltd) 669 { 670 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 671 672 if (stm32mp1_pwr_regulator_is_enabled(regu_id)) 673 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 674 675 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 676 } 677 678 static void pwr_set_state(struct stm32_scmi_voltd *voltd, bool enable) 679 { 680 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 681 682 DMSG("%sable PWR %s (was %s)", enable ? "En" : "Dis", voltd->name, 683 stm32mp1_pwr_regulator_is_enabled(regu_id) ? "on" : "off"); 684 685 stm32mp1_pwr_regulator_set_state(regu_id, enable); 686 } 687 688 static int32_t pmic_describe_levels(struct stm32_scmi_voltd *voltd, 689 size_t start_index, long *microvolt, 690 size_t *nb_elts) 691 { 692 const uint16_t *levels = NULL; 693 size_t full_count = 0; 694 size_t out_count = 0; 695 size_t i = 0; 696 697 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 698 return SCMI_DENIED; 699 700 stpmic1_regulator_levels_mv(voltd->priv_id, &levels, &full_count); 701 702 if (!microvolt) { 703 *nb_elts = full_count - start_index; 704 return SCMI_SUCCESS; 705 } 706 707 if (SUB_OVERFLOW(full_count, start_index, &out_count)) 708 return SCMI_GENERIC_ERROR; 709 710 out_count = MIN(out_count, *nb_elts); 711 712 FMSG("%zu levels: start %zu requested %zu output %zu", 713 full_count, start_index, *nb_elts, out_count); 714 715 for (i = 0; i < out_count; i++) 716 microvolt[i] = levels[start_index + i] * 1000; 717 718 *nb_elts = out_count; 719 720 return SCMI_SUCCESS; 721 } 722 723 static long pmic_get_level(struct stm32_scmi_voltd *voltd) 724 { 725 unsigned long level_mv = 0; 726 727 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 728 return 0; 729 730 stm32mp_get_pmic(); 731 level_mv = stpmic1_regulator_voltage_get(voltd->priv_id); 732 stm32mp_put_pmic(); 733 734 return (long)level_mv * 1000; 735 } 736 737 static int32_t pmic_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 738 { 739 int rc = 0; 740 unsigned int level_mv = 0; 741 742 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 743 return SCMI_DENIED; 744 745 if (level_uv < 0 || level_uv > (UINT16_MAX * 1000)) 746 return SCMI_INVALID_PARAMETERS; 747 748 level_mv = (unsigned int)level_uv / 1000; 749 750 DMSG("Set STPMIC1 regulator %s level to %dmV", voltd->name, level_mv); 751 752 stm32mp_get_pmic(); 753 rc = stpmic1_regulator_voltage_set(voltd->priv_id, level_mv); 754 stm32mp_put_pmic(); 755 756 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 757 } 758 759 static uint32_t pmic_get_state(struct stm32_scmi_voltd *voltd) 760 { 761 bool enabled = false; 762 763 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 764 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 765 766 stm32mp_get_pmic(); 767 enabled = stpmic1_is_regulator_enabled(voltd->priv_id); 768 stm32mp_put_pmic(); 769 770 if (enabled) 771 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 772 773 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 774 } 775 776 static int32_t pmic_set_state(struct stm32_scmi_voltd *voltd, bool enable) 777 { 778 int rc = 0; 779 780 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 781 return SCMI_DENIED; 782 783 stm32mp_get_pmic(); 784 785 DMSG("%sable STPMIC1 %s (was %s)", enable ? "En" : "Dis", voltd->name, 786 stpmic1_is_regulator_enabled(voltd->priv_id) ? "on" : "off"); 787 788 if (enable) 789 rc = stpmic1_regulator_enable(voltd->priv_id); 790 else 791 rc = stpmic1_regulator_disable(voltd->priv_id); 792 793 stm32mp_put_pmic(); 794 795 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 796 } 797 798 int32_t plat_scmi_voltd_levels_array(unsigned int channel_id, 799 unsigned int scmi_id, size_t start_index, 800 long *levels, size_t *nb_elts) 801 802 { 803 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 804 805 if (!voltd) 806 return SCMI_NOT_FOUND; 807 808 switch (voltd->priv_dev) { 809 case VOLTD_PWR: 810 return pwr_describe_levels(voltd, start_index, levels, nb_elts); 811 case VOLTD_PMIC: 812 return pmic_describe_levels(voltd, start_index, levels, 813 nb_elts); 814 default: 815 return SCMI_GENERIC_ERROR; 816 } 817 } 818 819 int32_t plat_scmi_voltd_get_level(unsigned int channel_id, unsigned int scmi_id, 820 long *level) 821 { 822 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 823 long voltage = 0; 824 825 if (!voltd) 826 return SCMI_INVALID_PARAMETERS; 827 828 switch (voltd->priv_dev) { 829 case VOLTD_PWR: 830 *level = pwr_get_level(voltd); 831 return SCMI_SUCCESS; 832 case VOLTD_PMIC: 833 voltage = pmic_get_level(voltd); 834 if (voltage > 0) { 835 *level = voltage; 836 return SCMI_SUCCESS; 837 } else { 838 return SCMI_GENERIC_ERROR; 839 } 840 default: 841 panic(); 842 } 843 } 844 845 int32_t plat_scmi_voltd_set_level(unsigned int channel_id, unsigned int scmi_id, 846 long level) 847 { 848 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 849 850 if (!voltd) 851 return SCMI_NOT_FOUND; 852 853 switch (voltd->priv_dev) { 854 case VOLTD_PWR: 855 return pwr_set_level(voltd, level); 856 case VOLTD_PMIC: 857 return pmic_set_level(voltd, level); 858 default: 859 return SCMI_GENERIC_ERROR; 860 } 861 } 862 863 int32_t plat_scmi_voltd_get_config(unsigned int channel_id, 864 unsigned int scmi_id, uint32_t *config) 865 { 866 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 867 868 if (!voltd) 869 return SCMI_NOT_FOUND; 870 871 switch (voltd->priv_dev) { 872 case VOLTD_PWR: 873 *config = pwr_get_state(voltd); 874 break; 875 case VOLTD_PMIC: 876 *config = pmic_get_state(voltd); 877 break; 878 default: 879 return SCMI_GENERIC_ERROR; 880 } 881 882 return SCMI_SUCCESS; 883 } 884 885 int32_t plat_scmi_voltd_set_config(unsigned int channel_id, 886 unsigned int scmi_id, uint32_t config) 887 { 888 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 889 int32_t rc = SCMI_SUCCESS; 890 891 if (!voltd) 892 return SCMI_NOT_FOUND; 893 894 switch (voltd->priv_dev) { 895 case VOLTD_PWR: 896 pwr_set_state(voltd, config); 897 break; 898 case VOLTD_PMIC: 899 rc = pmic_set_state(voltd, config); 900 break; 901 default: 902 return SCMI_GENERIC_ERROR; 903 } 904 905 return rc; 906 } 907 908 /* 909 * Initialize platform SCMI resources 910 */ 911 static TEE_Result stm32mp1_init_scmi_server(void) 912 { 913 size_t i = 0; 914 size_t j = 0; 915 916 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 917 const struct channel_resources *res = scmi_channel + i; 918 struct scmi_msg_channel *chan = res->channel; 919 920 if (chan->shm_addr.pa) { 921 struct io_pa_va *addr = &chan->shm_addr; 922 923 /* Enforce non-secure shm mapped as device memory */ 924 addr->va = (vaddr_t)phys_to_virt(addr->pa, 925 MEM_AREA_IO_NSEC, 926 chan->shm_size); 927 assert(addr->va); 928 929 scmi_smt_init_agent_channel(chan); 930 } 931 932 for (j = 0; j < res->clock_count; j++) { 933 struct stm32_scmi_clk *clk = &res->clock[j]; 934 935 if (!clk->name || 936 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 937 panic("SCMI clock name invalid"); 938 939 clk->clk = stm32mp_rcc_clock_id_to_clk(clk->clock_id); 940 assert(clk->clk); 941 942 /* Sync SCMI clocks with their targeted initial state */ 943 if (clk->enabled && 944 stm32mp_nsec_can_access_clock(clk->clock_id)) 945 clk_enable(clk->clk); 946 } 947 948 for (j = 0; j < res->rd_count; j++) { 949 struct stm32_scmi_rd *rd = &res->rd[j]; 950 struct rstctrl *rstctrl = NULL; 951 952 if (!rd->name || 953 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 954 panic("SCMI reset domain name invalid"); 955 956 if (stm32mp_nsec_can_access_clock(rd->reset_id)) 957 continue; 958 959 rstctrl = stm32mp_rcc_reset_id_to_rstctrl(rd->reset_id); 960 assert(rstctrl); 961 if (rstctrl_get_exclusive(rstctrl)) 962 continue; 963 964 rd->rstctrl = rstctrl; 965 } 966 967 for (j = 0; j < res->voltd_count; j++) { 968 struct stm32_scmi_voltd *voltd = &res->voltd[j]; 969 970 if (!voltd->name || 971 strlen(voltd->name) >= SCMI_VOLTD_NAME_SIZE) 972 panic("SCMI voltage domain name invalid"); 973 } 974 } 975 976 return TEE_SUCCESS; 977 } 978 979 driver_init_late(stm32mp1_init_scmi_server); 980