1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019-2022, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <confine_array_index.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/regulator.h> 11 #include <drivers/rstctrl.h> 12 #include <drivers/scmi-msg.h> 13 #include <drivers/scmi.h> 14 #include <drivers/stm32_vrefbuf.h> 15 #include <drivers/stm32mp1_pmic.h> 16 #include <drivers/stm32mp1_pwr.h> 17 #include <drivers/stm32mp13_regulator_iod.h> 18 #include <drivers/stpmic1.h> 19 #include <drivers/stpmic1_regulator.h> 20 #include <drivers/stm32mp_dt_bindings.h> 21 #include <initcall.h> 22 #include <mm/core_memprot.h> 23 #include <mm/core_mmu.h> 24 #include <platform_config.h> 25 #include <stdint.h> 26 #include <speculation_barrier.h> 27 #include <stm32_util.h> 28 #include <string.h> 29 #include <tee_api_defines.h> 30 #include <util.h> 31 32 #define TIMEOUT_US_1MS 1000 33 34 #define SCMI_CLOCK_NAME_SIZE 16 35 #define SCMI_RD_NAME_SIZE 16 36 #define SCMI_VOLTD_NAME_SIZE 16 37 38 /* 39 * struct stm32_scmi_clk - Data for the exposed clock 40 * @clock_id: Clock identifier in RCC clock driver 41 * @name: Clock string ID exposed to channel 42 * @enabled: State of the SCMI clock 43 */ 44 struct stm32_scmi_clk { 45 unsigned long clock_id; 46 struct clk *clk; 47 const char *name; 48 bool enabled; 49 }; 50 51 /* 52 * struct stm32_scmi_rd - Data for the exposed reset controller 53 * @reset_id: Reset identifier in RCC reset driver 54 * @name: Reset string ID exposed to channel 55 * @rstctrl: Reset controller device 56 */ 57 struct stm32_scmi_rd { 58 unsigned long reset_id; 59 const char *name; 60 struct rstctrl *rstctrl; 61 }; 62 63 enum voltd_device { 64 VOLTD_PWR, 65 VOLTD_PMIC, 66 VOLTD_VREFBUF, 67 VOLTD_IOD, 68 }; 69 70 /* 71 * struct stm32_scmi_voltd - Data for the exposed voltage domains 72 * @name: Power regulator string ID exposed to channel 73 * @priv_name: Internal string ID for the PMIC regulators 74 * @priv_id: Internal ID for the regulator aside PMIC ones 75 * @priv_dev: Internal ID for the device implementing the regulator 76 * @regulator: Regulator controller device 77 * @state: State of the SCMI voltage domain (true: enable, false: disable) 78 */ 79 struct stm32_scmi_voltd { 80 const char *name; 81 const char *priv_name; 82 unsigned int priv_id; 83 enum voltd_device priv_dev; 84 struct regulator *regulator; 85 bool state; 86 }; 87 88 #if CFG_STM32MP1_SCMI_SHM_BASE 89 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 90 CFG_STM32MP1_SCMI_SHM_SIZE); 91 92 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 93 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 94 95 #if (SMT_BUFFER_BASE + SMT_BUF_SLOT_SIZE > \ 96 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 97 #error "SCMI shared memory mismatch" 98 #endif 99 #endif /*CFG_STM32MP1_SCMI_SHM_BASE*/ 100 101 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 102 [(_scmi_id)] = { \ 103 .clock_id = (_id), \ 104 .name = (_name), \ 105 .enabled = (_init_enabled), \ 106 } 107 108 #define RESET_CELL(_scmi_id, _id, _name) \ 109 [(_scmi_id)] = { \ 110 .reset_id = (_id), \ 111 .name = (_name), \ 112 } 113 114 #define VOLTD_CELL(_scmi_id, _dev_id, _priv_id, _priv_name, _name) \ 115 [(_scmi_id)] = { \ 116 .priv_name = (_priv_name), \ 117 .priv_id = (_priv_id), \ 118 .priv_dev = (_dev_id), \ 119 .name = (_name), \ 120 } 121 122 #define VOLTD_CELL_PWR(_scmi_id, _priv_id, _name) \ 123 VOLTD_CELL((_scmi_id), VOLTD_PWR, (_priv_id), NULL, (_name)) 124 125 #define VOLTD_CELL_IOD(_scmi_id, _priv_id, _name) \ 126 VOLTD_CELL((_scmi_id), VOLTD_IOD, (_priv_id), NULL, (_name)) 127 128 #define VOLTD_CELL_VREFBUF(_scmi_id, _name) \ 129 VOLTD_CELL((_scmi_id), VOLTD_VREFBUF, 0, NULL, (_name)) 130 131 #define VOLTD_CELL_PMIC(_scmi_id, _priv_name, _name) \ 132 VOLTD_CELL((_scmi_id), VOLTD_PMIC, 0, (_priv_name), (_name)) 133 134 #ifdef CFG_STM32MP13 135 static struct stm32_scmi_clk stm32_scmi_clock[] = { 136 CLOCK_CELL(CK_SCMI_HSE, CK_HSE, "ck_hse", true), 137 CLOCK_CELL(CK_SCMI_HSI, CK_HSI, "ck_hsi", true), 138 CLOCK_CELL(CK_SCMI_CSI, CK_CSI, "ck_csi", true), 139 CLOCK_CELL(CK_SCMI_LSE, CK_LSE, "ck_lse", true), 140 CLOCK_CELL(CK_SCMI_LSI, CK_LSI, "ck_lsi", true), 141 CLOCK_CELL(CK_SCMI_HSE_DIV2, CK_HSE_DIV2, "clk-hse-div2", true), 142 CLOCK_CELL(CK_SCMI_PLL2_Q, PLL2_Q, "pll2_q", true), 143 CLOCK_CELL(CK_SCMI_PLL2_R, PLL2_R, "pll2_r", true), 144 CLOCK_CELL(CK_SCMI_PLL3_P, PLL3_P, "pll3_p", true), 145 CLOCK_CELL(CK_SCMI_PLL3_Q, PLL3_Q, "pll3_q", true), 146 CLOCK_CELL(CK_SCMI_PLL3_R, PLL3_R, "pll3_r", true), 147 CLOCK_CELL(CK_SCMI_PLL4_P, PLL4_P, "pll4_p", true), 148 CLOCK_CELL(CK_SCMI_PLL4_Q, PLL4_Q, "pll4_q", true), 149 CLOCK_CELL(CK_SCMI_PLL4_R, PLL4_R, "pll4_r", true), 150 CLOCK_CELL(CK_SCMI_MPU, CK_MPU, "ck_mpu", true), 151 CLOCK_CELL(CK_SCMI_AXI, CK_AXI, "ck_axi", true), 152 CLOCK_CELL(CK_SCMI_MLAHB, CK_MLAHB, "ck_mlahb", true), 153 CLOCK_CELL(CK_SCMI_CKPER, CK_PER, "ck_per", true), 154 CLOCK_CELL(CK_SCMI_PCLK1, PCLK1, "pclk1", true), 155 CLOCK_CELL(CK_SCMI_PCLK2, PCLK2, "pclk2", true), 156 CLOCK_CELL(CK_SCMI_PCLK3, PCLK3, "pclk3", true), 157 CLOCK_CELL(CK_SCMI_PCLK4, PCLK4, "pclk4", true), 158 CLOCK_CELL(CK_SCMI_PCLK5, PCLK5, "pclk5", true), 159 CLOCK_CELL(CK_SCMI_PCLK6, PCLK6, "pclk6", true), 160 CLOCK_CELL(CK_SCMI_CKTIMG1, CK_TIMG1, "timg1_ck", true), 161 CLOCK_CELL(CK_SCMI_CKTIMG2, CK_TIMG2, "timg2_ck", true), 162 CLOCK_CELL(CK_SCMI_CKTIMG3, CK_TIMG3, "timg3_ck", true), 163 CLOCK_CELL(CK_SCMI_RTC, RTC, "ck_rtc", true), 164 CLOCK_CELL(CK_SCMI_RTCAPB, RTCAPB, "rtcapb", true), 165 CLOCK_CELL(CK_SCMI_BSEC, BSEC, "bsec", true), 166 }; 167 #endif 168 169 #ifdef CFG_STM32MP15 170 static struct stm32_scmi_clk stm32_scmi_clock[] = { 171 CLOCK_CELL(CK_SCMI_HSE, CK_HSE, "ck_hse", true), 172 CLOCK_CELL(CK_SCMI_HSI, CK_HSI, "ck_hsi", true), 173 CLOCK_CELL(CK_SCMI_CSI, CK_CSI, "ck_csi", true), 174 CLOCK_CELL(CK_SCMI_LSE, CK_LSE, "ck_lse", true), 175 CLOCK_CELL(CK_SCMI_LSI, CK_LSI, "ck_lsi", true), 176 CLOCK_CELL(CK_SCMI_PLL2_Q, PLL2_Q, "pll2_q", true), 177 CLOCK_CELL(CK_SCMI_PLL2_R, PLL2_R, "pll2_r", true), 178 CLOCK_CELL(CK_SCMI_MPU, CK_MPU, "ck_mpu", true), 179 CLOCK_CELL(CK_SCMI_AXI, CK_AXI, "ck_axi", true), 180 CLOCK_CELL(CK_SCMI_BSEC, BSEC, "bsec", true), 181 CLOCK_CELL(CK_SCMI_CRYP1, CRYP1, "cryp1", false), 182 CLOCK_CELL(CK_SCMI_GPIOZ, GPIOZ, "gpioz", false), 183 CLOCK_CELL(CK_SCMI_HASH1, HASH1, "hash1", false), 184 CLOCK_CELL(CK_SCMI_I2C4, I2C4_K, "i2c4_k", false), 185 CLOCK_CELL(CK_SCMI_I2C6, I2C6_K, "i2c6_k", false), 186 CLOCK_CELL(CK_SCMI_IWDG1, IWDG1, "iwdg1", false), 187 CLOCK_CELL(CK_SCMI_RNG1, RNG1_K, "rng1_k", true), 188 CLOCK_CELL(CK_SCMI_RTC, RTC, "ck_rtc", true), 189 CLOCK_CELL(CK_SCMI_RTCAPB, RTCAPB, "rtcapb", true), 190 CLOCK_CELL(CK_SCMI_SPI6, SPI6_K, "spi6_k", false), 191 CLOCK_CELL(CK_SCMI_USART1, USART1_K, "usart1_k", false), 192 }; 193 #endif 194 195 #ifdef CFG_STM32MP13 196 static struct stm32_scmi_rd stm32_scmi_reset_domain[] = { 197 RESET_CELL(RST_SCMI_LTDC, LTDC_R, "ltdc"), 198 RESET_CELL(RST_SCMI_MDMA, MDMA_R, "mdma"), 199 }; 200 #endif 201 202 #ifdef CFG_STM32MP15 203 static struct stm32_scmi_rd stm32_scmi_reset_domain[] = { 204 RESET_CELL(RST_SCMI_SPI6, SPI6_R, "spi6"), 205 RESET_CELL(RST_SCMI_I2C4, I2C4_R, "i2c4"), 206 RESET_CELL(RST_SCMI_I2C6, I2C6_R, "i2c6"), 207 RESET_CELL(RST_SCMI_USART1, USART1_R, "usart1"), 208 RESET_CELL(RST_SCMI_STGEN, STGEN_R, "stgen"), 209 RESET_CELL(RST_SCMI_GPIOZ, GPIOZ_R, "gpioz"), 210 RESET_CELL(RST_SCMI_CRYP1, CRYP1_R, "cryp1"), 211 RESET_CELL(RST_SCMI_HASH1, HASH1_R, "hash1"), 212 RESET_CELL(RST_SCMI_RNG1, RNG1_R, "rng1"), 213 RESET_CELL(RST_SCMI_MDMA, MDMA_R, "mdma"), 214 RESET_CELL(RST_SCMI_MCU, MCU_R, "mcu"), 215 RESET_CELL(RST_SCMI_MCU_HOLD_BOOT, MCU_HOLD_BOOT_R, "mcu_hold_boot"), 216 }; 217 #endif 218 219 #ifdef CFG_STM32MP13 220 struct stm32_scmi_voltd scmi_voltage_domain[] = { 221 VOLTD_CELL_PWR(VOLTD_SCMI_REG11, PWR_REG11, "reg11"), 222 VOLTD_CELL_PWR(VOLTD_SCMI_REG18, PWR_REG18, "reg18"), 223 VOLTD_CELL_PWR(VOLTD_SCMI_USB33, PWR_USB33, "usb33"), 224 VOLTD_CELL_IOD(VOLTD_SCMI_SDMMC1_IO, IOD_SDMMC1, "sdmmc1"), 225 VOLTD_CELL_IOD(VOLTD_SCMI_SDMMC2_IO, IOD_SDMMC2, "sdmmc2"), 226 VOLTD_CELL_VREFBUF(VOLTD_SCMI_VREFBUF, "vrefbuf"), 227 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK1, "buck1", "buck1"), 228 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK2, "buck2", "buck2"), 229 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK3, "buck3", "buck3"), 230 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK4, "buck4", "buck4"), 231 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO1, "ldo1", "ldo1"), 232 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO2, "ldo2", "ldo2"), 233 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO3, "ldo3", "ldo3"), 234 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO4, "ldo4", "ldo4"), 235 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO5, "ldo5", "ldo5"), 236 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO6, "ldo6", "ldo6"), 237 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_VREFDDR, "vref_ddr", "vref_ddr"), 238 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BOOST, "boost", "bst_out"), 239 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_PWR_SW1, "pwr_sw1", "pwr_sw1"), 240 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_PWR_SW2, "pwr_sw2", "pwr_sw2"), 241 }; 242 #endif 243 244 #ifdef CFG_STM32MP15 245 struct stm32_scmi_voltd scmi_voltage_domain[] = { 246 VOLTD_CELL_PWR(VOLTD_SCMI_REG11, PWR_REG11, "reg11"), 247 VOLTD_CELL_PWR(VOLTD_SCMI_REG18, PWR_REG18, "reg18"), 248 VOLTD_CELL_PWR(VOLTD_SCMI_USB33, PWR_USB33, "usb33"), 249 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK1, "buck1", "vddcore"), 250 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK2, "buck2", "vdd_ddr"), 251 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK3, "buck3", "vdd"), 252 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK4, "buck4", "v3v3"), 253 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO1, "ldo1", "v1v8_audio"), 254 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO2, "ldo2", "v3v3_hdmi"), 255 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO3, "ldo3", "vtt_ddr"), 256 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO4, "ldo4", "vdd_usb"), 257 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO5, "ldo5", "vdda"), 258 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO6, "ldo6", "v1v2_hdmi"), 259 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_VREFDDR, "vref_ddr", "vref_ddr"), 260 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BOOST, "boost", "bst_out"), 261 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_PWR_SW1, "pwr_sw1", "vbus_otg"), 262 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_PWR_SW2, "pwr_sw2", "vbus_sw"), 263 }; 264 #endif 265 266 struct channel_resources { 267 struct scmi_msg_channel *channel; 268 struct stm32_scmi_clk *clock; 269 size_t clock_count; 270 struct stm32_scmi_rd *rd; 271 size_t rd_count; 272 struct stm32_scmi_voltd *voltd; 273 size_t voltd_count; 274 }; 275 276 static const struct channel_resources scmi_channel[] = { 277 [0] = { 278 .channel = &(struct scmi_msg_channel){ 279 #ifdef SMT_BUFFER_BASE 280 .shm_addr = { .pa = SMT_BUFFER_BASE }, 281 .shm_size = SMT_BUF_SLOT_SIZE, 282 #endif 283 }, 284 .clock = stm32_scmi_clock, 285 .clock_count = ARRAY_SIZE(stm32_scmi_clock), 286 .rd = stm32_scmi_reset_domain, 287 .rd_count = ARRAY_SIZE(stm32_scmi_reset_domain), 288 .voltd = scmi_voltage_domain, 289 .voltd_count = ARRAY_SIZE(scmi_voltage_domain), 290 }, 291 }; 292 293 static const struct channel_resources *find_resource(unsigned int channel_id) 294 { 295 assert(channel_id < ARRAY_SIZE(scmi_channel)); 296 297 return scmi_channel + channel_id; 298 } 299 300 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int channel_id) 301 { 302 const size_t max_id = ARRAY_SIZE(scmi_channel); 303 unsigned int confined_id = confine_array_index(channel_id, max_id); 304 305 if (channel_id >= max_id) 306 return NULL; 307 308 return find_resource(confined_id)->channel; 309 } 310 311 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 312 { 313 unsigned int n = 0; 314 unsigned int count = 0; 315 const size_t channel_count = ARRAY_SIZE(scmi_channel); 316 317 for (n = 0; n < channel_count; n++) 318 if (scmi_channel[n].clock_count) 319 break; 320 if (n < channel_count) 321 count++; 322 323 for (n = 0; n < channel_count; n++) 324 if (scmi_channel[n].rd_count) 325 break; 326 if (n < channel_count) 327 count++; 328 329 for (n = 0; n < channel_count; n++) 330 if (scmi_channel[n].voltd_count) 331 break; 332 if (n < channel_count) 333 count++; 334 335 return count; 336 } 337 338 static const char vendor[] = "ST"; 339 static const char sub_vendor[] = ""; 340 341 const char *plat_scmi_vendor_name(void) 342 { 343 return vendor; 344 } 345 346 const char *plat_scmi_sub_vendor_name(void) 347 { 348 return sub_vendor; 349 } 350 351 /* Currently supporting Clocks and Reset Domains */ 352 static const uint8_t plat_protocol_list[] = { 353 SCMI_PROTOCOL_ID_CLOCK, 354 SCMI_PROTOCOL_ID_RESET_DOMAIN, 355 SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, 356 0 /* Null termination */ 357 }; 358 359 size_t plat_scmi_protocol_count(void) 360 { 361 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 362 363 assert(count == plat_scmi_protocol_count_paranoid()); 364 365 return count; 366 } 367 368 const uint8_t *plat_scmi_protocol_list(unsigned int channel_id __unused) 369 { 370 assert(plat_scmi_protocol_count_paranoid() == 371 (ARRAY_SIZE(plat_protocol_list) - 1)); 372 373 return plat_protocol_list; 374 } 375 376 /* 377 * Platform SCMI clocks 378 */ 379 static struct stm32_scmi_clk *find_clock(unsigned int channel_id, 380 unsigned int scmi_id) 381 { 382 const struct channel_resources *resource = find_resource(channel_id); 383 size_t n = 0; 384 385 if (resource) { 386 for (n = 0; n < resource->clock_count; n++) 387 if (n == scmi_id) 388 return &resource->clock[n]; 389 } 390 391 return NULL; 392 } 393 394 size_t plat_scmi_clock_count(unsigned int channel_id) 395 { 396 const struct channel_resources *resource = find_resource(channel_id); 397 398 if (!resource) 399 return 0; 400 401 return resource->clock_count; 402 } 403 404 const char *plat_scmi_clock_get_name(unsigned int channel_id, 405 unsigned int scmi_id) 406 { 407 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 408 409 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 410 return NULL; 411 412 return clock->name; 413 } 414 415 int32_t plat_scmi_clock_rates_array(unsigned int channel_id, 416 unsigned int scmi_id, size_t start_index, 417 unsigned long *array, size_t *nb_elts) 418 { 419 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 420 421 if (!clock) 422 return SCMI_NOT_FOUND; 423 424 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 425 return SCMI_DENIED; 426 427 /* Exposed clocks are currently fixed rate clocks */ 428 if (start_index) 429 return SCMI_INVALID_PARAMETERS; 430 431 if (!array) 432 *nb_elts = 1; 433 else if (*nb_elts == 1) 434 *array = clk_get_rate(clock->clk); 435 else 436 return SCMI_GENERIC_ERROR; 437 438 return SCMI_SUCCESS; 439 } 440 441 unsigned long plat_scmi_clock_get_rate(unsigned int channel_id, 442 unsigned int scmi_id) 443 { 444 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 445 446 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 447 return 0; 448 449 return clk_get_rate(clock->clk); 450 } 451 452 int32_t plat_scmi_clock_get_state(unsigned int channel_id, unsigned int scmi_id) 453 { 454 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 455 456 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 457 return 0; 458 459 return (int32_t)clock->enabled; 460 } 461 462 int32_t plat_scmi_clock_set_state(unsigned int channel_id, unsigned int scmi_id, 463 bool enable_not_disable) 464 { 465 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 466 467 if (!clock) 468 return SCMI_NOT_FOUND; 469 470 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 471 return SCMI_DENIED; 472 473 if (enable_not_disable) { 474 if (!clock->enabled) { 475 FMSG("SCMI clock %u enable", scmi_id); 476 clk_enable(clock->clk); 477 clock->enabled = true; 478 } 479 } else { 480 if (clock->enabled) { 481 FMSG("SCMI clock %u disable", scmi_id); 482 clk_disable(clock->clk); 483 clock->enabled = false; 484 } 485 } 486 487 return SCMI_SUCCESS; 488 } 489 490 /* 491 * Platform SCMI reset domains 492 */ 493 static struct stm32_scmi_rd *find_rd(unsigned int channel_id, 494 unsigned int scmi_id) 495 { 496 const struct channel_resources *resource = find_resource(channel_id); 497 size_t n = 0; 498 499 if (resource) { 500 for (n = 0; n < resource->rd_count; n++) 501 if (n == scmi_id) 502 return &resource->rd[n]; 503 } 504 505 return NULL; 506 } 507 508 const char *plat_scmi_rd_get_name(unsigned int channel_id, unsigned int scmi_id) 509 { 510 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 511 512 if (!rd) 513 return NULL; 514 515 return rd->name; 516 } 517 518 size_t plat_scmi_rd_count(unsigned int channel_id) 519 { 520 const struct channel_resources *resource = find_resource(channel_id); 521 522 if (!resource) 523 return 0; 524 525 return resource->rd_count; 526 } 527 528 int32_t plat_scmi_rd_autonomous(unsigned int channel_id, unsigned int scmi_id, 529 uint32_t state) 530 { 531 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 532 533 if (!rd) 534 return SCMI_NOT_FOUND; 535 536 if (!rd->rstctrl || !stm32mp_nsec_can_access_reset(rd->reset_id)) 537 return SCMI_DENIED; 538 assert(rd->rstctrl); 539 540 #ifdef CFG_STM32MP15 541 if (rd->reset_id == MCU_HOLD_BOOT_R) 542 return SCMI_NOT_SUPPORTED; 543 #endif 544 545 /* Supports only reset with context loss */ 546 if (state) 547 return SCMI_NOT_SUPPORTED; 548 549 FMSG("SCMI reset %u cycle", scmi_id); 550 551 if (rstctrl_assert_to(rd->rstctrl, TIMEOUT_US_1MS)) 552 return SCMI_HARDWARE_ERROR; 553 554 if (rstctrl_deassert_to(rd->rstctrl, TIMEOUT_US_1MS)) 555 return SCMI_HARDWARE_ERROR; 556 557 return SCMI_SUCCESS; 558 } 559 560 int32_t plat_scmi_rd_set_state(unsigned int channel_id, unsigned int scmi_id, 561 bool assert_not_deassert) 562 { 563 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 564 TEE_Result res = TEE_ERROR_GENERIC; 565 566 if (!rd) 567 return SCMI_NOT_FOUND; 568 569 if (!rd->rstctrl || !stm32mp_nsec_can_access_reset(rd->reset_id)) 570 return SCMI_DENIED; 571 assert(rd->rstctrl); 572 573 if (assert_not_deassert) { 574 FMSG("SCMI reset %u set", scmi_id); 575 res = rstctrl_assert(rd->rstctrl); 576 } else { 577 FMSG("SCMI reset %u release", scmi_id); 578 res = rstctrl_deassert(rd->rstctrl); 579 } 580 581 if (res) 582 return SCMI_HARDWARE_ERROR; 583 584 return SCMI_SUCCESS; 585 } 586 587 /* 588 * Platform SCMI voltage domains 589 */ 590 static struct stm32_scmi_voltd *find_voltd(unsigned int channel_id, 591 unsigned int scmi_id) 592 { 593 const struct channel_resources *resource = find_resource(channel_id); 594 size_t n = 0; 595 596 if (resource) { 597 for (n = 0; n < resource->voltd_count; n++) 598 if (n == scmi_id) 599 return &resource->voltd[n]; 600 } 601 602 return NULL; 603 } 604 605 size_t plat_scmi_voltd_count(unsigned int channel_id) 606 { 607 const struct channel_resources *resource = find_resource(channel_id); 608 609 if (!resource) 610 return 0; 611 612 return resource->voltd_count; 613 } 614 615 const char *plat_scmi_voltd_get_name(unsigned int channel_id, 616 unsigned int scmi_id) 617 { 618 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 619 620 /* Currently non-secure is allowed to access all PWR regulators */ 621 if (!voltd) 622 return NULL; 623 624 return voltd->name; 625 } 626 627 int32_t plat_scmi_voltd_levels_array(unsigned int channel_id, 628 unsigned int scmi_id, size_t start_index, 629 long *out_levels, size_t *nb_elts) 630 631 { 632 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 633 634 if (!voltd) 635 return SCMI_NOT_FOUND; 636 637 if (voltd->regulator) { 638 struct regulator_voltages_desc *desc = NULL; 639 TEE_Result res = TEE_ERROR_GENERIC; 640 const int *levels = NULL; 641 size_t n = 0; 642 643 res = regulator_supported_voltages(voltd->regulator, &desc, 644 &levels); 645 if (res == TEE_ERROR_NOT_SUPPORTED) 646 return SCMI_NOT_SUPPORTED; 647 if (res) 648 return SCMI_GENERIC_ERROR; 649 if (!desc || desc->type != VOLTAGE_TYPE_FULL_LIST) { 650 /* 651 * Triplet min/max/step description. Caller should use 652 * plat_scmi_voltd_levels_by_step(). 653 */ 654 return SCMI_NOT_SUPPORTED; 655 } 656 657 if (start_index >= desc->num_levels) 658 return SCMI_OUT_OF_RANGE; 659 660 if (!*nb_elts) { 661 *nb_elts = desc->num_levels - start_index; 662 return SCMI_SUCCESS; 663 } 664 665 *nb_elts = MIN(*nb_elts, desc->num_levels - start_index); 666 for (n = 0; n < *nb_elts; n++) 667 out_levels[n] = levels[start_index + n]; 668 669 return SCMI_SUCCESS; 670 } 671 672 return SCMI_DENIED; 673 } 674 675 int32_t plat_scmi_voltd_levels_by_step(unsigned int channel_id, 676 unsigned int scmi_id, long *min_max_step) 677 { 678 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 679 680 if (!voltd) 681 return SCMI_NOT_FOUND; 682 683 if (voltd->regulator) { 684 struct regulator_voltages_desc *desc = NULL; 685 TEE_Result res = TEE_ERROR_GENERIC; 686 const int *levels = NULL; 687 688 res = regulator_supported_voltages(voltd->regulator, &desc, 689 &levels); 690 if (res == TEE_ERROR_NOT_SUPPORTED) 691 return SCMI_NOT_SUPPORTED; 692 if (res) 693 return SCMI_GENERIC_ERROR; 694 if (!desc || desc->type != VOLTAGE_TYPE_INCREMENT) { 695 /* 696 * Triplet min/max/step description. Caller should use 697 * plat_scmi_voltd_levels_by_step(). 698 */ 699 return SCMI_NOT_SUPPORTED; 700 } 701 702 min_max_step[0] = levels[0]; 703 min_max_step[1] = levels[1]; 704 min_max_step[2] = levels[2]; 705 706 return SCMI_SUCCESS; 707 } 708 709 return SCMI_NOT_SUPPORTED; 710 } 711 712 int32_t plat_scmi_voltd_get_level(unsigned int channel_id, unsigned int scmi_id, 713 long *level_uv) 714 { 715 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 716 717 if (!voltd) 718 return SCMI_INVALID_PARAMETERS; 719 720 if (voltd->regulator) { 721 *level_uv = regulator_get_voltage(voltd->regulator); 722 return SCMI_SUCCESS; 723 } 724 725 return SCMI_DENIED; 726 } 727 728 int32_t plat_scmi_voltd_set_level(unsigned int channel_id, unsigned int scmi_id, 729 long level_uv) 730 { 731 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 732 733 if (!voltd) 734 return SCMI_NOT_FOUND; 735 736 if (voltd->regulator) { 737 TEE_Result res = TEE_ERROR_GENERIC; 738 739 if (level_uv < INT_MIN || level_uv > INT_MAX) 740 return SCMI_OUT_OF_RANGE; 741 742 res = regulator_set_voltage(voltd->regulator, level_uv); 743 if (res) 744 return SCMI_GENERIC_ERROR; 745 else 746 return SCMI_SUCCESS; 747 } 748 749 return SCMI_DENIED; 750 } 751 752 int32_t plat_scmi_voltd_get_config(unsigned int channel_id, 753 unsigned int scmi_id, uint32_t *config) 754 { 755 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 756 757 if (!voltd) 758 return SCMI_NOT_FOUND; 759 760 if (voltd->regulator) { 761 if (voltd->state) 762 *config = SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 763 else 764 *config = SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 765 766 return SCMI_SUCCESS; 767 } 768 769 return SCMI_DENIED; 770 } 771 772 int32_t plat_scmi_voltd_set_config(unsigned int channel_id, 773 unsigned int scmi_id, uint32_t config) 774 { 775 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 776 777 if (!voltd) 778 return SCMI_NOT_FOUND; 779 780 if (voltd->regulator) { 781 switch (config) { 782 case SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON: 783 if (!voltd->state) { 784 if (regulator_enable(voltd->regulator)) 785 return SCMI_GENERIC_ERROR; 786 787 voltd->state = true; 788 } 789 break; 790 case SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF: 791 if (voltd->state) { 792 if (regulator_disable(voltd->regulator)) 793 return SCMI_GENERIC_ERROR; 794 795 voltd->state = false; 796 } 797 break; 798 default: 799 return SCMI_INVALID_PARAMETERS; 800 } 801 802 return SCMI_SUCCESS; 803 } 804 805 return SCMI_DENIED; 806 } 807 808 static void get_voltd_regulator(struct stm32_scmi_voltd *voltd) 809 { 810 switch (voltd->priv_dev) { 811 case VOLTD_PWR: 812 voltd->regulator = stm32mp1_pwr_get_regulator(voltd->priv_id); 813 break; 814 case VOLTD_PMIC: 815 voltd->regulator = stm32mp_pmic_get_regulator(voltd->priv_name); 816 break; 817 case VOLTD_VREFBUF: 818 voltd->regulator = stm32_vrefbuf_regulator(); 819 break; 820 case VOLTD_IOD: 821 voltd->regulator = stm32mp1_get_iod_regulator(voltd->priv_id); 822 break; 823 default: 824 break; 825 } 826 827 if (voltd->regulator && voltd->regulator->flags & REGULATOR_BOOT_ON) 828 regulator_enable(voltd->regulator); 829 } 830 831 /* 832 * Initialize platform SCMI resources 833 */ 834 static TEE_Result stm32mp1_init_scmi_server(void) 835 { 836 size_t i = 0; 837 size_t j = 0; 838 839 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 840 const struct channel_resources *res = scmi_channel + i; 841 struct scmi_msg_channel *chan = res->channel; 842 843 if (chan->shm_addr.pa) { 844 struct io_pa_va *addr = &chan->shm_addr; 845 846 /* Enforce non-secure shm mapped as device memory */ 847 addr->va = (vaddr_t)phys_to_virt(addr->pa, 848 MEM_AREA_IO_NSEC, 849 chan->shm_size); 850 assert(addr->va); 851 852 scmi_smt_init_agent_channel(chan); 853 } 854 855 for (j = 0; j < res->clock_count; j++) { 856 struct stm32_scmi_clk *clk = &res->clock[j]; 857 858 if (!clk->name || 859 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 860 panic("SCMI clock name invalid"); 861 862 clk->clk = stm32mp_rcc_clock_id_to_clk(clk->clock_id); 863 assert(clk->clk); 864 865 /* Sync SCMI clocks with their targeted initial state */ 866 if (clk->enabled && 867 stm32mp_nsec_can_access_clock(clk->clock_id)) 868 clk_enable(clk->clk); 869 } 870 871 for (j = 0; j < res->rd_count; j++) { 872 struct stm32_scmi_rd *rd = &res->rd[j]; 873 struct rstctrl *rstctrl = NULL; 874 875 if (!rd->name || 876 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 877 panic("SCMI reset domain name invalid"); 878 879 if (stm32mp_nsec_can_access_clock(rd->reset_id)) 880 continue; 881 882 rstctrl = stm32mp_rcc_reset_id_to_rstctrl(rd->reset_id); 883 assert(rstctrl); 884 if (rstctrl_get_exclusive(rstctrl)) 885 continue; 886 887 rd->rstctrl = rstctrl; 888 } 889 890 for (j = 0; j < res->voltd_count; j++) { 891 struct stm32_scmi_voltd *voltd = &res->voltd[j]; 892 893 if (!voltd->name || 894 strlen(voltd->name) >= SCMI_VOLTD_NAME_SIZE) 895 panic("SCMI voltage domain name invalid"); 896 897 get_voltd_regulator(voltd); 898 } 899 } 900 901 return TEE_SUCCESS; 902 } 903 904 driver_init_late(stm32mp1_init_scmi_server); 905