1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019-2022, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <confine_array_index.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/firewall_device.h> 11 #include <drivers/regulator.h> 12 #include <drivers/rstctrl.h> 13 #include <drivers/scmi-msg.h> 14 #include <drivers/scmi.h> 15 #include <drivers/stm32_cpu_opp.h> 16 #include <drivers/stm32_remoteproc.h> 17 #include <drivers/stm32_vrefbuf.h> 18 #include <drivers/stm32mp1_pmic.h> 19 #include <drivers/stm32mp1_pwr.h> 20 #include <drivers/stm32mp13_regulator_iod.h> 21 #include <drivers/stpmic1.h> 22 #include <drivers/stpmic1_regulator.h> 23 #include <drivers/stm32mp_dt_bindings.h> 24 #include <initcall.h> 25 #include <mm/core_memprot.h> 26 #include <mm/core_mmu.h> 27 #include <platform_config.h> 28 #include <stdbool.h> 29 #include <stdint.h> 30 #include <speculation_barrier.h> 31 #include <stm32_util.h> 32 #include <string.h> 33 #include <tee_api_defines.h> 34 #include <util.h> 35 36 #define TIMEOUT_US_1MS 1000 37 38 #define SCMI_CLOCK_NAME_SIZE 16 39 #define SCMI_RD_NAME_SIZE 16 40 #define SCMI_VOLTD_NAME_SIZE 16 41 42 #define ETZPC_ID_ALWAYS_ACCESSIBLE (STM32MP1_ETZPC_MAX_ID + 1) 43 #define ETZPC_ID_NEVER_ACCESSIBLE (STM32MP1_ETZPC_MAX_ID + 2) 44 45 /* 46 * struct stm32_scmi_clk - Data for the exposed clock 47 * @clock_id: Clock identifier in RCC clock driver 48 * @etzpc_id: ETZPC ID of the peripheral related to the clock 49 * @name: Clock string ID exposed to channel 50 * @enabled: State of the SCMI clock 51 */ 52 struct stm32_scmi_clk { 53 unsigned long clock_id; 54 struct clk *clk; 55 unsigned int etzpc_id; 56 const char *name; 57 bool enabled; 58 }; 59 60 /* 61 * struct stm32_scmi_rd - Data for the exposed reset controller 62 * @reset_id: Reset identifier in RCC reset driver 63 * @etzpc_id: ETZPC ID of the peripheral related to the reset controller 64 * @name: Reset string ID exposed to channel 65 * @rstctrl: Reset controller device 66 */ 67 struct stm32_scmi_rd { 68 unsigned long reset_id; 69 unsigned int etzpc_id; 70 const char *name; 71 struct rstctrl *rstctrl; 72 }; 73 74 enum voltd_device { 75 VOLTD_PWR, 76 VOLTD_PMIC, 77 VOLTD_VREFBUF, 78 VOLTD_IOD, 79 }; 80 81 /* 82 * struct stm32_scmi_voltd - Data for the exposed voltage domains 83 * @name: Power regulator string ID exposed to channel 84 * @priv_name: Internal string ID for the PMIC regulators 85 * @priv_id: Internal ID for the regulator aside PMIC ones 86 * @priv_dev: Internal ID for the device implementing the regulator 87 * @regulator: Regulator controller device 88 * @state: State of the SCMI voltage domain (true: enable, false: disable) 89 */ 90 struct stm32_scmi_voltd { 91 const char *name; 92 const char *priv_name; 93 unsigned int priv_id; 94 enum voltd_device priv_dev; 95 struct regulator *regulator; 96 bool state; 97 }; 98 99 /* 100 * struct stm32_scmi_perfd - Data for the exposed performance domains 101 * @name: Performance domain string ID (aka name) exposed to channel 102 */ 103 struct stm32_scmi_perfd { 104 const char *name; 105 }; 106 107 #if CFG_STM32MP1_SCMI_SHM_BASE 108 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 109 CFG_STM32MP1_SCMI_SHM_SIZE); 110 111 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 112 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 113 114 #if (SMT_BUFFER_BASE + SMT_BUF_SLOT_SIZE > \ 115 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 116 #error "SCMI shared memory mismatch" 117 #endif 118 #endif /*CFG_STM32MP1_SCMI_SHM_BASE*/ 119 120 /* SCMI clock always accessible */ 121 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 122 [(_scmi_id)] = { \ 123 .clock_id = (_id), \ 124 .etzpc_id = ETZPC_ID_ALWAYS_ACCESSIBLE, \ 125 .name = (_name), \ 126 .enabled = (_init_enabled), \ 127 } 128 129 /* SCMI clock accessible upon DECPROT ID assigned to non-secure */ 130 #define CLOCK_CELL_DECPROT(_scmi_id, _id, _name, _init_enabled, _etzpc_id) \ 131 [(_scmi_id)] = { \ 132 .clock_id = (_id), \ 133 .etzpc_id = (_etzpc_id), \ 134 .name = (_name), \ 135 .enabled = (_init_enabled), \ 136 } 137 138 /* SCMI reset domain always accessible */ 139 #define RESET_CELL(_scmi_id, _id, _name) \ 140 [(_scmi_id)] = { \ 141 .reset_id = (_id), \ 142 .etzpc_id = ETZPC_ID_ALWAYS_ACCESSIBLE, \ 143 .name = (_name), \ 144 } 145 146 /* SCMI reset domain accessible upon DECPROT ID assigned to non-secure */ 147 #define RESET_CELL_DECPROT(_scmi_id, _id, _name, _etzpc_id) \ 148 [(_scmi_id)] = { \ 149 .reset_id = (_id), \ 150 .etzpc_id = (_etzpc_id), \ 151 .name = (_name), \ 152 } 153 154 #define VOLTD_CELL(_scmi_id, _dev_id, _priv_id, _priv_name, _name) \ 155 [(_scmi_id)] = { \ 156 .priv_name = (_priv_name), \ 157 .priv_id = (_priv_id), \ 158 .priv_dev = (_dev_id), \ 159 .name = (_name), \ 160 } 161 162 #define VOLTD_CELL_PWR(_scmi_id, _priv_id, _name) \ 163 VOLTD_CELL((_scmi_id), VOLTD_PWR, (_priv_id), NULL, (_name)) 164 165 #define VOLTD_CELL_IOD(_scmi_id, _priv_id, _name) \ 166 VOLTD_CELL((_scmi_id), VOLTD_IOD, (_priv_id), NULL, (_name)) 167 168 #define VOLTD_CELL_VREFBUF(_scmi_id, _name) \ 169 VOLTD_CELL((_scmi_id), VOLTD_VREFBUF, 0, NULL, (_name)) 170 171 #define VOLTD_CELL_PMIC(_scmi_id, _priv_name, _name) \ 172 VOLTD_CELL((_scmi_id), VOLTD_PMIC, 0, (_priv_name), (_name)) 173 174 #ifdef CFG_STM32MP13 175 static struct stm32_scmi_clk stm32_scmi_clock[] = { 176 CLOCK_CELL(CK_SCMI_HSE, CK_HSE, "ck_hse", true), 177 CLOCK_CELL(CK_SCMI_HSI, CK_HSI, "ck_hsi", true), 178 CLOCK_CELL(CK_SCMI_CSI, CK_CSI, "ck_csi", true), 179 CLOCK_CELL(CK_SCMI_LSE, CK_LSE, "ck_lse", true), 180 CLOCK_CELL(CK_SCMI_LSI, CK_LSI, "ck_lsi", true), 181 CLOCK_CELL(CK_SCMI_HSE_DIV2, CK_HSE_DIV2, "clk-hse-div2", true), 182 CLOCK_CELL(CK_SCMI_PLL2_Q, PLL2_Q, "pll2_q", true), 183 CLOCK_CELL(CK_SCMI_PLL2_R, PLL2_R, "pll2_r", true), 184 CLOCK_CELL(CK_SCMI_PLL3_P, PLL3_P, "pll3_p", true), 185 CLOCK_CELL(CK_SCMI_PLL3_Q, PLL3_Q, "pll3_q", true), 186 CLOCK_CELL(CK_SCMI_PLL3_R, PLL3_R, "pll3_r", true), 187 CLOCK_CELL(CK_SCMI_PLL4_P, PLL4_P, "pll4_p", true), 188 CLOCK_CELL(CK_SCMI_PLL4_Q, PLL4_Q, "pll4_q", true), 189 CLOCK_CELL(CK_SCMI_PLL4_R, PLL4_R, "pll4_r", true), 190 CLOCK_CELL(CK_SCMI_MPU, CK_MPU, "ck_mpu", true), 191 CLOCK_CELL(CK_SCMI_AXI, CK_AXI, "ck_axi", true), 192 CLOCK_CELL(CK_SCMI_MLAHB, CK_MLAHB, "ck_mlahb", true), 193 CLOCK_CELL(CK_SCMI_CKPER, CK_PER, "ck_per", true), 194 CLOCK_CELL(CK_SCMI_PCLK1, PCLK1, "pclk1", true), 195 CLOCK_CELL(CK_SCMI_PCLK2, PCLK2, "pclk2", true), 196 CLOCK_CELL(CK_SCMI_PCLK3, PCLK3, "pclk3", true), 197 CLOCK_CELL(CK_SCMI_PCLK4, PCLK4, "pclk4", true), 198 CLOCK_CELL(CK_SCMI_PCLK5, PCLK5, "pclk5", true), 199 CLOCK_CELL(CK_SCMI_PCLK6, PCLK6, "pclk6", true), 200 CLOCK_CELL(CK_SCMI_CKTIMG1, CK_TIMG1, "timg1_ck", true), 201 CLOCK_CELL(CK_SCMI_CKTIMG2, CK_TIMG2, "timg2_ck", true), 202 CLOCK_CELL(CK_SCMI_CKTIMG3, CK_TIMG3, "timg3_ck", true), 203 CLOCK_CELL(CK_SCMI_RTC, RTC, "ck_rtc", true), 204 CLOCK_CELL(CK_SCMI_RTCAPB, RTCAPB, "rtcapb", true), 205 CLOCK_CELL(CK_SCMI_BSEC, BSEC, "bsec", true), 206 }; 207 #endif 208 209 #ifdef CFG_STM32MP15 210 static struct stm32_scmi_clk stm32_scmi_clock[] = { 211 CLOCK_CELL(CK_SCMI_HSE, CK_HSE, "ck_hse", true), 212 CLOCK_CELL(CK_SCMI_HSI, CK_HSI, "ck_hsi", true), 213 CLOCK_CELL(CK_SCMI_CSI, CK_CSI, "ck_csi", true), 214 CLOCK_CELL(CK_SCMI_LSE, CK_LSE, "ck_lse", true), 215 CLOCK_CELL(CK_SCMI_LSI, CK_LSI, "ck_lsi", true), 216 CLOCK_CELL(CK_SCMI_PLL2_Q, PLL2_Q, "pll2_q", true), 217 CLOCK_CELL(CK_SCMI_PLL2_R, PLL2_R, "pll2_r", true), 218 CLOCK_CELL(CK_SCMI_MPU, CK_MPU, "ck_mpu", true), 219 CLOCK_CELL(CK_SCMI_AXI, CK_AXI, "ck_axi", true), 220 CLOCK_CELL(CK_SCMI_BSEC, BSEC, "bsec", true), 221 CLOCK_CELL_DECPROT(CK_SCMI_CRYP1, CRYP1, "cryp1", false, 222 STM32MP1_ETZPC_CRYP1_ID), 223 CLOCK_CELL(CK_SCMI_GPIOZ, GPIOZ, "gpioz", false), 224 CLOCK_CELL_DECPROT(CK_SCMI_HASH1, HASH1, "hash1", false, 225 STM32MP1_ETZPC_HASH1_ID), 226 CLOCK_CELL_DECPROT(CK_SCMI_I2C4, I2C4_K, "i2c4_k", false, 227 STM32MP1_ETZPC_I2C4_ID), 228 CLOCK_CELL_DECPROT(CK_SCMI_I2C6, I2C6_K, "i2c6_k", false, 229 STM32MP1_ETZPC_I2C6_ID), 230 CLOCK_CELL_DECPROT(CK_SCMI_IWDG1, IWDG1, "iwdg1", false, 231 STM32MP1_ETZPC_IWDG1_ID), 232 CLOCK_CELL_DECPROT(CK_SCMI_RNG1, RNG1_K, "rng1_k", true, 233 STM32MP1_ETZPC_RNG1_ID), 234 CLOCK_CELL(CK_SCMI_RTC, RTC, "ck_rtc", true), 235 CLOCK_CELL(CK_SCMI_RTCAPB, RTCAPB, "rtcapb", true), 236 CLOCK_CELL_DECPROT(CK_SCMI_SPI6, SPI6_K, "spi6_k", false, 237 STM32MP1_ETZPC_SPI6_ID), 238 CLOCK_CELL_DECPROT(CK_SCMI_USART1, USART1_K, "usart1_k", false, 239 STM32MP1_ETZPC_USART1_ID), 240 }; 241 #endif 242 243 #ifdef CFG_STM32MP13 244 static struct stm32_scmi_rd stm32_scmi_reset_domain[] = { 245 RESET_CELL_DECPROT(RST_SCMI_LTDC, LTDC_R, "ltdc", 246 STM32MP1_ETZPC_LTDC_ID), 247 RESET_CELL(RST_SCMI_MDMA, MDMA_R, "mdma"), 248 }; 249 #endif 250 251 #ifdef CFG_STM32MP15 252 static struct stm32_scmi_rd stm32_scmi_reset_domain[] = { 253 RESET_CELL_DECPROT(RST_SCMI_SPI6, SPI6_R, "spi6", 254 STM32MP1_ETZPC_SPI6_ID), 255 RESET_CELL_DECPROT(RST_SCMI_I2C4, I2C4_R, "i2c4", 256 STM32MP1_ETZPC_I2C4_ID), 257 RESET_CELL_DECPROT(RST_SCMI_I2C6, I2C6_R, "i2c6", 258 STM32MP1_ETZPC_I2C6_ID), 259 RESET_CELL_DECPROT(RST_SCMI_USART1, USART1_R, "usart1", 260 STM32MP1_ETZPC_USART1_ID), 261 RESET_CELL_DECPROT(RST_SCMI_STGEN, STGEN_R, "stgen", 262 STM32MP1_ETZPC_STGENC_ID), 263 RESET_CELL_DECPROT(RST_SCMI_GPIOZ, GPIOZ_R, "gpioz", 264 ETZPC_ID_NEVER_ACCESSIBLE), 265 RESET_CELL_DECPROT(RST_SCMI_CRYP1, CRYP1_R, "cryp1", 266 STM32MP1_ETZPC_CRYP1_ID), 267 RESET_CELL_DECPROT(RST_SCMI_HASH1, HASH1_R, "hash1", 268 STM32MP1_ETZPC_HASH1_ID), 269 RESET_CELL_DECPROT(RST_SCMI_RNG1, RNG1_R, "rng1", 270 STM32MP1_ETZPC_RNG1_ID), 271 RESET_CELL(RST_SCMI_MDMA, MDMA_R, "mdma"), 272 RESET_CELL(RST_SCMI_MCU, MCU_R, "mcu"), 273 RESET_CELL(RST_SCMI_MCU_HOLD_BOOT, MCU_HOLD_BOOT_R, "mcu_hold_boot"), 274 }; 275 #endif 276 277 #ifdef CFG_STM32MP13 278 struct stm32_scmi_voltd scmi_voltage_domain[] = { 279 VOLTD_CELL_PWR(VOLTD_SCMI_REG11, PWR_REG11, "reg11"), 280 VOLTD_CELL_PWR(VOLTD_SCMI_REG18, PWR_REG18, "reg18"), 281 VOLTD_CELL_PWR(VOLTD_SCMI_USB33, PWR_USB33, "usb33"), 282 VOLTD_CELL_IOD(VOLTD_SCMI_SDMMC1_IO, IOD_SDMMC1, "sdmmc1"), 283 VOLTD_CELL_IOD(VOLTD_SCMI_SDMMC2_IO, IOD_SDMMC2, "sdmmc2"), 284 VOLTD_CELL_VREFBUF(VOLTD_SCMI_VREFBUF, "vrefbuf"), 285 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK1, "buck1", "buck1"), 286 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK2, "buck2", "buck2"), 287 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK3, "buck3", "buck3"), 288 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK4, "buck4", "buck4"), 289 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO1, "ldo1", "ldo1"), 290 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO2, "ldo2", "ldo2"), 291 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO3, "ldo3", "ldo3"), 292 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO4, "ldo4", "ldo4"), 293 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO5, "ldo5", "ldo5"), 294 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO6, "ldo6", "ldo6"), 295 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_VREFDDR, "vref_ddr", "vref_ddr"), 296 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BOOST, "boost", "bst_out"), 297 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_PWR_SW1, "pwr_sw1", "pwr_sw1"), 298 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_PWR_SW2, "pwr_sw2", "pwr_sw2"), 299 }; 300 #endif 301 302 #ifdef CFG_STM32MP15 303 struct stm32_scmi_voltd scmi_voltage_domain[] = { 304 VOLTD_CELL_PWR(VOLTD_SCMI_REG11, PWR_REG11, "reg11"), 305 VOLTD_CELL_PWR(VOLTD_SCMI_REG18, PWR_REG18, "reg18"), 306 VOLTD_CELL_PWR(VOLTD_SCMI_USB33, PWR_USB33, "usb33"), 307 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK1, "buck1", "vddcore"), 308 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK2, "buck2", "vdd_ddr"), 309 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK3, "buck3", "vdd"), 310 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK4, "buck4", "v3v3"), 311 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO1, "ldo1", "v1v8_audio"), 312 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO2, "ldo2", "v3v3_hdmi"), 313 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO3, "ldo3", "vtt_ddr"), 314 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO4, "ldo4", "vdd_usb"), 315 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO5, "ldo5", "vdda"), 316 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO6, "ldo6", "v1v2_hdmi"), 317 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_VREFDDR, "vref_ddr", "vref_ddr"), 318 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BOOST, "boost", "bst_out"), 319 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_PWR_SW1, "pwr_sw1", "vbus_otg"), 320 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_PWR_SW2, "pwr_sw2", "vbus_sw"), 321 }; 322 #endif 323 324 struct channel_resources { 325 struct scmi_msg_channel *channel; 326 struct stm32_scmi_clk *clock; 327 size_t clock_count; 328 struct stm32_scmi_rd *rd; 329 size_t rd_count; 330 struct stm32_scmi_voltd *voltd; 331 size_t voltd_count; 332 #ifdef CFG_SCMI_MSG_PERF_DOMAIN 333 struct stm32_scmi_perfd *perfd; 334 size_t perfd_count; 335 #endif 336 }; 337 338 #define PERFD_CELL(_scmi_id, _name) \ 339 [_scmi_id] = { \ 340 .name = (_name), \ 341 } 342 343 struct stm32_scmi_perfd __maybe_unused scmi_performance_domain[] = { 344 PERFD_CELL(0 /* PERFD_SCMI0_CPU_OPP */, "cpu-opp"), 345 }; 346 347 static const struct channel_resources scmi_channel[] = { 348 [0] = { 349 .channel = &(struct scmi_msg_channel){ 350 #ifdef SMT_BUFFER_BASE 351 .shm_addr = { .pa = SMT_BUFFER_BASE }, 352 .shm_size = SMT_BUF_SLOT_SIZE, 353 #endif 354 }, 355 .clock = stm32_scmi_clock, 356 .clock_count = ARRAY_SIZE(stm32_scmi_clock), 357 .rd = stm32_scmi_reset_domain, 358 .rd_count = ARRAY_SIZE(stm32_scmi_reset_domain), 359 .voltd = scmi_voltage_domain, 360 .voltd_count = ARRAY_SIZE(scmi_voltage_domain), 361 #ifdef CFG_SCMI_MSG_PERF_DOMAIN 362 .perfd = scmi_performance_domain, 363 .perfd_count = ARRAY_SIZE(scmi_performance_domain), 364 #endif 365 }, 366 }; 367 368 static const struct channel_resources *find_resource(unsigned int channel_id) 369 { 370 assert(channel_id < ARRAY_SIZE(scmi_channel)); 371 372 return scmi_channel + channel_id; 373 } 374 375 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int channel_id) 376 { 377 const size_t max_id = ARRAY_SIZE(scmi_channel); 378 unsigned int confined_id = confine_array_index(channel_id, max_id); 379 380 if (channel_id >= max_id) 381 return NULL; 382 383 return find_resource(confined_id)->channel; 384 } 385 386 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 387 { 388 unsigned int n = 0; 389 unsigned int count = 0; 390 const size_t channel_count = ARRAY_SIZE(scmi_channel); 391 392 for (n = 0; n < channel_count; n++) 393 if (scmi_channel[n].clock_count) 394 break; 395 if (n < channel_count) 396 count++; 397 398 for (n = 0; n < channel_count; n++) 399 if (scmi_channel[n].rd_count) 400 break; 401 if (n < channel_count) 402 count++; 403 404 for (n = 0; n < channel_count; n++) 405 if (scmi_channel[n].voltd_count) 406 break; 407 if (n < channel_count) 408 count++; 409 410 #ifdef CFG_SCMI_MSG_PERF_DOMAIN 411 for (n = 0; n < channel_count; n++) 412 if (scmi_channel[n].perfd_count) 413 break; 414 if (n < channel_count) 415 count++; 416 #endif 417 418 return count; 419 } 420 421 static const char vendor[] = "ST"; 422 static const char sub_vendor[] = ""; 423 424 const char *plat_scmi_vendor_name(void) 425 { 426 return vendor; 427 } 428 429 const char *plat_scmi_sub_vendor_name(void) 430 { 431 return sub_vendor; 432 } 433 434 /* Currently supporting Clocks and Reset Domains */ 435 static const uint8_t plat_protocol_list[] = { 436 SCMI_PROTOCOL_ID_CLOCK, 437 SCMI_PROTOCOL_ID_RESET_DOMAIN, 438 SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, 439 #ifdef CFG_SCMI_MSG_PERF_DOMAIN 440 SCMI_PROTOCOL_ID_PERF, 441 #endif 442 0 /* Null termination */ 443 }; 444 445 size_t plat_scmi_protocol_count(void) 446 { 447 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 448 449 assert(count == plat_scmi_protocol_count_paranoid()); 450 451 return count; 452 } 453 454 const uint8_t *plat_scmi_protocol_list(unsigned int channel_id __unused) 455 { 456 assert(plat_scmi_protocol_count_paranoid() == 457 (ARRAY_SIZE(plat_protocol_list) - 1)); 458 459 return plat_protocol_list; 460 } 461 462 static bool nsec_can_access_resource(unsigned int etzpc_id) 463 { 464 static struct firewall_controller *etzpc_fw_ctrl; 465 uint32_t query_arg = DECPROT(etzpc_id, DECPROT_NS_RW, DECPROT_UNLOCK); 466 struct firewall_query query = { 467 .arg_count = 1, 468 .args = &query_arg, 469 .ctrl = etzpc_fw_ctrl, 470 }; 471 472 if (etzpc_id == ETZPC_ID_NEVER_ACCESSIBLE) 473 return false; 474 if (etzpc_id == ETZPC_ID_ALWAYS_ACCESSIBLE) 475 return true; 476 477 if (!etzpc_fw_ctrl) { 478 struct dt_driver_provider *prov = NULL; 479 int node = 0; 480 481 node = fdt_node_offset_by_compatible(get_embedded_dt(), -1, 482 "st,stm32-etzpc"); 483 if (node < 0) 484 panic(); 485 486 prov = dt_driver_get_provider_by_node(node, DT_DRIVER_FIREWALL); 487 if (!prov) 488 panic(); 489 490 etzpc_fw_ctrl = dt_driver_provider_priv_data(prov); 491 query.ctrl = etzpc_fw_ctrl; 492 } 493 494 return firewall_check_access(&query) == TEE_SUCCESS; 495 } 496 497 /* 498 * Platform SCMI clocks 499 */ 500 static struct stm32_scmi_clk *find_clock(unsigned int channel_id, 501 unsigned int scmi_id) 502 { 503 const struct channel_resources *resource = find_resource(channel_id); 504 size_t n = 0; 505 506 if (resource) { 507 for (n = 0; n < resource->clock_count; n++) 508 if (n == scmi_id) 509 return &resource->clock[n]; 510 } 511 512 return NULL; 513 } 514 515 size_t plat_scmi_clock_count(unsigned int channel_id) 516 { 517 const struct channel_resources *resource = find_resource(channel_id); 518 519 if (!resource) 520 return 0; 521 522 return resource->clock_count; 523 } 524 525 const char *plat_scmi_clock_get_name(unsigned int channel_id, 526 unsigned int scmi_id) 527 { 528 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 529 530 if (!clock || !nsec_can_access_resource(clock->etzpc_id)) 531 return NULL; 532 533 return clock->name; 534 } 535 536 int32_t plat_scmi_clock_rates_array(unsigned int channel_id, 537 unsigned int scmi_id, size_t start_index, 538 unsigned long *array, size_t *nb_elts) 539 { 540 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 541 542 if (!clock) 543 return SCMI_NOT_FOUND; 544 545 if (!nsec_can_access_resource(clock->etzpc_id)) 546 return SCMI_DENIED; 547 548 /* Exposed clocks are currently fixed rate clocks */ 549 if (start_index) 550 return SCMI_INVALID_PARAMETERS; 551 552 if (!array) 553 *nb_elts = 1; 554 else if (*nb_elts == 1) 555 *array = clk_get_rate(clock->clk); 556 else 557 return SCMI_GENERIC_ERROR; 558 559 return SCMI_SUCCESS; 560 } 561 562 unsigned long plat_scmi_clock_get_rate(unsigned int channel_id, 563 unsigned int scmi_id) 564 { 565 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 566 567 if (!clock || !nsec_can_access_resource(clock->etzpc_id)) 568 return 0; 569 570 return clk_get_rate(clock->clk); 571 } 572 573 int32_t plat_scmi_clock_get_state(unsigned int channel_id, unsigned int scmi_id) 574 { 575 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 576 577 if (!clock || !nsec_can_access_resource(clock->etzpc_id)) 578 return 0; 579 580 return (int32_t)clock->enabled; 581 } 582 583 int32_t plat_scmi_clock_set_state(unsigned int channel_id, unsigned int scmi_id, 584 bool enable_not_disable) 585 { 586 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 587 588 if (!clock) 589 return SCMI_NOT_FOUND; 590 591 if (!nsec_can_access_resource(clock->etzpc_id)) 592 return SCMI_DENIED; 593 594 if (enable_not_disable) { 595 if (!clock->enabled) { 596 FMSG("SCMI clock %u enable", scmi_id); 597 clk_enable(clock->clk); 598 clock->enabled = true; 599 } 600 } else { 601 if (clock->enabled) { 602 FMSG("SCMI clock %u disable", scmi_id); 603 clk_disable(clock->clk); 604 clock->enabled = false; 605 } 606 } 607 608 return SCMI_SUCCESS; 609 } 610 611 /* 612 * Platform SCMI reset domains 613 */ 614 static struct stm32_scmi_rd *find_rd(unsigned int channel_id, 615 unsigned int scmi_id) 616 { 617 const struct channel_resources *resource = find_resource(channel_id); 618 size_t n = 0; 619 620 if (resource) { 621 for (n = 0; n < resource->rd_count; n++) 622 if (n == scmi_id) 623 return &resource->rd[n]; 624 } 625 626 return NULL; 627 } 628 629 const char *plat_scmi_rd_get_name(unsigned int channel_id, unsigned int scmi_id) 630 { 631 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 632 633 if (!rd) 634 return NULL; 635 636 return rd->name; 637 } 638 639 size_t plat_scmi_rd_count(unsigned int channel_id) 640 { 641 const struct channel_resources *resource = find_resource(channel_id); 642 643 if (!resource) 644 return 0; 645 646 return resource->rd_count; 647 } 648 649 int32_t plat_scmi_rd_autonomous(unsigned int channel_id, unsigned int scmi_id, 650 uint32_t state) 651 { 652 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 653 654 if (!rd) 655 return SCMI_NOT_FOUND; 656 657 if (!rd->rstctrl || !nsec_can_access_resource(rd->etzpc_id)) 658 return SCMI_DENIED; 659 660 #ifdef CFG_STM32MP15 661 /* Reset cycle on MCU hold boot is not supported */ 662 if (rd->reset_id == MCU_HOLD_BOOT_R) 663 return SCMI_NOT_SUPPORTED; 664 /* Remoteproc driver may handle all MCU reset controllers */ 665 if (rd->reset_id == MCU_R && stm32_rproc_is_secure(STM32_M4_RPROC_ID)) 666 return SCMI_DENIED; 667 #endif 668 669 /* Supports only reset with context loss */ 670 if (state) 671 return SCMI_NOT_SUPPORTED; 672 673 FMSG("SCMI reset %u cycle", scmi_id); 674 675 if (rstctrl_assert_to(rd->rstctrl, TIMEOUT_US_1MS)) 676 return SCMI_HARDWARE_ERROR; 677 678 if (rstctrl_deassert_to(rd->rstctrl, TIMEOUT_US_1MS)) 679 return SCMI_HARDWARE_ERROR; 680 681 return SCMI_SUCCESS; 682 } 683 684 int32_t plat_scmi_rd_set_state(unsigned int channel_id, unsigned int scmi_id, 685 bool assert_not_deassert) 686 { 687 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 688 TEE_Result res = TEE_ERROR_GENERIC; 689 690 if (!rd) 691 return SCMI_NOT_FOUND; 692 693 if (!rd->rstctrl || !nsec_can_access_resource(rd->etzpc_id)) 694 return SCMI_DENIED; 695 696 #ifdef CFG_STM32MP15 697 /* Remoteproc driver may handle all MCU reset controllers */ 698 if ((rd->reset_id == MCU_R || rd->reset_id == MCU_HOLD_BOOT_R) && 699 stm32_rproc_is_secure(STM32_M4_RPROC_ID)) 700 return SCMI_DENIED; 701 #endif 702 703 if (assert_not_deassert) { 704 FMSG("SCMI reset %u set", scmi_id); 705 res = rstctrl_assert(rd->rstctrl); 706 } else { 707 FMSG("SCMI reset %u release", scmi_id); 708 res = rstctrl_deassert(rd->rstctrl); 709 } 710 711 if (res) 712 return SCMI_HARDWARE_ERROR; 713 714 return SCMI_SUCCESS; 715 } 716 717 /* 718 * Platform SCMI voltage domains 719 */ 720 static struct stm32_scmi_voltd *find_voltd(unsigned int channel_id, 721 unsigned int scmi_id) 722 { 723 const struct channel_resources *resource = find_resource(channel_id); 724 size_t n = 0; 725 726 if (resource) { 727 for (n = 0; n < resource->voltd_count; n++) 728 if (n == scmi_id) 729 return &resource->voltd[n]; 730 } 731 732 return NULL; 733 } 734 735 size_t plat_scmi_voltd_count(unsigned int channel_id) 736 { 737 const struct channel_resources *resource = find_resource(channel_id); 738 739 if (!resource) 740 return 0; 741 742 return resource->voltd_count; 743 } 744 745 const char *plat_scmi_voltd_get_name(unsigned int channel_id, 746 unsigned int scmi_id) 747 { 748 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 749 750 /* Currently non-secure is allowed to access all PWR regulators */ 751 if (!voltd) 752 return NULL; 753 754 return voltd->name; 755 } 756 757 int32_t plat_scmi_voltd_levels_array(unsigned int channel_id, 758 unsigned int scmi_id, size_t start_index, 759 long *out_levels, size_t *nb_elts) 760 761 { 762 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 763 764 if (!voltd) 765 return SCMI_NOT_FOUND; 766 767 if (voltd->regulator) { 768 struct regulator_voltages_desc *desc = NULL; 769 TEE_Result res = TEE_ERROR_GENERIC; 770 const int *levels = NULL; 771 size_t n = 0; 772 773 res = regulator_supported_voltages(voltd->regulator, &desc, 774 &levels); 775 if (res == TEE_ERROR_NOT_SUPPORTED) 776 return SCMI_NOT_SUPPORTED; 777 if (res) 778 return SCMI_GENERIC_ERROR; 779 if (!desc || desc->type != VOLTAGE_TYPE_FULL_LIST) { 780 /* 781 * Triplet min/max/step description. Caller should use 782 * plat_scmi_voltd_levels_by_step(). 783 */ 784 return SCMI_NOT_SUPPORTED; 785 } 786 787 if (start_index >= desc->num_levels) 788 return SCMI_OUT_OF_RANGE; 789 790 if (!*nb_elts) { 791 *nb_elts = desc->num_levels - start_index; 792 return SCMI_SUCCESS; 793 } 794 795 *nb_elts = MIN(*nb_elts, desc->num_levels - start_index); 796 for (n = 0; n < *nb_elts; n++) 797 out_levels[n] = levels[start_index + n]; 798 799 return SCMI_SUCCESS; 800 } 801 802 return SCMI_DENIED; 803 } 804 805 int32_t plat_scmi_voltd_levels_by_step(unsigned int channel_id, 806 unsigned int scmi_id, long *min_max_step) 807 { 808 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 809 810 if (!voltd) 811 return SCMI_NOT_FOUND; 812 813 if (voltd->regulator) { 814 struct regulator_voltages_desc *desc = NULL; 815 TEE_Result res = TEE_ERROR_GENERIC; 816 const int *levels = NULL; 817 818 res = regulator_supported_voltages(voltd->regulator, &desc, 819 &levels); 820 if (res == TEE_ERROR_NOT_SUPPORTED) 821 return SCMI_NOT_SUPPORTED; 822 if (res) 823 return SCMI_GENERIC_ERROR; 824 if (!desc || desc->type != VOLTAGE_TYPE_INCREMENT) { 825 /* 826 * Triplet min/max/step description. Caller should use 827 * plat_scmi_voltd_levels_by_step(). 828 */ 829 return SCMI_NOT_SUPPORTED; 830 } 831 832 min_max_step[0] = levels[0]; 833 min_max_step[1] = levels[1]; 834 min_max_step[2] = levels[2]; 835 836 return SCMI_SUCCESS; 837 } 838 839 return SCMI_NOT_SUPPORTED; 840 } 841 842 int32_t plat_scmi_voltd_get_level(unsigned int channel_id, unsigned int scmi_id, 843 long *level_uv) 844 { 845 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 846 847 if (!voltd) 848 return SCMI_INVALID_PARAMETERS; 849 850 if (voltd->regulator) { 851 *level_uv = regulator_get_voltage(voltd->regulator); 852 return SCMI_SUCCESS; 853 } 854 855 return SCMI_DENIED; 856 } 857 858 int32_t plat_scmi_voltd_set_level(unsigned int channel_id, unsigned int scmi_id, 859 long level_uv) 860 { 861 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 862 863 if (!voltd) 864 return SCMI_NOT_FOUND; 865 866 if (voltd->regulator) { 867 TEE_Result res = TEE_ERROR_GENERIC; 868 869 if (level_uv < INT_MIN || level_uv > INT_MAX) 870 return SCMI_OUT_OF_RANGE; 871 872 res = regulator_set_voltage(voltd->regulator, level_uv); 873 if (res) 874 return SCMI_GENERIC_ERROR; 875 else 876 return SCMI_SUCCESS; 877 } 878 879 return SCMI_DENIED; 880 } 881 882 int32_t plat_scmi_voltd_get_config(unsigned int channel_id, 883 unsigned int scmi_id, uint32_t *config) 884 { 885 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 886 887 if (!voltd) 888 return SCMI_NOT_FOUND; 889 890 if (voltd->regulator) { 891 if (voltd->state) 892 *config = SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 893 else 894 *config = SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 895 896 return SCMI_SUCCESS; 897 } 898 899 return SCMI_DENIED; 900 } 901 902 int32_t plat_scmi_voltd_set_config(unsigned int channel_id, 903 unsigned int scmi_id, uint32_t config) 904 { 905 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 906 907 if (!voltd) 908 return SCMI_NOT_FOUND; 909 910 if (voltd->regulator) { 911 switch (config) { 912 case SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON: 913 if (!voltd->state) { 914 if (regulator_enable(voltd->regulator)) 915 return SCMI_GENERIC_ERROR; 916 917 voltd->state = true; 918 } 919 break; 920 case SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF: 921 if (voltd->state) { 922 if (regulator_disable(voltd->regulator)) 923 return SCMI_GENERIC_ERROR; 924 925 voltd->state = false; 926 } 927 break; 928 default: 929 return SCMI_INVALID_PARAMETERS; 930 } 931 932 return SCMI_SUCCESS; 933 } 934 935 return SCMI_DENIED; 936 } 937 938 static void get_voltd_regulator(struct stm32_scmi_voltd *voltd) 939 { 940 switch (voltd->priv_dev) { 941 case VOLTD_PWR: 942 voltd->regulator = stm32mp1_pwr_get_regulator(voltd->priv_id); 943 break; 944 case VOLTD_PMIC: 945 voltd->regulator = stm32mp_pmic_get_regulator(voltd->priv_name); 946 break; 947 case VOLTD_VREFBUF: 948 voltd->regulator = stm32_vrefbuf_regulator(); 949 break; 950 case VOLTD_IOD: 951 voltd->regulator = stm32mp1_get_iod_regulator(voltd->priv_id); 952 break; 953 default: 954 break; 955 } 956 957 if (voltd->regulator && voltd->regulator->flags & REGULATOR_BOOT_ON) 958 regulator_enable(voltd->regulator); 959 } 960 961 #ifdef CFG_SCMI_MSG_PERF_DOMAIN 962 /* 963 * Platform SCMI performance domains 964 * 965 * Note: currently exposes a single performance domain that is the CPU DVFS 966 * operating point. Non-secure is allowed to access this performance domain. 967 */ 968 static struct stm32_scmi_perfd *find_perfd(unsigned int channel_id, 969 unsigned int domain_id) 970 { 971 const struct channel_resources *resource = find_resource(channel_id); 972 size_t n = 0; 973 974 if (resource) { 975 for (n = 0; n < resource->perfd_count; n++) 976 if (n == domain_id) 977 return &resource->perfd[n]; 978 } 979 980 return NULL; 981 } 982 983 size_t plat_scmi_perf_count(unsigned int channel_id) 984 { 985 const struct channel_resources *resource = find_resource(channel_id); 986 987 if (!resource) 988 return 0; 989 990 return resource->perfd_count; 991 } 992 993 const char *plat_scmi_perf_domain_name(unsigned int channel_id, 994 unsigned int domain_id) 995 { 996 struct stm32_scmi_perfd *perfd = find_perfd(channel_id, domain_id); 997 998 if (!perfd) 999 return NULL; 1000 1001 return perfd->name; 1002 } 1003 1004 int32_t plat_scmi_perf_sustained_freq(unsigned int channel_id, 1005 unsigned int domain_id, 1006 unsigned int *freq) 1007 { 1008 struct stm32_scmi_perfd *perfd = find_perfd(channel_id, domain_id); 1009 1010 if (!perfd) 1011 return SCMI_NOT_FOUND; 1012 1013 *freq = stm32_cpu_opp_sustained_level(); 1014 1015 return SCMI_SUCCESS; 1016 } 1017 1018 int32_t plat_scmi_perf_level_latency(unsigned int channel_id, 1019 unsigned int domain_id, 1020 unsigned int level __unused, 1021 unsigned int *latency) 1022 { 1023 struct stm32_scmi_perfd *perfd = find_perfd(channel_id, domain_id); 1024 1025 if (!perfd) 1026 return SCMI_NOT_FOUND; 1027 1028 *latency = CFG_STM32MP_OPP_LATENCY_US; 1029 1030 return SCMI_SUCCESS; 1031 } 1032 1033 int32_t plat_scmi_perf_levels_array(unsigned int channel_id, 1034 unsigned int domain_id, size_t start_index, 1035 unsigned int *levels, size_t *nb_elts) 1036 { 1037 struct stm32_scmi_perfd *perfd = find_perfd(channel_id, domain_id); 1038 size_t full_count = 0; 1039 size_t out_count = 0; 1040 size_t n = 0; 1041 1042 if (!perfd) 1043 return SCMI_NOT_FOUND; 1044 1045 full_count = stm32_cpu_opp_count(); 1046 if (SUB_OVERFLOW(full_count, start_index, &out_count)) 1047 return SCMI_OUT_OF_RANGE; 1048 1049 if (!levels) { 1050 *nb_elts = full_count - start_index; 1051 1052 return SCMI_SUCCESS; 1053 } 1054 1055 out_count = MIN(out_count, *nb_elts); 1056 1057 FMSG("%zu levels: start %zu requested %zu output %zu", 1058 full_count, start_index, *nb_elts, out_count); 1059 1060 for (n = 0; n < out_count; n++) 1061 levels[n] = stm32_cpu_opp_level(start_index + n); 1062 1063 *nb_elts = out_count; 1064 1065 return SCMI_SUCCESS; 1066 } 1067 1068 int32_t plat_scmi_perf_level_get(unsigned int channel_id, 1069 unsigned int domain_id, unsigned int *level) 1070 { 1071 struct stm32_scmi_perfd *perfd = find_perfd(channel_id, domain_id); 1072 unsigned int current_level = 0; 1073 1074 if (!perfd) 1075 return SCMI_NOT_FOUND; 1076 1077 if (stm32_cpu_opp_read_level(¤t_level)) 1078 return SCMI_GENERIC_ERROR; 1079 1080 *level = current_level; 1081 1082 return SCMI_SUCCESS; 1083 } 1084 1085 int32_t plat_scmi_perf_level_set(unsigned int channel_id, 1086 unsigned int domain_id, unsigned int level) 1087 { 1088 struct stm32_scmi_perfd *perfd = find_perfd(channel_id, domain_id); 1089 1090 if (!perfd) 1091 return SCMI_NOT_FOUND; 1092 1093 switch (stm32_cpu_opp_set_level(level)) { 1094 case TEE_SUCCESS: 1095 return SCMI_SUCCESS; 1096 case TEE_ERROR_BAD_PARAMETERS: 1097 return SCMI_OUT_OF_RANGE; 1098 default: 1099 return SCMI_GENERIC_ERROR; 1100 } 1101 } 1102 #endif 1103 1104 /* 1105 * Initialize platform SCMI resources 1106 */ 1107 static TEE_Result stm32mp1_init_scmi_server(void) 1108 { 1109 size_t i = 0; 1110 size_t j = 0; 1111 1112 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 1113 const struct channel_resources *res = scmi_channel + i; 1114 struct scmi_msg_channel *chan = res->channel; 1115 1116 if (chan->shm_addr.pa) { 1117 struct io_pa_va *addr = &chan->shm_addr; 1118 1119 /* Enforce non-secure shm mapped as device memory */ 1120 addr->va = (vaddr_t)phys_to_virt(addr->pa, 1121 MEM_AREA_IO_NSEC, 1122 chan->shm_size); 1123 assert(addr->va); 1124 1125 scmi_smt_init_agent_channel(chan); 1126 } 1127 1128 for (j = 0; j < res->clock_count; j++) { 1129 struct stm32_scmi_clk *clk = &res->clock[j]; 1130 1131 if (!clk->name || 1132 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 1133 panic("SCMI clock name invalid"); 1134 1135 clk->clk = stm32mp_rcc_clock_id_to_clk(clk->clock_id); 1136 assert(clk->clk); 1137 1138 /* Sync SCMI clocks with their targeted initial state */ 1139 if (clk->enabled && 1140 nsec_can_access_resource(clk->etzpc_id)) 1141 clk_enable(clk->clk); 1142 } 1143 1144 for (j = 0; j < res->rd_count; j++) { 1145 struct stm32_scmi_rd *rd = &res->rd[j]; 1146 struct rstctrl *rstctrl = NULL; 1147 1148 if (!rd->name || 1149 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 1150 panic("SCMI reset domain name invalid"); 1151 1152 rstctrl = stm32mp_rcc_reset_id_to_rstctrl(rd->reset_id); 1153 assert(rstctrl); 1154 if (rstctrl_get_exclusive(rstctrl)) 1155 continue; 1156 1157 rd->rstctrl = rstctrl; 1158 } 1159 1160 for (j = 0; j < res->voltd_count; j++) { 1161 struct stm32_scmi_voltd *voltd = &res->voltd[j]; 1162 1163 if (!voltd->name || 1164 strlen(voltd->name) >= SCMI_VOLTD_NAME_SIZE) 1165 panic("SCMI voltage domain name invalid"); 1166 1167 get_voltd_regulator(voltd); 1168 } 1169 } 1170 1171 return TEE_SUCCESS; 1172 } 1173 1174 driver_init_late(stm32mp1_init_scmi_server); 1175