1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <confine_array_index.h> 8 #include <drivers/scmi-msg.h> 9 #include <drivers/scmi.h> 10 #include <drivers/stm32mp1_pmic.h> 11 #include <drivers/stm32mp1_pwr.h> 12 #include <drivers/stpmic1.h> 13 #include <dt-bindings/clock/stm32mp1-clks.h> 14 #include <dt-bindings/regulator/st,stm32mp15-regulator.h> 15 #include <dt-bindings/reset/stm32mp1-resets.h> 16 #include <initcall.h> 17 #include <mm/core_memprot.h> 18 #include <mm/core_mmu.h> 19 #include <platform_config.h> 20 #include <stdint.h> 21 #include <speculation_barrier.h> 22 #include <stm32_util.h> 23 #include <string.h> 24 #include <tee_api_defines.h> 25 #include <util.h> 26 27 #define TIMEOUT_US_1MS 1000 28 29 #define SCMI_CLOCK_NAME_SIZE 16 30 #define SCMI_RD_NAME_SIZE 16 31 #define SCMI_VOLTD_NAME_SIZE 16 32 33 /* 34 * struct stm32_scmi_clk - Data for the exposed clock 35 * @clock_id: Clock identifier in RCC clock driver 36 * @name: Clock string ID exposed to channel 37 * @enabled: State of the SCMI clock 38 */ 39 struct stm32_scmi_clk { 40 unsigned long clock_id; 41 const char *name; 42 bool enabled; 43 }; 44 45 /* 46 * struct stm32_scmi_rd - Data for the exposed reset controller 47 * @reset_id: Reset identifier in RCC reset driver 48 * @name: Reset string ID exposed to channel 49 */ 50 struct stm32_scmi_rd { 51 unsigned long reset_id; 52 const char *name; 53 }; 54 55 enum voltd_device { 56 VOLTD_PWR, 57 VOLTD_PMIC, 58 }; 59 60 /* 61 * struct stm32_scmi_voltd - Data for the exposed voltage domains 62 * @name: Power regulator string ID exposed to channel 63 * @priv_id: Internal string ID for the regulator 64 * @priv_dev: Internal ID for the device implementing the regulator 65 */ 66 struct stm32_scmi_voltd { 67 const char *name; 68 const char *priv_id; 69 enum voltd_device priv_dev; 70 71 }; 72 73 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 74 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 75 #define SMT_BUFFER0_BASE SMT_BUFFER_BASE 76 #define SMT_BUFFER1_BASE (SMT_BUFFER_BASE + 0x200) 77 78 #if (SMT_BUFFER1_BASE + SMT_BUF_SLOT_SIZE > \ 79 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 80 #error "SCMI shared memory mismatch" 81 #endif 82 83 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 84 CFG_STM32MP1_SCMI_SHM_SIZE); 85 86 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 87 [_scmi_id] = { \ 88 .clock_id = _id, \ 89 .name = _name, \ 90 .enabled = _init_enabled, \ 91 } 92 93 static struct stm32_scmi_clk stm32_scmi0_clock[] = { 94 CLOCK_CELL(CK_SCMI0_HSE, CK_HSE, "ck_hse", true), 95 CLOCK_CELL(CK_SCMI0_HSI, CK_HSI, "ck_hsi", true), 96 CLOCK_CELL(CK_SCMI0_CSI, CK_CSI, "ck_csi", true), 97 CLOCK_CELL(CK_SCMI0_LSE, CK_LSE, "ck_lse", true), 98 CLOCK_CELL(CK_SCMI0_LSI, CK_LSI, "ck_lsi", true), 99 CLOCK_CELL(CK_SCMI0_PLL2_Q, PLL2_Q, "pll2_q", true), 100 CLOCK_CELL(CK_SCMI0_PLL2_R, PLL2_R, "pll2_r", true), 101 CLOCK_CELL(CK_SCMI0_MPU, CK_MPU, "ck_mpu", true), 102 CLOCK_CELL(CK_SCMI0_AXI, CK_AXI, "ck_axi", true), 103 CLOCK_CELL(CK_SCMI0_BSEC, BSEC, "bsec", true), 104 CLOCK_CELL(CK_SCMI0_CRYP1, CRYP1, "cryp1", false), 105 CLOCK_CELL(CK_SCMI0_GPIOZ, GPIOZ, "gpioz", false), 106 CLOCK_CELL(CK_SCMI0_HASH1, HASH1, "hash1", false), 107 CLOCK_CELL(CK_SCMI0_I2C4, I2C4_K, "i2c4_k", false), 108 CLOCK_CELL(CK_SCMI0_I2C6, I2C6_K, "i2c6_k", false), 109 CLOCK_CELL(CK_SCMI0_IWDG1, IWDG1, "iwdg1", false), 110 CLOCK_CELL(CK_SCMI0_RNG1, RNG1_K, "rng1_k", true), 111 CLOCK_CELL(CK_SCMI0_RTC, RTC, "ck_rtc", true), 112 CLOCK_CELL(CK_SCMI0_RTCAPB, RTCAPB, "rtcapb", true), 113 CLOCK_CELL(CK_SCMI0_SPI6, SPI6_K, "spi6_k", false), 114 CLOCK_CELL(CK_SCMI0_USART1, USART1_K, "usart1_k", false), 115 }; 116 117 static struct stm32_scmi_clk stm32_scmi1_clock[] = { 118 CLOCK_CELL(CK_SCMI1_PLL3_Q, PLL3_Q, "pll3_q", true), 119 CLOCK_CELL(CK_SCMI1_PLL3_R, PLL3_R, "pll3_r", true), 120 CLOCK_CELL(CK_SCMI1_MCU, CK_MCU, "ck_mcu", false), 121 }; 122 123 #define RESET_CELL(_scmi_id, _id, _name) \ 124 [_scmi_id] = { \ 125 .reset_id = _id, \ 126 .name = _name, \ 127 } 128 129 static struct stm32_scmi_rd stm32_scmi0_reset_domain[] = { 130 RESET_CELL(RST_SCMI0_SPI6, SPI6_R, "spi6"), 131 RESET_CELL(RST_SCMI0_I2C4, I2C4_R, "i2c4"), 132 RESET_CELL(RST_SCMI0_I2C6, I2C6_R, "i2c6"), 133 RESET_CELL(RST_SCMI0_USART1, USART1_R, "usart1"), 134 RESET_CELL(RST_SCMI0_STGEN, STGEN_R, "stgen"), 135 RESET_CELL(RST_SCMI0_GPIOZ, GPIOZ_R, "gpioz"), 136 RESET_CELL(RST_SCMI0_CRYP1, CRYP1_R, "cryp1"), 137 RESET_CELL(RST_SCMI0_HASH1, HASH1_R, "hash1"), 138 RESET_CELL(RST_SCMI0_RNG1, RNG1_R, "rng1"), 139 RESET_CELL(RST_SCMI0_MDMA, MDMA_R, "mdma"), 140 RESET_CELL(RST_SCMI0_MCU, MCU_R, "mcu"), 141 RESET_CELL(RST_SCMI0_MCU_HOLD_BOOT, MCU_HOLD_BOOT_R, "mcu_hold_boot"), 142 }; 143 144 #define VOLTD_CELL(_scmi_id, _dev_id, _priv_id, _name) \ 145 [_scmi_id] = { \ 146 .priv_id = (_priv_id), \ 147 .priv_dev = (_dev_id), \ 148 .name = (_name), \ 149 } 150 151 #define PWR_REG11_NAME_ID "0" 152 #define PWR_REG18_NAME_ID "1" 153 #define PWR_USB33_NAME_ID "2" 154 155 struct stm32_scmi_voltd scmi0_voltage_domain[] = { 156 VOLTD_CELL(VOLTD_SCMI0_REG11, VOLTD_PWR, PWR_REG11_NAME_ID, "reg11"), 157 VOLTD_CELL(VOLTD_SCMI0_REG18, VOLTD_PWR, PWR_REG18_NAME_ID, "reg18"), 158 VOLTD_CELL(VOLTD_SCMI0_USB33, VOLTD_PWR, PWR_USB33_NAME_ID, "usb33"), 159 }; 160 161 struct channel_resources { 162 struct scmi_msg_channel *channel; 163 struct stm32_scmi_clk *clock; 164 size_t clock_count; 165 struct stm32_scmi_rd *rd; 166 size_t rd_count; 167 struct stm32_scmi_voltd *voltd; 168 size_t voltd_count; 169 }; 170 171 static const struct channel_resources scmi_channel[] = { 172 [0] = { 173 .channel = &(struct scmi_msg_channel){ 174 .shm_addr = { .pa = SMT_BUFFER0_BASE }, 175 .shm_size = SMT_BUF_SLOT_SIZE, 176 }, 177 .clock = stm32_scmi0_clock, 178 .clock_count = ARRAY_SIZE(stm32_scmi0_clock), 179 .rd = stm32_scmi0_reset_domain, 180 .rd_count = ARRAY_SIZE(stm32_scmi0_reset_domain), 181 .voltd = scmi0_voltage_domain, 182 .voltd_count = ARRAY_SIZE(scmi0_voltage_domain), 183 }, 184 [1] = { 185 .channel = &(struct scmi_msg_channel){ 186 .shm_addr = { .pa = SMT_BUFFER1_BASE }, 187 .shm_size = SMT_BUF_SLOT_SIZE, 188 }, 189 .clock = stm32_scmi1_clock, 190 .clock_count = ARRAY_SIZE(stm32_scmi1_clock), 191 }, 192 }; 193 194 static const struct channel_resources *find_resource(unsigned int channel_id) 195 { 196 assert(channel_id < ARRAY_SIZE(scmi_channel)); 197 198 return scmi_channel + channel_id; 199 } 200 201 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int channel_id) 202 { 203 const size_t max_id = ARRAY_SIZE(scmi_channel); 204 unsigned int confined_id = confine_array_index(channel_id, max_id); 205 206 if (channel_id >= max_id) 207 return NULL; 208 209 return find_resource(confined_id)->channel; 210 } 211 212 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 213 { 214 unsigned int n = 0; 215 unsigned int count = 0; 216 const size_t channel_count = ARRAY_SIZE(scmi_channel); 217 218 for (n = 0; n < channel_count; n++) 219 if (scmi_channel[n].clock_count) 220 break; 221 if (n < channel_count) 222 count++; 223 224 for (n = 0; n < channel_count; n++) 225 if (scmi_channel[n].rd_count) 226 break; 227 if (n < channel_count) 228 count++; 229 230 for (n = 0; n < channel_count; n++) 231 if (scmi_channel[n].voltd_count) 232 break; 233 if (n < channel_count) 234 count++; 235 236 return count; 237 } 238 239 static const char vendor[] = "ST"; 240 static const char sub_vendor[] = ""; 241 242 const char *plat_scmi_vendor_name(void) 243 { 244 return vendor; 245 } 246 247 const char *plat_scmi_sub_vendor_name(void) 248 { 249 return sub_vendor; 250 } 251 252 /* Currently supporting Clocks and Reset Domains */ 253 static const uint8_t plat_protocol_list[] = { 254 SCMI_PROTOCOL_ID_CLOCK, 255 SCMI_PROTOCOL_ID_RESET_DOMAIN, 256 SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, 257 0 /* Null termination */ 258 }; 259 260 size_t plat_scmi_protocol_count(void) 261 { 262 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 263 264 assert(count == plat_scmi_protocol_count_paranoid()); 265 266 return count; 267 } 268 269 const uint8_t *plat_scmi_protocol_list(unsigned int channel_id __unused) 270 { 271 assert(plat_scmi_protocol_count_paranoid() == 272 (ARRAY_SIZE(plat_protocol_list) - 1)); 273 274 return plat_protocol_list; 275 } 276 277 /* 278 * Platform SCMI clocks 279 */ 280 static struct stm32_scmi_clk *find_clock(unsigned int channel_id, 281 unsigned int scmi_id) 282 { 283 const struct channel_resources *resource = find_resource(channel_id); 284 size_t n = 0; 285 286 if (resource) { 287 for (n = 0; n < resource->clock_count; n++) 288 if (n == scmi_id) 289 return &resource->clock[n]; 290 } 291 292 return NULL; 293 } 294 295 size_t plat_scmi_clock_count(unsigned int channel_id) 296 { 297 const struct channel_resources *resource = find_resource(channel_id); 298 299 if (!resource) 300 return 0; 301 302 return resource->clock_count; 303 } 304 305 const char *plat_scmi_clock_get_name(unsigned int channel_id, 306 unsigned int scmi_id) 307 { 308 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 309 310 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 311 return NULL; 312 313 return clock->name; 314 } 315 316 int32_t plat_scmi_clock_rates_array(unsigned int channel_id, 317 unsigned int scmi_id, size_t start_index, 318 unsigned long *array, size_t *nb_elts) 319 { 320 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 321 322 if (!clock) 323 return SCMI_NOT_FOUND; 324 325 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 326 return SCMI_DENIED; 327 328 /* Exposed clocks are currently fixed rate clocks */ 329 if (start_index) 330 return SCMI_INVALID_PARAMETERS; 331 332 if (!array) 333 *nb_elts = 1; 334 else if (*nb_elts == 1) 335 *array = stm32_clock_get_rate(clock->clock_id); 336 else 337 return SCMI_GENERIC_ERROR; 338 339 return SCMI_SUCCESS; 340 } 341 342 unsigned long plat_scmi_clock_get_rate(unsigned int channel_id, 343 unsigned int scmi_id) 344 { 345 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 346 347 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 348 return 0; 349 350 return stm32_clock_get_rate(clock->clock_id); 351 } 352 353 int32_t plat_scmi_clock_get_state(unsigned int channel_id, unsigned int scmi_id) 354 { 355 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 356 357 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 358 return 0; 359 360 return (int32_t)clock->enabled; 361 } 362 363 int32_t plat_scmi_clock_set_state(unsigned int channel_id, unsigned int scmi_id, 364 bool enable_not_disable) 365 { 366 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 367 368 if (!clock) 369 return SCMI_NOT_FOUND; 370 371 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 372 return SCMI_DENIED; 373 374 if (enable_not_disable) { 375 if (!clock->enabled) { 376 DMSG("SCMI clock %u enable", scmi_id); 377 stm32_clock_enable(clock->clock_id); 378 clock->enabled = true; 379 } 380 } else { 381 if (clock->enabled) { 382 DMSG("SCMI clock %u disable", scmi_id); 383 stm32_clock_disable(clock->clock_id); 384 clock->enabled = false; 385 } 386 } 387 388 return SCMI_SUCCESS; 389 } 390 391 /* 392 * Platform SCMI reset domains 393 */ 394 static struct stm32_scmi_rd *find_rd(unsigned int channel_id, 395 unsigned int scmi_id) 396 { 397 const struct channel_resources *resource = find_resource(channel_id); 398 size_t n = 0; 399 400 if (resource) { 401 for (n = 0; n < resource->rd_count; n++) 402 if (n == scmi_id) 403 return &resource->rd[n]; 404 } 405 406 return NULL; 407 } 408 409 const char *plat_scmi_rd_get_name(unsigned int channel_id, unsigned int scmi_id) 410 { 411 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 412 413 if (!rd) 414 return NULL; 415 416 return rd->name; 417 } 418 419 size_t plat_scmi_rd_count(unsigned int channel_id) 420 { 421 const struct channel_resources *resource = find_resource(channel_id); 422 423 if (!resource) 424 return 0; 425 426 return resource->rd_count; 427 } 428 429 int32_t plat_scmi_rd_autonomous(unsigned int channel_id, unsigned int scmi_id, 430 uint32_t state) 431 { 432 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 433 434 if (!rd) 435 return SCMI_NOT_FOUND; 436 437 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 438 return SCMI_DENIED; 439 440 if (rd->reset_id == MCU_HOLD_BOOT_R) 441 return SCMI_NOT_SUPPORTED; 442 443 /* Supports only reset with context loss */ 444 if (state) 445 return SCMI_NOT_SUPPORTED; 446 447 DMSG("SCMI reset %u cycle", scmi_id); 448 449 if (stm32_reset_assert(rd->reset_id, TIMEOUT_US_1MS)) 450 return SCMI_HARDWARE_ERROR; 451 452 if (stm32_reset_deassert(rd->reset_id, TIMEOUT_US_1MS)) 453 return SCMI_HARDWARE_ERROR; 454 455 return SCMI_SUCCESS; 456 } 457 458 int32_t plat_scmi_rd_set_state(unsigned int channel_id, unsigned int scmi_id, 459 bool assert_not_deassert) 460 { 461 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 462 463 if (!rd) 464 return SCMI_NOT_FOUND; 465 466 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 467 return SCMI_DENIED; 468 469 if (rd->reset_id == MCU_HOLD_BOOT_R) { 470 DMSG("SCMI MCU hold boot %s", 471 assert_not_deassert ? "set" : "release"); 472 stm32_reset_assert_deassert_mcu(assert_not_deassert); 473 return SCMI_SUCCESS; 474 } 475 476 if (assert_not_deassert) { 477 DMSG("SCMI reset %u set", scmi_id); 478 stm32_reset_set(rd->reset_id); 479 } else { 480 DMSG("SCMI reset %u release", scmi_id); 481 stm32_reset_release(rd->reset_id); 482 } 483 484 return SCMI_SUCCESS; 485 } 486 487 /* 488 * Platform SCMI voltage domains 489 */ 490 static struct stm32_scmi_voltd *find_voltd(unsigned int channel_id, 491 unsigned int scmi_id) 492 { 493 const struct channel_resources *resource = find_resource(channel_id); 494 size_t n = 0; 495 496 if (resource) { 497 for (n = 0; n < resource->voltd_count; n++) 498 if (n == scmi_id) 499 return &resource->voltd[n]; 500 } 501 502 return NULL; 503 } 504 505 size_t plat_scmi_voltd_count(unsigned int channel_id) 506 { 507 const struct channel_resources *resource = find_resource(channel_id); 508 509 if (!resource) 510 return 0; 511 512 return resource->voltd_count; 513 } 514 515 const char *plat_scmi_voltd_get_name(unsigned int channel_id, 516 unsigned int scmi_id) 517 { 518 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 519 520 /* Currently non-secure is allowed to access all PWR regulators */ 521 if (!voltd) 522 return NULL; 523 524 return voltd->name; 525 } 526 527 static enum pwr_regulator pwr_scmi_to_regu_id(struct stm32_scmi_voltd *voltd) 528 { 529 if (!strcmp(voltd->priv_id, PWR_REG11_NAME_ID)) 530 return PWR_REG11; 531 if (!strcmp(voltd->priv_id, PWR_REG18_NAME_ID)) 532 return PWR_REG18; 533 if (!strcmp(voltd->priv_id, PWR_USB33_NAME_ID)) 534 return PWR_USB33; 535 536 panic(); 537 } 538 539 static long pwr_get_level(struct stm32_scmi_voltd *voltd) 540 { 541 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 542 543 return (long)stm32mp1_pwr_regulator_mv(regu_id) * 1000; 544 } 545 546 static int32_t pwr_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 547 { 548 if (level_uv != pwr_get_level(voltd)) 549 return SCMI_INVALID_PARAMETERS; 550 551 return SCMI_SUCCESS; 552 } 553 554 static int32_t pwr_describe_levels(struct stm32_scmi_voltd *voltd, 555 size_t start_index, long *microvolt, 556 size_t *nb_elts) 557 { 558 if (start_index) 559 return SCMI_INVALID_PARAMETERS; 560 561 if (!microvolt) { 562 *nb_elts = 1; 563 return SCMI_SUCCESS; 564 } 565 566 if (*nb_elts < 1) 567 return SCMI_GENERIC_ERROR; 568 569 *nb_elts = 1; 570 *microvolt = pwr_get_level(voltd); 571 572 return SCMI_SUCCESS; 573 } 574 575 static uint32_t pwr_get_state(struct stm32_scmi_voltd *voltd) 576 { 577 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 578 579 if (stm32mp1_pwr_regulator_is_enabled(regu_id)) 580 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 581 582 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 583 } 584 585 static void pwr_set_state(struct stm32_scmi_voltd *voltd, bool enable) 586 { 587 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 588 589 DMSG("%sable PWR %s (was %s)", enable ? "En" : "Dis", voltd->name, 590 stm32mp1_pwr_regulator_is_enabled(regu_id) ? "on" : "off"); 591 592 stm32mp1_pwr_regulator_set_state(regu_id, enable); 593 } 594 595 static int32_t pmic_describe_levels(struct stm32_scmi_voltd *voltd, 596 size_t start_index, long *microvolt, 597 size_t *nb_elts) 598 { 599 const uint16_t *levels = NULL; 600 size_t full_count = 0; 601 size_t out_count = 0; 602 size_t i = 0; 603 604 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 605 return SCMI_DENIED; 606 607 stpmic1_regulator_levels_mv(voltd->priv_id, &levels, &full_count); 608 609 if (!microvolt) { 610 *nb_elts = full_count - start_index; 611 return SCMI_SUCCESS; 612 } 613 614 if (SUB_OVERFLOW(full_count, start_index, &out_count)) 615 return SCMI_GENERIC_ERROR; 616 617 out_count = MIN(out_count, *nb_elts); 618 619 FMSG("%zu levels: start %zu requested %zu output %zu", 620 full_count, start_index, *nb_elts, out_count); 621 622 for (i = 0; i < out_count; i++) 623 microvolt[i] = levels[start_index + i] * 1000; 624 625 *nb_elts = out_count; 626 627 return SCMI_SUCCESS; 628 } 629 630 static long pmic_get_level(struct stm32_scmi_voltd *voltd) 631 { 632 unsigned long level_mv = 0; 633 634 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 635 return 0; 636 637 stm32mp_get_pmic(); 638 level_mv = stpmic1_regulator_voltage_get(voltd->priv_id); 639 stm32mp_put_pmic(); 640 641 return (long)level_mv * 1000; 642 } 643 644 static int32_t pmic_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 645 { 646 int rc = 0; 647 unsigned int level_mv = 0; 648 649 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 650 return SCMI_DENIED; 651 652 if (level_uv < 0 || level_uv > (UINT16_MAX * 1000)) 653 return SCMI_INVALID_PARAMETERS; 654 655 level_mv = (unsigned int)level_uv / 1000; 656 657 DMSG("Set STPMIC1 regulator %s level to %dmV", voltd->name, level_mv); 658 659 stm32mp_get_pmic(); 660 rc = stpmic1_regulator_voltage_set(voltd->priv_id, level_mv); 661 stm32mp_put_pmic(); 662 663 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 664 } 665 666 static uint32_t pmic_get_state(struct stm32_scmi_voltd *voltd) 667 { 668 bool enabled = false; 669 670 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 671 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 672 673 stm32mp_get_pmic(); 674 enabled = stpmic1_is_regulator_enabled(voltd->priv_id); 675 stm32mp_put_pmic(); 676 677 if (enabled) 678 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 679 680 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 681 } 682 683 static int32_t pmic_set_state(struct stm32_scmi_voltd *voltd, bool enable) 684 { 685 int rc = 0; 686 687 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 688 return SCMI_DENIED; 689 690 stm32mp_get_pmic(); 691 692 DMSG("%sable STPMIC1 %s (was %s)", enable ? "En" : "Dis", voltd->name, 693 stpmic1_is_regulator_enabled(voltd->priv_id) ? "on" : "off"); 694 695 if (enable) 696 rc = stpmic1_regulator_enable(voltd->priv_id); 697 else 698 rc = stpmic1_regulator_disable(voltd->priv_id); 699 700 stm32mp_put_pmic(); 701 702 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 703 } 704 705 int32_t plat_scmi_voltd_levels_array(unsigned int channel_id, 706 unsigned int scmi_id, size_t start_index, 707 long *levels, size_t *nb_elts) 708 709 { 710 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 711 712 if (!voltd) 713 return SCMI_NOT_FOUND; 714 715 switch (voltd->priv_dev) { 716 case VOLTD_PWR: 717 return pwr_describe_levels(voltd, start_index, levels, nb_elts); 718 case VOLTD_PMIC: 719 return pmic_describe_levels(voltd, start_index, levels, 720 nb_elts); 721 default: 722 return SCMI_GENERIC_ERROR; 723 } 724 } 725 726 long plat_scmi_voltd_get_level(unsigned int channel_id, unsigned int scmi_id) 727 { 728 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 729 730 if (!voltd) 731 return 0; 732 733 switch (voltd->priv_dev) { 734 case VOLTD_PWR: 735 return pwr_get_level(voltd); 736 case VOLTD_PMIC: 737 return pmic_get_level(voltd); 738 default: 739 panic(); 740 } 741 } 742 743 int32_t plat_scmi_voltd_set_level(unsigned int channel_id, unsigned int scmi_id, 744 long level) 745 { 746 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 747 748 if (!voltd) 749 return SCMI_NOT_FOUND; 750 751 switch (voltd->priv_dev) { 752 case VOLTD_PWR: 753 return pwr_set_level(voltd, level); 754 case VOLTD_PMIC: 755 return pmic_set_level(voltd, level); 756 default: 757 return SCMI_GENERIC_ERROR; 758 } 759 } 760 761 int32_t plat_scmi_voltd_get_config(unsigned int channel_id, 762 unsigned int scmi_id, uint32_t *config) 763 { 764 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 765 766 if (!voltd) 767 return SCMI_NOT_FOUND; 768 769 switch (voltd->priv_dev) { 770 case VOLTD_PWR: 771 *config = pwr_get_state(voltd); 772 break; 773 case VOLTD_PMIC: 774 *config = pmic_get_state(voltd); 775 break; 776 default: 777 return SCMI_GENERIC_ERROR; 778 } 779 780 return SCMI_SUCCESS; 781 } 782 783 int32_t plat_scmi_voltd_set_config(unsigned int channel_id, 784 unsigned int scmi_id, uint32_t config) 785 { 786 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 787 int32_t rc = SCMI_SUCCESS; 788 789 if (!voltd) 790 return SCMI_NOT_FOUND; 791 792 switch (voltd->priv_dev) { 793 case VOLTD_PWR: 794 pwr_set_state(voltd, config); 795 break; 796 case VOLTD_PMIC: 797 rc = pmic_set_state(voltd, config); 798 break; 799 default: 800 return SCMI_GENERIC_ERROR; 801 } 802 803 return rc; 804 } 805 806 /* 807 * Initialize platform SCMI resources 808 */ 809 static TEE_Result stm32mp1_init_scmi_server(void) 810 { 811 size_t i = 0; 812 size_t j = 0; 813 814 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 815 const struct channel_resources *res = scmi_channel + i; 816 struct scmi_msg_channel *chan = res->channel; 817 818 /* Enforce non-secure shm mapped as device memory */ 819 chan->shm_addr.va = (vaddr_t)phys_to_virt(chan->shm_addr.pa, 820 MEM_AREA_IO_NSEC); 821 assert(chan->shm_addr.va); 822 823 scmi_smt_init_agent_channel(chan); 824 825 for (j = 0; j < res->clock_count; j++) { 826 struct stm32_scmi_clk *clk = &res->clock[j]; 827 828 if (!clk->name || 829 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 830 panic("SCMI clock name invalid"); 831 832 /* Sync SCMI clocks with their targeted initial state */ 833 if (clk->enabled && 834 stm32mp_nsec_can_access_clock(clk->clock_id)) 835 stm32_clock_enable(clk->clock_id); 836 } 837 838 for (j = 0; j < res->rd_count; j++) { 839 struct stm32_scmi_rd *rd = &res->rd[j]; 840 841 if (!rd->name || 842 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 843 panic("SCMI reset domain name invalid"); 844 } 845 846 for (j = 0; j < res->voltd_count; j++) { 847 struct stm32_scmi_voltd *voltd = &res->voltd[j]; 848 849 if (!voltd->name || 850 strlen(voltd->name) >= SCMI_VOLTD_NAME_SIZE) 851 panic("SCMI voltage domain name invalid"); 852 } 853 } 854 855 return TEE_SUCCESS; 856 } 857 858 driver_init_late(stm32mp1_init_scmi_server); 859