1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <drivers/scmi-msg.h> 8 #include <drivers/scmi.h> 9 #include <drivers/stm32mp1_pmic.h> 10 #include <drivers/stm32mp1_pwr.h> 11 #include <drivers/stpmic1.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/regulator/st,stm32mp15-regulator.h> 14 #include <dt-bindings/reset/stm32mp1-resets.h> 15 #include <initcall.h> 16 #include <mm/core_memprot.h> 17 #include <mm/core_mmu.h> 18 #include <platform_config.h> 19 #include <stdint.h> 20 #include <speculation_barrier.h> 21 #include <stm32_util.h> 22 #include <string.h> 23 #include <tee_api_defines.h> 24 #include <util.h> 25 26 #define TIMEOUT_US_1MS 1000 27 28 #define SCMI_CLOCK_NAME_SIZE 16 29 #define SCMI_RD_NAME_SIZE 16 30 #define SCMI_VOLTD_NAME_SIZE 16 31 32 /* 33 * struct stm32_scmi_clk - Data for the exposed clock 34 * @clock_id: Clock identifier in RCC clock driver 35 * @name: Clock string ID exposed to channel 36 * @enabled: State of the SCMI clock 37 */ 38 struct stm32_scmi_clk { 39 unsigned long clock_id; 40 const char *name; 41 bool enabled; 42 }; 43 44 /* 45 * struct stm32_scmi_rd - Data for the exposed reset controller 46 * @reset_id: Reset identifier in RCC reset driver 47 * @name: Reset string ID exposed to channel 48 */ 49 struct stm32_scmi_rd { 50 unsigned long reset_id; 51 const char *name; 52 }; 53 54 enum voltd_device { 55 VOLTD_PWR, 56 VOLTD_PMIC, 57 }; 58 59 /* 60 * struct stm32_scmi_voltd - Data for the exposed voltage domains 61 * @name: Power regulator string ID exposed to channel 62 * @priv_id: Internal string ID for the regulator 63 * @priv_dev: Internal ID for the device implementing the regulator 64 */ 65 struct stm32_scmi_voltd { 66 const char *name; 67 const char *priv_id; 68 enum voltd_device priv_dev; 69 70 }; 71 72 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 73 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 74 #define SMT_BUFFER0_BASE SMT_BUFFER_BASE 75 #define SMT_BUFFER1_BASE (SMT_BUFFER_BASE + 0x200) 76 77 #if (SMT_BUFFER1_BASE + SMT_BUF_SLOT_SIZE > \ 78 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 79 #error "SCMI shared memory mismatch" 80 #endif 81 82 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 83 CFG_STM32MP1_SCMI_SHM_SIZE); 84 85 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 86 [_scmi_id] = { \ 87 .clock_id = _id, \ 88 .name = _name, \ 89 .enabled = _init_enabled, \ 90 } 91 92 static struct stm32_scmi_clk stm32_scmi0_clock[] = { 93 CLOCK_CELL(CK_SCMI0_HSE, CK_HSE, "ck_hse", true), 94 CLOCK_CELL(CK_SCMI0_HSI, CK_HSI, "ck_hsi", true), 95 CLOCK_CELL(CK_SCMI0_CSI, CK_CSI, "ck_csi", true), 96 CLOCK_CELL(CK_SCMI0_LSE, CK_LSE, "ck_lse", true), 97 CLOCK_CELL(CK_SCMI0_LSI, CK_LSI, "ck_lsi", true), 98 CLOCK_CELL(CK_SCMI0_PLL2_Q, PLL2_Q, "pll2_q", true), 99 CLOCK_CELL(CK_SCMI0_PLL2_R, PLL2_R, "pll2_r", true), 100 CLOCK_CELL(CK_SCMI0_MPU, CK_MPU, "ck_mpu", true), 101 CLOCK_CELL(CK_SCMI0_AXI, CK_AXI, "ck_axi", true), 102 CLOCK_CELL(CK_SCMI0_BSEC, BSEC, "bsec", true), 103 CLOCK_CELL(CK_SCMI0_CRYP1, CRYP1, "cryp1", false), 104 CLOCK_CELL(CK_SCMI0_GPIOZ, GPIOZ, "gpioz", false), 105 CLOCK_CELL(CK_SCMI0_HASH1, HASH1, "hash1", false), 106 CLOCK_CELL(CK_SCMI0_I2C4, I2C4_K, "i2c4_k", false), 107 CLOCK_CELL(CK_SCMI0_I2C6, I2C6_K, "i2c6_k", false), 108 CLOCK_CELL(CK_SCMI0_IWDG1, IWDG1, "iwdg1", false), 109 CLOCK_CELL(CK_SCMI0_RNG1, RNG1_K, "rng1_k", true), 110 CLOCK_CELL(CK_SCMI0_RTC, RTC, "ck_rtc", true), 111 CLOCK_CELL(CK_SCMI0_RTCAPB, RTCAPB, "rtcapb", true), 112 CLOCK_CELL(CK_SCMI0_SPI6, SPI6_K, "spi6_k", false), 113 CLOCK_CELL(CK_SCMI0_USART1, USART1_K, "usart1_k", false), 114 }; 115 116 static struct stm32_scmi_clk stm32_scmi1_clock[] = { 117 CLOCK_CELL(CK_SCMI1_PLL3_Q, PLL3_Q, "pll3_q", true), 118 CLOCK_CELL(CK_SCMI1_PLL3_R, PLL3_R, "pll3_r", true), 119 CLOCK_CELL(CK_SCMI1_MCU, CK_MCU, "ck_mcu", false), 120 }; 121 122 #define RESET_CELL(_scmi_id, _id, _name) \ 123 [_scmi_id] = { \ 124 .reset_id = _id, \ 125 .name = _name, \ 126 } 127 128 static struct stm32_scmi_rd stm32_scmi0_reset_domain[] = { 129 RESET_CELL(RST_SCMI0_SPI6, SPI6_R, "spi6"), 130 RESET_CELL(RST_SCMI0_I2C4, I2C4_R, "i2c4"), 131 RESET_CELL(RST_SCMI0_I2C6, I2C6_R, "i2c6"), 132 RESET_CELL(RST_SCMI0_USART1, USART1_R, "usart1"), 133 RESET_CELL(RST_SCMI0_STGEN, STGEN_R, "stgen"), 134 RESET_CELL(RST_SCMI0_GPIOZ, GPIOZ_R, "gpioz"), 135 RESET_CELL(RST_SCMI0_CRYP1, CRYP1_R, "cryp1"), 136 RESET_CELL(RST_SCMI0_HASH1, HASH1_R, "hash1"), 137 RESET_CELL(RST_SCMI0_RNG1, RNG1_R, "rng1"), 138 RESET_CELL(RST_SCMI0_MDMA, MDMA_R, "mdma"), 139 RESET_CELL(RST_SCMI0_MCU, MCU_R, "mcu"), 140 RESET_CELL(RST_SCMI0_MCU_HOLD_BOOT, MCU_HOLD_BOOT_R, "mcu_hold_boot"), 141 }; 142 143 #define VOLTD_CELL(_scmi_id, _dev_id, _priv_id, _name) \ 144 [_scmi_id] = { \ 145 .priv_id = (_priv_id), \ 146 .priv_dev = (_dev_id), \ 147 .name = (_name), \ 148 } 149 150 #define PWR_REG11_NAME_ID "0" 151 #define PWR_REG18_NAME_ID "1" 152 #define PWR_USB33_NAME_ID "2" 153 154 struct stm32_scmi_voltd scmi0_voltage_domain[] = { 155 VOLTD_CELL(VOLTD_SCMI0_REG11, VOLTD_PWR, PWR_REG11_NAME_ID, "reg11"), 156 VOLTD_CELL(VOLTD_SCMI0_REG18, VOLTD_PWR, PWR_REG18_NAME_ID, "reg18"), 157 VOLTD_CELL(VOLTD_SCMI0_USB33, VOLTD_PWR, PWR_USB33_NAME_ID, "usb33"), 158 }; 159 160 struct channel_resources { 161 struct scmi_msg_channel *channel; 162 struct stm32_scmi_clk *clock; 163 size_t clock_count; 164 struct stm32_scmi_rd *rd; 165 size_t rd_count; 166 struct stm32_scmi_voltd *voltd; 167 size_t voltd_count; 168 }; 169 170 static const struct channel_resources scmi_channel[] = { 171 [0] = { 172 .channel = &(struct scmi_msg_channel){ 173 .shm_addr = { .pa = SMT_BUFFER0_BASE }, 174 .shm_size = SMT_BUF_SLOT_SIZE, 175 }, 176 .clock = stm32_scmi0_clock, 177 .clock_count = ARRAY_SIZE(stm32_scmi0_clock), 178 .rd = stm32_scmi0_reset_domain, 179 .rd_count = ARRAY_SIZE(stm32_scmi0_reset_domain), 180 .voltd = scmi0_voltage_domain, 181 .voltd_count = ARRAY_SIZE(scmi0_voltage_domain), 182 }, 183 [1] = { 184 .channel = &(struct scmi_msg_channel){ 185 .shm_addr = { .pa = SMT_BUFFER1_BASE }, 186 .shm_size = SMT_BUF_SLOT_SIZE, 187 }, 188 .clock = stm32_scmi1_clock, 189 .clock_count = ARRAY_SIZE(stm32_scmi1_clock), 190 }, 191 }; 192 193 static const struct channel_resources *find_resource(unsigned int channel_id) 194 { 195 assert(channel_id < ARRAY_SIZE(scmi_channel)); 196 197 return scmi_channel + channel_id; 198 } 199 200 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int channel_id) 201 { 202 return find_resource(channel_id)->channel; 203 } 204 205 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 206 { 207 unsigned int n = 0; 208 unsigned int count = 0; 209 const size_t channel_count = ARRAY_SIZE(scmi_channel); 210 211 for (n = 0; n < channel_count; n++) 212 if (scmi_channel[n].clock_count) 213 break; 214 if (n < channel_count) 215 count++; 216 217 for (n = 0; n < channel_count; n++) 218 if (scmi_channel[n].rd_count) 219 break; 220 if (n < channel_count) 221 count++; 222 223 for (n = 0; n < channel_count; n++) 224 if (scmi_channel[n].voltd_count) 225 break; 226 if (n < channel_count) 227 count++; 228 229 return count; 230 } 231 232 static const char vendor[] = "ST"; 233 static const char sub_vendor[] = ""; 234 235 const char *plat_scmi_vendor_name(void) 236 { 237 return vendor; 238 } 239 240 const char *plat_scmi_sub_vendor_name(void) 241 { 242 return sub_vendor; 243 } 244 245 /* Currently supporting Clocks and Reset Domains */ 246 static const uint8_t plat_protocol_list[] = { 247 SCMI_PROTOCOL_ID_CLOCK, 248 SCMI_PROTOCOL_ID_RESET_DOMAIN, 249 SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, 250 0 /* Null termination */ 251 }; 252 253 size_t plat_scmi_protocol_count(void) 254 { 255 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 256 257 assert(count == plat_scmi_protocol_count_paranoid()); 258 259 return count; 260 } 261 262 const uint8_t *plat_scmi_protocol_list(unsigned int channel_id __unused) 263 { 264 assert(plat_scmi_protocol_count_paranoid() == 265 (ARRAY_SIZE(plat_protocol_list) - 1)); 266 267 return plat_protocol_list; 268 } 269 270 /* 271 * Platform SCMI clocks 272 */ 273 static struct stm32_scmi_clk *find_clock(unsigned int channel_id, 274 unsigned int scmi_id) 275 { 276 const struct channel_resources *resource = find_resource(channel_id); 277 size_t n = 0; 278 279 if (resource) { 280 for (n = 0; n < resource->clock_count; n++) 281 if (n == scmi_id) 282 return &resource->clock[n]; 283 } 284 285 return NULL; 286 } 287 288 size_t plat_scmi_clock_count(unsigned int channel_id) 289 { 290 const struct channel_resources *resource = find_resource(channel_id); 291 292 if (!resource) 293 return 0; 294 295 return resource->clock_count; 296 } 297 298 const char *plat_scmi_clock_get_name(unsigned int channel_id, 299 unsigned int scmi_id) 300 { 301 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 302 303 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 304 return NULL; 305 306 return clock->name; 307 } 308 309 int32_t plat_scmi_clock_rates_array(unsigned int channel_id, 310 unsigned int scmi_id, size_t start_index, 311 unsigned long *array, size_t *nb_elts) 312 { 313 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 314 315 if (!clock) 316 return SCMI_NOT_FOUND; 317 318 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 319 return SCMI_DENIED; 320 321 /* Exposed clocks are currently fixed rate clocks */ 322 if (start_index) 323 return SCMI_INVALID_PARAMETERS; 324 325 if (!array) 326 *nb_elts = 1; 327 else if (*nb_elts == 1) 328 *array = stm32_clock_get_rate(clock->clock_id); 329 else 330 return SCMI_GENERIC_ERROR; 331 332 return SCMI_SUCCESS; 333 } 334 335 unsigned long plat_scmi_clock_get_rate(unsigned int channel_id, 336 unsigned int scmi_id) 337 { 338 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 339 340 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 341 return 0; 342 343 return stm32_clock_get_rate(clock->clock_id); 344 } 345 346 int32_t plat_scmi_clock_get_state(unsigned int channel_id, unsigned int scmi_id) 347 { 348 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 349 350 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 351 return 0; 352 353 return (int32_t)clock->enabled; 354 } 355 356 int32_t plat_scmi_clock_set_state(unsigned int channel_id, unsigned int scmi_id, 357 bool enable_not_disable) 358 { 359 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 360 361 if (!clock) 362 return SCMI_NOT_FOUND; 363 364 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 365 return SCMI_DENIED; 366 367 if (enable_not_disable) { 368 if (!clock->enabled) { 369 DMSG("SCMI clock %u enable", scmi_id); 370 stm32_clock_enable(clock->clock_id); 371 clock->enabled = true; 372 } 373 } else { 374 if (clock->enabled) { 375 DMSG("SCMI clock %u disable", scmi_id); 376 stm32_clock_disable(clock->clock_id); 377 clock->enabled = false; 378 } 379 } 380 381 return SCMI_SUCCESS; 382 } 383 384 /* 385 * Platform SCMI reset domains 386 */ 387 static struct stm32_scmi_rd *find_rd(unsigned int channel_id, 388 unsigned int scmi_id) 389 { 390 const struct channel_resources *resource = find_resource(channel_id); 391 size_t n = 0; 392 393 if (resource) { 394 for (n = 0; n < resource->rd_count; n++) 395 if (n == scmi_id) 396 return &resource->rd[n]; 397 } 398 399 return NULL; 400 } 401 402 const char *plat_scmi_rd_get_name(unsigned int channel_id, unsigned int scmi_id) 403 { 404 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 405 406 if (!rd) 407 return NULL; 408 409 return rd->name; 410 } 411 412 size_t plat_scmi_rd_count(unsigned int channel_id) 413 { 414 const struct channel_resources *resource = find_resource(channel_id); 415 416 if (!resource) 417 return 0; 418 419 return resource->rd_count; 420 } 421 422 int32_t plat_scmi_rd_autonomous(unsigned int channel_id, unsigned int scmi_id, 423 uint32_t state) 424 { 425 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 426 427 if (!rd) 428 return SCMI_NOT_FOUND; 429 430 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 431 return SCMI_DENIED; 432 433 if (rd->reset_id == MCU_HOLD_BOOT_R) 434 return SCMI_NOT_SUPPORTED; 435 436 /* Supports only reset with context loss */ 437 if (state) 438 return SCMI_NOT_SUPPORTED; 439 440 DMSG("SCMI reset %u cycle", scmi_id); 441 442 if (stm32_reset_assert(rd->reset_id, TIMEOUT_US_1MS)) 443 return SCMI_HARDWARE_ERROR; 444 445 if (stm32_reset_deassert(rd->reset_id, TIMEOUT_US_1MS)) 446 return SCMI_HARDWARE_ERROR; 447 448 return SCMI_SUCCESS; 449 } 450 451 int32_t plat_scmi_rd_set_state(unsigned int channel_id, unsigned int scmi_id, 452 bool assert_not_deassert) 453 { 454 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 455 456 if (!rd) 457 return SCMI_NOT_FOUND; 458 459 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 460 return SCMI_DENIED; 461 462 if (rd->reset_id == MCU_HOLD_BOOT_R) { 463 DMSG("SCMI MCU hold boot %s", 464 assert_not_deassert ? "set" : "release"); 465 stm32_reset_assert_deassert_mcu(assert_not_deassert); 466 return SCMI_SUCCESS; 467 } 468 469 if (assert_not_deassert) { 470 DMSG("SCMI reset %u set", scmi_id); 471 stm32_reset_set(rd->reset_id); 472 } else { 473 DMSG("SCMI reset %u release", scmi_id); 474 stm32_reset_release(rd->reset_id); 475 } 476 477 return SCMI_SUCCESS; 478 } 479 480 /* 481 * Platform SCMI voltage domains 482 */ 483 static struct stm32_scmi_voltd *find_voltd(unsigned int channel_id, 484 unsigned int scmi_id) 485 { 486 const struct channel_resources *resource = find_resource(channel_id); 487 size_t n = 0; 488 489 if (resource) { 490 for (n = 0; n < resource->voltd_count; n++) 491 if (n == scmi_id) 492 return &resource->voltd[n]; 493 } 494 495 return NULL; 496 } 497 498 size_t plat_scmi_voltd_count(unsigned int channel_id) 499 { 500 const struct channel_resources *resource = find_resource(channel_id); 501 502 if (!resource) 503 return 0; 504 505 return resource->voltd_count; 506 } 507 508 const char *plat_scmi_voltd_get_name(unsigned int channel_id, 509 unsigned int scmi_id) 510 { 511 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 512 513 /* Currently non-secure is allowed to access all PWR regulators */ 514 if (!voltd) 515 return NULL; 516 517 return voltd->name; 518 } 519 520 static enum pwr_regulator pwr_scmi_to_regu_id(struct stm32_scmi_voltd *voltd) 521 { 522 if (!strcmp(voltd->priv_id, PWR_REG11_NAME_ID)) 523 return PWR_REG11; 524 if (!strcmp(voltd->priv_id, PWR_REG18_NAME_ID)) 525 return PWR_REG18; 526 if (!strcmp(voltd->priv_id, PWR_USB33_NAME_ID)) 527 return PWR_USB33; 528 529 panic(); 530 } 531 532 static long pwr_get_level(struct stm32_scmi_voltd *voltd) 533 { 534 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 535 536 return (long)stm32mp1_pwr_regulator_mv(regu_id) * 1000; 537 } 538 539 static int32_t pwr_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 540 { 541 if (level_uv != pwr_get_level(voltd)) 542 return SCMI_INVALID_PARAMETERS; 543 544 return SCMI_SUCCESS; 545 } 546 547 static int32_t pwr_describe_levels(struct stm32_scmi_voltd *voltd, 548 size_t start_index, long *microvolt, 549 size_t *nb_elts) 550 { 551 if (start_index) 552 return SCMI_INVALID_PARAMETERS; 553 554 if (!microvolt) { 555 *nb_elts = 1; 556 return SCMI_SUCCESS; 557 } 558 559 if (*nb_elts < 1) 560 return SCMI_GENERIC_ERROR; 561 562 *nb_elts = 1; 563 *microvolt = pwr_get_level(voltd); 564 565 return SCMI_SUCCESS; 566 } 567 568 static uint32_t pwr_get_state(struct stm32_scmi_voltd *voltd) 569 { 570 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 571 572 if (stm32mp1_pwr_regulator_is_enabled(regu_id)) 573 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 574 575 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 576 } 577 578 static void pwr_set_state(struct stm32_scmi_voltd *voltd, bool enable) 579 { 580 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 581 582 DMSG("%sable PWR %s (was %s)", enable ? "En" : "Dis", voltd->name, 583 stm32mp1_pwr_regulator_is_enabled(regu_id) ? "on" : "off"); 584 585 stm32mp1_pwr_regulator_set_state(regu_id, enable); 586 } 587 588 static int32_t pmic_describe_levels(struct stm32_scmi_voltd *voltd, 589 size_t start_index, long *microvolt, 590 size_t *nb_elts) 591 { 592 const uint16_t *levels = NULL; 593 size_t full_count = 0; 594 size_t out_count = 0; 595 size_t i = 0; 596 597 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 598 return SCMI_DENIED; 599 600 stpmic1_regulator_levels_mv(voltd->priv_id, &levels, &full_count); 601 602 if (!microvolt) { 603 *nb_elts = full_count - start_index; 604 return SCMI_SUCCESS; 605 } 606 607 if (SUB_OVERFLOW(full_count, start_index, &out_count)) 608 return SCMI_GENERIC_ERROR; 609 610 out_count = MIN(out_count, *nb_elts); 611 612 FMSG("%zu levels: start %zu requested %zu output %zu", 613 full_count, start_index, *nb_elts, out_count); 614 615 for (i = 0; i < out_count; i++) 616 microvolt[i] = levels[start_index + i] * 1000; 617 618 *nb_elts = out_count; 619 620 return SCMI_SUCCESS; 621 } 622 623 static long pmic_get_level(struct stm32_scmi_voltd *voltd) 624 { 625 unsigned long level_mv = 0; 626 627 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 628 return 0; 629 630 stm32mp_get_pmic(); 631 level_mv = stpmic1_regulator_voltage_get(voltd->priv_id); 632 stm32mp_put_pmic(); 633 634 return (long)level_mv * 1000; 635 } 636 637 static int32_t pmic_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 638 { 639 int rc = 0; 640 unsigned int level_mv = 0; 641 642 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 643 return SCMI_DENIED; 644 645 if (level_uv < 0 || level_uv > (UINT16_MAX * 1000)) 646 return SCMI_INVALID_PARAMETERS; 647 648 level_mv = (unsigned int)level_uv / 1000; 649 650 DMSG("Set STPMIC1 regulator %s level to %dmV", voltd->name, level_mv); 651 652 stm32mp_get_pmic(); 653 rc = stpmic1_regulator_voltage_set(voltd->priv_id, level_mv); 654 stm32mp_put_pmic(); 655 656 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 657 } 658 659 static uint32_t pmic_get_state(struct stm32_scmi_voltd *voltd) 660 { 661 bool enabled = false; 662 663 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 664 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 665 666 stm32mp_get_pmic(); 667 enabled = stpmic1_is_regulator_enabled(voltd->priv_id); 668 stm32mp_put_pmic(); 669 670 if (enabled) 671 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 672 673 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 674 } 675 676 static int32_t pmic_set_state(struct stm32_scmi_voltd *voltd, bool enable) 677 { 678 int rc = 0; 679 680 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 681 return SCMI_DENIED; 682 683 stm32mp_get_pmic(); 684 685 DMSG("%sable STPMIC1 %s (was %s)", enable ? "En" : "Dis", voltd->name, 686 stpmic1_is_regulator_enabled(voltd->priv_id) ? "on" : "off"); 687 688 if (enable) 689 rc = stpmic1_regulator_enable(voltd->priv_id); 690 else 691 rc = stpmic1_regulator_disable(voltd->priv_id); 692 693 stm32mp_put_pmic(); 694 695 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 696 } 697 698 int32_t plat_scmi_voltd_levels_array(unsigned int channel_id, 699 unsigned int scmi_id, size_t start_index, 700 long *levels, size_t *nb_elts) 701 702 { 703 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 704 705 if (!voltd) 706 return SCMI_NOT_FOUND; 707 708 switch (voltd->priv_dev) { 709 case VOLTD_PWR: 710 return pwr_describe_levels(voltd, start_index, levels, nb_elts); 711 case VOLTD_PMIC: 712 return pmic_describe_levels(voltd, start_index, levels, 713 nb_elts); 714 default: 715 return SCMI_GENERIC_ERROR; 716 } 717 } 718 719 long plat_scmi_voltd_get_level(unsigned int channel_id, unsigned int scmi_id) 720 { 721 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 722 723 if (!voltd) 724 return 0; 725 726 switch (voltd->priv_dev) { 727 case VOLTD_PWR: 728 return pwr_get_level(voltd); 729 case VOLTD_PMIC: 730 return pmic_get_level(voltd); 731 default: 732 panic(); 733 } 734 } 735 736 int32_t plat_scmi_voltd_set_level(unsigned int channel_id, unsigned int scmi_id, 737 long level) 738 { 739 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 740 741 if (!voltd) 742 return SCMI_NOT_FOUND; 743 744 switch (voltd->priv_dev) { 745 case VOLTD_PWR: 746 return pwr_set_level(voltd, level); 747 case VOLTD_PMIC: 748 return pmic_set_level(voltd, level); 749 default: 750 return SCMI_GENERIC_ERROR; 751 } 752 } 753 754 int32_t plat_scmi_voltd_get_config(unsigned int channel_id, 755 unsigned int scmi_id, uint32_t *config) 756 { 757 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 758 759 if (!voltd) 760 return SCMI_NOT_FOUND; 761 762 switch (voltd->priv_dev) { 763 case VOLTD_PWR: 764 *config = pwr_get_state(voltd); 765 break; 766 case VOLTD_PMIC: 767 *config = pmic_get_state(voltd); 768 break; 769 default: 770 return SCMI_GENERIC_ERROR; 771 } 772 773 return SCMI_SUCCESS; 774 } 775 776 int32_t plat_scmi_voltd_set_config(unsigned int channel_id, 777 unsigned int scmi_id, uint32_t config) 778 { 779 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 780 int32_t rc = SCMI_SUCCESS; 781 782 if (!voltd) 783 return SCMI_NOT_FOUND; 784 785 switch (voltd->priv_dev) { 786 case VOLTD_PWR: 787 pwr_set_state(voltd, config); 788 break; 789 case VOLTD_PMIC: 790 rc = pmic_set_state(voltd, config); 791 break; 792 default: 793 return SCMI_GENERIC_ERROR; 794 } 795 796 return rc; 797 } 798 799 /* 800 * Initialize platform SCMI resources 801 */ 802 static TEE_Result stm32mp1_init_scmi_server(void) 803 { 804 size_t i = 0; 805 size_t j = 0; 806 807 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 808 const struct channel_resources *res = scmi_channel + i; 809 struct scmi_msg_channel *chan = res->channel; 810 811 /* Enforce non-secure shm mapped as device memory */ 812 chan->shm_addr.va = (vaddr_t)phys_to_virt(chan->shm_addr.pa, 813 MEM_AREA_IO_NSEC); 814 assert(chan->shm_addr.va); 815 816 scmi_smt_init_agent_channel(chan); 817 818 for (j = 0; j < res->clock_count; j++) { 819 struct stm32_scmi_clk *clk = &res->clock[j]; 820 821 if (!clk->name || 822 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 823 panic("SCMI clock name invalid"); 824 825 /* Sync SCMI clocks with their targeted initial state */ 826 if (clk->enabled && 827 stm32mp_nsec_can_access_clock(clk->clock_id)) 828 stm32_clock_enable(clk->clock_id); 829 } 830 831 for (j = 0; j < res->rd_count; j++) { 832 struct stm32_scmi_rd *rd = &res->rd[j]; 833 834 if (!rd->name || 835 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 836 panic("SCMI reset domain name invalid"); 837 } 838 839 for (j = 0; j < res->voltd_count; j++) { 840 struct stm32_scmi_voltd *voltd = &res->voltd[j]; 841 842 if (!voltd->name || 843 strlen(voltd->name) >= SCMI_VOLTD_NAME_SIZE) 844 panic("SCMI voltage domain name invalid"); 845 } 846 } 847 848 return TEE_SUCCESS; 849 } 850 851 driver_init_late(stm32mp1_init_scmi_server); 852