1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019-2022, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <confine_array_index.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/firewall_device.h> 11 #include <drivers/regulator.h> 12 #include <drivers/rstctrl.h> 13 #include <drivers/scmi-msg.h> 14 #include <drivers/scmi.h> 15 #include <drivers/stm32_remoteproc.h> 16 #include <drivers/stm32_vrefbuf.h> 17 #include <drivers/stm32mp1_pmic.h> 18 #include <drivers/stm32mp1_pwr.h> 19 #include <drivers/stm32mp13_regulator_iod.h> 20 #include <drivers/stpmic1.h> 21 #include <drivers/stpmic1_regulator.h> 22 #include <drivers/stm32mp_dt_bindings.h> 23 #include <initcall.h> 24 #include <mm/core_memprot.h> 25 #include <mm/core_mmu.h> 26 #include <platform_config.h> 27 #include <stdint.h> 28 #include <speculation_barrier.h> 29 #include <stm32_util.h> 30 #include <string.h> 31 #include <tee_api_defines.h> 32 #include <util.h> 33 34 #define TIMEOUT_US_1MS 1000 35 36 #define SCMI_CLOCK_NAME_SIZE 16 37 #define SCMI_RD_NAME_SIZE 16 38 #define SCMI_VOLTD_NAME_SIZE 16 39 40 #define ETZPC_ID_ALWAYS_ACCESSIBLE (STM32MP1_ETZPC_MAX_ID + 1) 41 #define ETZPC_ID_NEVER_ACCESSIBLE (STM32MP1_ETZPC_MAX_ID + 2) 42 43 /* 44 * struct stm32_scmi_clk - Data for the exposed clock 45 * @clock_id: Clock identifier in RCC clock driver 46 * @etzpc_id: ETZPC ID of the peripheral related to the clock 47 * @name: Clock string ID exposed to channel 48 * @enabled: State of the SCMI clock 49 */ 50 struct stm32_scmi_clk { 51 unsigned long clock_id; 52 struct clk *clk; 53 unsigned int etzpc_id; 54 const char *name; 55 bool enabled; 56 }; 57 58 /* 59 * struct stm32_scmi_rd - Data for the exposed reset controller 60 * @reset_id: Reset identifier in RCC reset driver 61 * @etzpc_id: ETZPC ID of the peripheral related to the reset controller 62 * @name: Reset string ID exposed to channel 63 * @rstctrl: Reset controller device 64 */ 65 struct stm32_scmi_rd { 66 unsigned long reset_id; 67 unsigned int etzpc_id; 68 const char *name; 69 struct rstctrl *rstctrl; 70 }; 71 72 enum voltd_device { 73 VOLTD_PWR, 74 VOLTD_PMIC, 75 VOLTD_VREFBUF, 76 VOLTD_IOD, 77 }; 78 79 /* 80 * struct stm32_scmi_voltd - Data for the exposed voltage domains 81 * @name: Power regulator string ID exposed to channel 82 * @priv_name: Internal string ID for the PMIC regulators 83 * @priv_id: Internal ID for the regulator aside PMIC ones 84 * @priv_dev: Internal ID for the device implementing the regulator 85 * @regulator: Regulator controller device 86 * @state: State of the SCMI voltage domain (true: enable, false: disable) 87 */ 88 struct stm32_scmi_voltd { 89 const char *name; 90 const char *priv_name; 91 unsigned int priv_id; 92 enum voltd_device priv_dev; 93 struct regulator *regulator; 94 bool state; 95 }; 96 97 #if CFG_STM32MP1_SCMI_SHM_BASE 98 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 99 CFG_STM32MP1_SCMI_SHM_SIZE); 100 101 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 102 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 103 104 #if (SMT_BUFFER_BASE + SMT_BUF_SLOT_SIZE > \ 105 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 106 #error "SCMI shared memory mismatch" 107 #endif 108 #endif /*CFG_STM32MP1_SCMI_SHM_BASE*/ 109 110 /* SCMI clock always accessible */ 111 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 112 [(_scmi_id)] = { \ 113 .clock_id = (_id), \ 114 .etzpc_id = ETZPC_ID_ALWAYS_ACCESSIBLE, \ 115 .name = (_name), \ 116 .enabled = (_init_enabled), \ 117 } 118 119 /* SCMI clock accessible upon DECPROT ID assigned to non-secure */ 120 #define CLOCK_CELL_DECPROT(_scmi_id, _id, _name, _init_enabled, _etzpc_id) \ 121 [(_scmi_id)] = { \ 122 .clock_id = (_id), \ 123 .etzpc_id = (_etzpc_id), \ 124 .name = (_name), \ 125 .enabled = (_init_enabled), \ 126 } 127 128 /* SCMI reset domain always accessible */ 129 #define RESET_CELL(_scmi_id, _id, _name) \ 130 [(_scmi_id)] = { \ 131 .reset_id = (_id), \ 132 .etzpc_id = ETZPC_ID_ALWAYS_ACCESSIBLE, \ 133 .name = (_name), \ 134 } 135 136 /* SCMI reset domain accessible upon DECPROT ID assigned to non-secure */ 137 #define RESET_CELL_DECPROT(_scmi_id, _id, _name, _etzpc_id) \ 138 [(_scmi_id)] = { \ 139 .reset_id = (_id), \ 140 .etzpc_id = (_etzpc_id), \ 141 .name = (_name), \ 142 } 143 144 #define VOLTD_CELL(_scmi_id, _dev_id, _priv_id, _priv_name, _name) \ 145 [(_scmi_id)] = { \ 146 .priv_name = (_priv_name), \ 147 .priv_id = (_priv_id), \ 148 .priv_dev = (_dev_id), \ 149 .name = (_name), \ 150 } 151 152 #define VOLTD_CELL_PWR(_scmi_id, _priv_id, _name) \ 153 VOLTD_CELL((_scmi_id), VOLTD_PWR, (_priv_id), NULL, (_name)) 154 155 #define VOLTD_CELL_IOD(_scmi_id, _priv_id, _name) \ 156 VOLTD_CELL((_scmi_id), VOLTD_IOD, (_priv_id), NULL, (_name)) 157 158 #define VOLTD_CELL_VREFBUF(_scmi_id, _name) \ 159 VOLTD_CELL((_scmi_id), VOLTD_VREFBUF, 0, NULL, (_name)) 160 161 #define VOLTD_CELL_PMIC(_scmi_id, _priv_name, _name) \ 162 VOLTD_CELL((_scmi_id), VOLTD_PMIC, 0, (_priv_name), (_name)) 163 164 #ifdef CFG_STM32MP13 165 static struct stm32_scmi_clk stm32_scmi_clock[] = { 166 CLOCK_CELL(CK_SCMI_HSE, CK_HSE, "ck_hse", true), 167 CLOCK_CELL(CK_SCMI_HSI, CK_HSI, "ck_hsi", true), 168 CLOCK_CELL(CK_SCMI_CSI, CK_CSI, "ck_csi", true), 169 CLOCK_CELL(CK_SCMI_LSE, CK_LSE, "ck_lse", true), 170 CLOCK_CELL(CK_SCMI_LSI, CK_LSI, "ck_lsi", true), 171 CLOCK_CELL(CK_SCMI_HSE_DIV2, CK_HSE_DIV2, "clk-hse-div2", true), 172 CLOCK_CELL(CK_SCMI_PLL2_Q, PLL2_Q, "pll2_q", true), 173 CLOCK_CELL(CK_SCMI_PLL2_R, PLL2_R, "pll2_r", true), 174 CLOCK_CELL(CK_SCMI_PLL3_P, PLL3_P, "pll3_p", true), 175 CLOCK_CELL(CK_SCMI_PLL3_Q, PLL3_Q, "pll3_q", true), 176 CLOCK_CELL(CK_SCMI_PLL3_R, PLL3_R, "pll3_r", true), 177 CLOCK_CELL(CK_SCMI_PLL4_P, PLL4_P, "pll4_p", true), 178 CLOCK_CELL(CK_SCMI_PLL4_Q, PLL4_Q, "pll4_q", true), 179 CLOCK_CELL(CK_SCMI_PLL4_R, PLL4_R, "pll4_r", true), 180 CLOCK_CELL(CK_SCMI_MPU, CK_MPU, "ck_mpu", true), 181 CLOCK_CELL(CK_SCMI_AXI, CK_AXI, "ck_axi", true), 182 CLOCK_CELL(CK_SCMI_MLAHB, CK_MLAHB, "ck_mlahb", true), 183 CLOCK_CELL(CK_SCMI_CKPER, CK_PER, "ck_per", true), 184 CLOCK_CELL(CK_SCMI_PCLK1, PCLK1, "pclk1", true), 185 CLOCK_CELL(CK_SCMI_PCLK2, PCLK2, "pclk2", true), 186 CLOCK_CELL(CK_SCMI_PCLK3, PCLK3, "pclk3", true), 187 CLOCK_CELL(CK_SCMI_PCLK4, PCLK4, "pclk4", true), 188 CLOCK_CELL(CK_SCMI_PCLK5, PCLK5, "pclk5", true), 189 CLOCK_CELL(CK_SCMI_PCLK6, PCLK6, "pclk6", true), 190 CLOCK_CELL(CK_SCMI_CKTIMG1, CK_TIMG1, "timg1_ck", true), 191 CLOCK_CELL(CK_SCMI_CKTIMG2, CK_TIMG2, "timg2_ck", true), 192 CLOCK_CELL(CK_SCMI_CKTIMG3, CK_TIMG3, "timg3_ck", true), 193 CLOCK_CELL(CK_SCMI_RTC, RTC, "ck_rtc", true), 194 CLOCK_CELL(CK_SCMI_RTCAPB, RTCAPB, "rtcapb", true), 195 CLOCK_CELL(CK_SCMI_BSEC, BSEC, "bsec", true), 196 }; 197 #endif 198 199 #ifdef CFG_STM32MP15 200 static struct stm32_scmi_clk stm32_scmi_clock[] = { 201 CLOCK_CELL(CK_SCMI_HSE, CK_HSE, "ck_hse", true), 202 CLOCK_CELL(CK_SCMI_HSI, CK_HSI, "ck_hsi", true), 203 CLOCK_CELL(CK_SCMI_CSI, CK_CSI, "ck_csi", true), 204 CLOCK_CELL(CK_SCMI_LSE, CK_LSE, "ck_lse", true), 205 CLOCK_CELL(CK_SCMI_LSI, CK_LSI, "ck_lsi", true), 206 CLOCK_CELL(CK_SCMI_PLL2_Q, PLL2_Q, "pll2_q", true), 207 CLOCK_CELL(CK_SCMI_PLL2_R, PLL2_R, "pll2_r", true), 208 CLOCK_CELL(CK_SCMI_MPU, CK_MPU, "ck_mpu", true), 209 CLOCK_CELL(CK_SCMI_AXI, CK_AXI, "ck_axi", true), 210 CLOCK_CELL(CK_SCMI_BSEC, BSEC, "bsec", true), 211 CLOCK_CELL_DECPROT(CK_SCMI_CRYP1, CRYP1, "cryp1", false, 212 STM32MP1_ETZPC_CRYP1_ID), 213 CLOCK_CELL(CK_SCMI_GPIOZ, GPIOZ, "gpioz", false), 214 CLOCK_CELL_DECPROT(CK_SCMI_HASH1, HASH1, "hash1", false, 215 STM32MP1_ETZPC_HASH1_ID), 216 CLOCK_CELL_DECPROT(CK_SCMI_I2C4, I2C4_K, "i2c4_k", false, 217 STM32MP1_ETZPC_I2C4_ID), 218 CLOCK_CELL_DECPROT(CK_SCMI_I2C6, I2C6_K, "i2c6_k", false, 219 STM32MP1_ETZPC_I2C6_ID), 220 CLOCK_CELL_DECPROT(CK_SCMI_IWDG1, IWDG1, "iwdg1", false, 221 STM32MP1_ETZPC_IWDG1_ID), 222 CLOCK_CELL_DECPROT(CK_SCMI_RNG1, RNG1_K, "rng1_k", true, 223 STM32MP1_ETZPC_RNG1_ID), 224 CLOCK_CELL(CK_SCMI_RTC, RTC, "ck_rtc", true), 225 CLOCK_CELL(CK_SCMI_RTCAPB, RTCAPB, "rtcapb", true), 226 CLOCK_CELL_DECPROT(CK_SCMI_SPI6, SPI6_K, "spi6_k", false, 227 STM32MP1_ETZPC_SPI6_ID), 228 CLOCK_CELL_DECPROT(CK_SCMI_USART1, USART1_K, "usart1_k", false, 229 STM32MP1_ETZPC_USART1_ID), 230 }; 231 #endif 232 233 #ifdef CFG_STM32MP13 234 static struct stm32_scmi_rd stm32_scmi_reset_domain[] = { 235 RESET_CELL_DECPROT(RST_SCMI_LTDC, LTDC_R, "ltdc", 236 STM32MP1_ETZPC_LTDC_ID), 237 RESET_CELL(RST_SCMI_MDMA, MDMA_R, "mdma"), 238 }; 239 #endif 240 241 #ifdef CFG_STM32MP15 242 static struct stm32_scmi_rd stm32_scmi_reset_domain[] = { 243 RESET_CELL_DECPROT(RST_SCMI_SPI6, SPI6_R, "spi6", 244 STM32MP1_ETZPC_SPI6_ID), 245 RESET_CELL_DECPROT(RST_SCMI_I2C4, I2C4_R, "i2c4", 246 STM32MP1_ETZPC_I2C4_ID), 247 RESET_CELL_DECPROT(RST_SCMI_I2C6, I2C6_R, "i2c6", 248 STM32MP1_ETZPC_I2C6_ID), 249 RESET_CELL_DECPROT(RST_SCMI_USART1, USART1_R, "usart1", 250 STM32MP1_ETZPC_USART1_ID), 251 RESET_CELL_DECPROT(RST_SCMI_STGEN, STGEN_R, "stgen", 252 STM32MP1_ETZPC_STGENC_ID), 253 RESET_CELL_DECPROT(RST_SCMI_GPIOZ, GPIOZ_R, "gpioz", 254 ETZPC_ID_NEVER_ACCESSIBLE), 255 RESET_CELL_DECPROT(RST_SCMI_CRYP1, CRYP1_R, "cryp1", 256 STM32MP1_ETZPC_CRYP1_ID), 257 RESET_CELL_DECPROT(RST_SCMI_HASH1, HASH1_R, "hash1", 258 STM32MP1_ETZPC_HASH1_ID), 259 RESET_CELL_DECPROT(RST_SCMI_RNG1, RNG1_R, "rng1", 260 STM32MP1_ETZPC_RNG1_ID), 261 RESET_CELL(RST_SCMI_MDMA, MDMA_R, "mdma"), 262 RESET_CELL(RST_SCMI_MCU, MCU_R, "mcu"), 263 RESET_CELL(RST_SCMI_MCU_HOLD_BOOT, MCU_HOLD_BOOT_R, "mcu_hold_boot"), 264 }; 265 #endif 266 267 #ifdef CFG_STM32MP13 268 struct stm32_scmi_voltd scmi_voltage_domain[] = { 269 VOLTD_CELL_PWR(VOLTD_SCMI_REG11, PWR_REG11, "reg11"), 270 VOLTD_CELL_PWR(VOLTD_SCMI_REG18, PWR_REG18, "reg18"), 271 VOLTD_CELL_PWR(VOLTD_SCMI_USB33, PWR_USB33, "usb33"), 272 VOLTD_CELL_IOD(VOLTD_SCMI_SDMMC1_IO, IOD_SDMMC1, "sdmmc1"), 273 VOLTD_CELL_IOD(VOLTD_SCMI_SDMMC2_IO, IOD_SDMMC2, "sdmmc2"), 274 VOLTD_CELL_VREFBUF(VOLTD_SCMI_VREFBUF, "vrefbuf"), 275 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK1, "buck1", "buck1"), 276 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK2, "buck2", "buck2"), 277 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK3, "buck3", "buck3"), 278 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK4, "buck4", "buck4"), 279 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO1, "ldo1", "ldo1"), 280 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO2, "ldo2", "ldo2"), 281 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO3, "ldo3", "ldo3"), 282 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO4, "ldo4", "ldo4"), 283 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO5, "ldo5", "ldo5"), 284 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO6, "ldo6", "ldo6"), 285 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_VREFDDR, "vref_ddr", "vref_ddr"), 286 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BOOST, "boost", "bst_out"), 287 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_PWR_SW1, "pwr_sw1", "pwr_sw1"), 288 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_PWR_SW2, "pwr_sw2", "pwr_sw2"), 289 }; 290 #endif 291 292 #ifdef CFG_STM32MP15 293 struct stm32_scmi_voltd scmi_voltage_domain[] = { 294 VOLTD_CELL_PWR(VOLTD_SCMI_REG11, PWR_REG11, "reg11"), 295 VOLTD_CELL_PWR(VOLTD_SCMI_REG18, PWR_REG18, "reg18"), 296 VOLTD_CELL_PWR(VOLTD_SCMI_USB33, PWR_USB33, "usb33"), 297 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK1, "buck1", "vddcore"), 298 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK2, "buck2", "vdd_ddr"), 299 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK3, "buck3", "vdd"), 300 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BUCK4, "buck4", "v3v3"), 301 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO1, "ldo1", "v1v8_audio"), 302 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO2, "ldo2", "v3v3_hdmi"), 303 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO3, "ldo3", "vtt_ddr"), 304 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO4, "ldo4", "vdd_usb"), 305 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO5, "ldo5", "vdda"), 306 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_LDO6, "ldo6", "v1v2_hdmi"), 307 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_VREFDDR, "vref_ddr", "vref_ddr"), 308 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_BOOST, "boost", "bst_out"), 309 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_PWR_SW1, "pwr_sw1", "vbus_otg"), 310 VOLTD_CELL_PMIC(VOLTD_SCMI_STPMIC1_PWR_SW2, "pwr_sw2", "vbus_sw"), 311 }; 312 #endif 313 314 struct channel_resources { 315 struct scmi_msg_channel *channel; 316 struct stm32_scmi_clk *clock; 317 size_t clock_count; 318 struct stm32_scmi_rd *rd; 319 size_t rd_count; 320 struct stm32_scmi_voltd *voltd; 321 size_t voltd_count; 322 }; 323 324 static const struct channel_resources scmi_channel[] = { 325 [0] = { 326 .channel = &(struct scmi_msg_channel){ 327 #ifdef SMT_BUFFER_BASE 328 .shm_addr = { .pa = SMT_BUFFER_BASE }, 329 .shm_size = SMT_BUF_SLOT_SIZE, 330 #endif 331 }, 332 .clock = stm32_scmi_clock, 333 .clock_count = ARRAY_SIZE(stm32_scmi_clock), 334 .rd = stm32_scmi_reset_domain, 335 .rd_count = ARRAY_SIZE(stm32_scmi_reset_domain), 336 .voltd = scmi_voltage_domain, 337 .voltd_count = ARRAY_SIZE(scmi_voltage_domain), 338 }, 339 }; 340 341 static const struct channel_resources *find_resource(unsigned int channel_id) 342 { 343 assert(channel_id < ARRAY_SIZE(scmi_channel)); 344 345 return scmi_channel + channel_id; 346 } 347 348 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int channel_id) 349 { 350 const size_t max_id = ARRAY_SIZE(scmi_channel); 351 unsigned int confined_id = confine_array_index(channel_id, max_id); 352 353 if (channel_id >= max_id) 354 return NULL; 355 356 return find_resource(confined_id)->channel; 357 } 358 359 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 360 { 361 unsigned int n = 0; 362 unsigned int count = 0; 363 const size_t channel_count = ARRAY_SIZE(scmi_channel); 364 365 for (n = 0; n < channel_count; n++) 366 if (scmi_channel[n].clock_count) 367 break; 368 if (n < channel_count) 369 count++; 370 371 for (n = 0; n < channel_count; n++) 372 if (scmi_channel[n].rd_count) 373 break; 374 if (n < channel_count) 375 count++; 376 377 for (n = 0; n < channel_count; n++) 378 if (scmi_channel[n].voltd_count) 379 break; 380 if (n < channel_count) 381 count++; 382 383 return count; 384 } 385 386 static const char vendor[] = "ST"; 387 static const char sub_vendor[] = ""; 388 389 const char *plat_scmi_vendor_name(void) 390 { 391 return vendor; 392 } 393 394 const char *plat_scmi_sub_vendor_name(void) 395 { 396 return sub_vendor; 397 } 398 399 /* Currently supporting Clocks and Reset Domains */ 400 static const uint8_t plat_protocol_list[] = { 401 SCMI_PROTOCOL_ID_CLOCK, 402 SCMI_PROTOCOL_ID_RESET_DOMAIN, 403 SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, 404 0 /* Null termination */ 405 }; 406 407 size_t plat_scmi_protocol_count(void) 408 { 409 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 410 411 assert(count == plat_scmi_protocol_count_paranoid()); 412 413 return count; 414 } 415 416 const uint8_t *plat_scmi_protocol_list(unsigned int channel_id __unused) 417 { 418 assert(plat_scmi_protocol_count_paranoid() == 419 (ARRAY_SIZE(plat_protocol_list) - 1)); 420 421 return plat_protocol_list; 422 } 423 424 static bool nsec_can_access_resource(unsigned int etzpc_id) 425 { 426 static struct firewall_controller *etzpc_fw_ctrl; 427 uint32_t query_arg = DECPROT(etzpc_id, DECPROT_NS_RW, DECPROT_UNLOCK); 428 struct firewall_query query = { 429 .arg_count = 1, 430 .args = &query_arg, 431 .ctrl = etzpc_fw_ctrl, 432 }; 433 434 if (etzpc_id == ETZPC_ID_NEVER_ACCESSIBLE) 435 return false; 436 if (etzpc_id == ETZPC_ID_ALWAYS_ACCESSIBLE) 437 return true; 438 439 if (!etzpc_fw_ctrl) { 440 struct dt_driver_provider *prov = NULL; 441 int node = 0; 442 443 node = fdt_node_offset_by_compatible(get_embedded_dt(), -1, 444 "st,stm32-etzpc"); 445 if (node < 0) 446 panic(); 447 448 prov = dt_driver_get_provider_by_node(node, DT_DRIVER_FIREWALL); 449 if (!prov) 450 panic(); 451 452 etzpc_fw_ctrl = dt_driver_provider_priv_data(prov); 453 query.ctrl = etzpc_fw_ctrl; 454 } 455 456 return firewall_check_access(&query) == TEE_SUCCESS; 457 } 458 459 /* 460 * Platform SCMI clocks 461 */ 462 static struct stm32_scmi_clk *find_clock(unsigned int channel_id, 463 unsigned int scmi_id) 464 { 465 const struct channel_resources *resource = find_resource(channel_id); 466 size_t n = 0; 467 468 if (resource) { 469 for (n = 0; n < resource->clock_count; n++) 470 if (n == scmi_id) 471 return &resource->clock[n]; 472 } 473 474 return NULL; 475 } 476 477 size_t plat_scmi_clock_count(unsigned int channel_id) 478 { 479 const struct channel_resources *resource = find_resource(channel_id); 480 481 if (!resource) 482 return 0; 483 484 return resource->clock_count; 485 } 486 487 const char *plat_scmi_clock_get_name(unsigned int channel_id, 488 unsigned int scmi_id) 489 { 490 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 491 492 if (!clock || !nsec_can_access_resource(clock->etzpc_id)) 493 return NULL; 494 495 return clock->name; 496 } 497 498 int32_t plat_scmi_clock_rates_array(unsigned int channel_id, 499 unsigned int scmi_id, size_t start_index, 500 unsigned long *array, size_t *nb_elts) 501 { 502 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 503 504 if (!clock) 505 return SCMI_NOT_FOUND; 506 507 if (!nsec_can_access_resource(clock->etzpc_id)) 508 return SCMI_DENIED; 509 510 /* Exposed clocks are currently fixed rate clocks */ 511 if (start_index) 512 return SCMI_INVALID_PARAMETERS; 513 514 if (!array) 515 *nb_elts = 1; 516 else if (*nb_elts == 1) 517 *array = clk_get_rate(clock->clk); 518 else 519 return SCMI_GENERIC_ERROR; 520 521 return SCMI_SUCCESS; 522 } 523 524 unsigned long plat_scmi_clock_get_rate(unsigned int channel_id, 525 unsigned int scmi_id) 526 { 527 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 528 529 if (!clock || !nsec_can_access_resource(clock->etzpc_id)) 530 return 0; 531 532 return clk_get_rate(clock->clk); 533 } 534 535 int32_t plat_scmi_clock_get_state(unsigned int channel_id, unsigned int scmi_id) 536 { 537 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 538 539 if (!clock || !nsec_can_access_resource(clock->etzpc_id)) 540 return 0; 541 542 return (int32_t)clock->enabled; 543 } 544 545 int32_t plat_scmi_clock_set_state(unsigned int channel_id, unsigned int scmi_id, 546 bool enable_not_disable) 547 { 548 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 549 550 if (!clock) 551 return SCMI_NOT_FOUND; 552 553 if (!nsec_can_access_resource(clock->etzpc_id)) 554 return SCMI_DENIED; 555 556 if (enable_not_disable) { 557 if (!clock->enabled) { 558 FMSG("SCMI clock %u enable", scmi_id); 559 clk_enable(clock->clk); 560 clock->enabled = true; 561 } 562 } else { 563 if (clock->enabled) { 564 FMSG("SCMI clock %u disable", scmi_id); 565 clk_disable(clock->clk); 566 clock->enabled = false; 567 } 568 } 569 570 return SCMI_SUCCESS; 571 } 572 573 /* 574 * Platform SCMI reset domains 575 */ 576 static struct stm32_scmi_rd *find_rd(unsigned int channel_id, 577 unsigned int scmi_id) 578 { 579 const struct channel_resources *resource = find_resource(channel_id); 580 size_t n = 0; 581 582 if (resource) { 583 for (n = 0; n < resource->rd_count; n++) 584 if (n == scmi_id) 585 return &resource->rd[n]; 586 } 587 588 return NULL; 589 } 590 591 const char *plat_scmi_rd_get_name(unsigned int channel_id, unsigned int scmi_id) 592 { 593 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 594 595 if (!rd) 596 return NULL; 597 598 return rd->name; 599 } 600 601 size_t plat_scmi_rd_count(unsigned int channel_id) 602 { 603 const struct channel_resources *resource = find_resource(channel_id); 604 605 if (!resource) 606 return 0; 607 608 return resource->rd_count; 609 } 610 611 int32_t plat_scmi_rd_autonomous(unsigned int channel_id, unsigned int scmi_id, 612 uint32_t state) 613 { 614 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 615 616 if (!rd) 617 return SCMI_NOT_FOUND; 618 619 if (!rd->rstctrl || !nsec_can_access_resource(rd->etzpc_id)) 620 return SCMI_DENIED; 621 622 #ifdef CFG_STM32MP15 623 /* Reset cycle on MCU hold boot is not supported */ 624 if (rd->reset_id == MCU_HOLD_BOOT_R) 625 return SCMI_NOT_SUPPORTED; 626 /* Remoteproc driver may handle all MCU reset controllers */ 627 if (rd->reset_id == MCU_R && stm32_rproc_is_secure(STM32_M4_RPROC_ID)) 628 return SCMI_DENIED; 629 #endif 630 631 /* Supports only reset with context loss */ 632 if (state) 633 return SCMI_NOT_SUPPORTED; 634 635 FMSG("SCMI reset %u cycle", scmi_id); 636 637 if (rstctrl_assert_to(rd->rstctrl, TIMEOUT_US_1MS)) 638 return SCMI_HARDWARE_ERROR; 639 640 if (rstctrl_deassert_to(rd->rstctrl, TIMEOUT_US_1MS)) 641 return SCMI_HARDWARE_ERROR; 642 643 return SCMI_SUCCESS; 644 } 645 646 int32_t plat_scmi_rd_set_state(unsigned int channel_id, unsigned int scmi_id, 647 bool assert_not_deassert) 648 { 649 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 650 TEE_Result res = TEE_ERROR_GENERIC; 651 652 if (!rd) 653 return SCMI_NOT_FOUND; 654 655 if (!rd->rstctrl || !nsec_can_access_resource(rd->etzpc_id)) 656 return SCMI_DENIED; 657 658 #ifdef CFG_STM32MP15 659 /* Remoteproc driver may handle all MCU reset controllers */ 660 if ((rd->reset_id == MCU_R || rd->reset_id == MCU_HOLD_BOOT_R) && 661 stm32_rproc_is_secure(STM32_M4_RPROC_ID)) 662 return SCMI_DENIED; 663 #endif 664 665 if (assert_not_deassert) { 666 FMSG("SCMI reset %u set", scmi_id); 667 res = rstctrl_assert(rd->rstctrl); 668 } else { 669 FMSG("SCMI reset %u release", scmi_id); 670 res = rstctrl_deassert(rd->rstctrl); 671 } 672 673 if (res) 674 return SCMI_HARDWARE_ERROR; 675 676 return SCMI_SUCCESS; 677 } 678 679 /* 680 * Platform SCMI voltage domains 681 */ 682 static struct stm32_scmi_voltd *find_voltd(unsigned int channel_id, 683 unsigned int scmi_id) 684 { 685 const struct channel_resources *resource = find_resource(channel_id); 686 size_t n = 0; 687 688 if (resource) { 689 for (n = 0; n < resource->voltd_count; n++) 690 if (n == scmi_id) 691 return &resource->voltd[n]; 692 } 693 694 return NULL; 695 } 696 697 size_t plat_scmi_voltd_count(unsigned int channel_id) 698 { 699 const struct channel_resources *resource = find_resource(channel_id); 700 701 if (!resource) 702 return 0; 703 704 return resource->voltd_count; 705 } 706 707 const char *plat_scmi_voltd_get_name(unsigned int channel_id, 708 unsigned int scmi_id) 709 { 710 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 711 712 /* Currently non-secure is allowed to access all PWR regulators */ 713 if (!voltd) 714 return NULL; 715 716 return voltd->name; 717 } 718 719 int32_t plat_scmi_voltd_levels_array(unsigned int channel_id, 720 unsigned int scmi_id, size_t start_index, 721 long *out_levels, size_t *nb_elts) 722 723 { 724 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 725 726 if (!voltd) 727 return SCMI_NOT_FOUND; 728 729 if (voltd->regulator) { 730 struct regulator_voltages_desc *desc = NULL; 731 TEE_Result res = TEE_ERROR_GENERIC; 732 const int *levels = NULL; 733 size_t n = 0; 734 735 res = regulator_supported_voltages(voltd->regulator, &desc, 736 &levels); 737 if (res == TEE_ERROR_NOT_SUPPORTED) 738 return SCMI_NOT_SUPPORTED; 739 if (res) 740 return SCMI_GENERIC_ERROR; 741 if (!desc || desc->type != VOLTAGE_TYPE_FULL_LIST) { 742 /* 743 * Triplet min/max/step description. Caller should use 744 * plat_scmi_voltd_levels_by_step(). 745 */ 746 return SCMI_NOT_SUPPORTED; 747 } 748 749 if (start_index >= desc->num_levels) 750 return SCMI_OUT_OF_RANGE; 751 752 if (!*nb_elts) { 753 *nb_elts = desc->num_levels - start_index; 754 return SCMI_SUCCESS; 755 } 756 757 *nb_elts = MIN(*nb_elts, desc->num_levels - start_index); 758 for (n = 0; n < *nb_elts; n++) 759 out_levels[n] = levels[start_index + n]; 760 761 return SCMI_SUCCESS; 762 } 763 764 return SCMI_DENIED; 765 } 766 767 int32_t plat_scmi_voltd_levels_by_step(unsigned int channel_id, 768 unsigned int scmi_id, long *min_max_step) 769 { 770 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 771 772 if (!voltd) 773 return SCMI_NOT_FOUND; 774 775 if (voltd->regulator) { 776 struct regulator_voltages_desc *desc = NULL; 777 TEE_Result res = TEE_ERROR_GENERIC; 778 const int *levels = NULL; 779 780 res = regulator_supported_voltages(voltd->regulator, &desc, 781 &levels); 782 if (res == TEE_ERROR_NOT_SUPPORTED) 783 return SCMI_NOT_SUPPORTED; 784 if (res) 785 return SCMI_GENERIC_ERROR; 786 if (!desc || desc->type != VOLTAGE_TYPE_INCREMENT) { 787 /* 788 * Triplet min/max/step description. Caller should use 789 * plat_scmi_voltd_levels_by_step(). 790 */ 791 return SCMI_NOT_SUPPORTED; 792 } 793 794 min_max_step[0] = levels[0]; 795 min_max_step[1] = levels[1]; 796 min_max_step[2] = levels[2]; 797 798 return SCMI_SUCCESS; 799 } 800 801 return SCMI_NOT_SUPPORTED; 802 } 803 804 int32_t plat_scmi_voltd_get_level(unsigned int channel_id, unsigned int scmi_id, 805 long *level_uv) 806 { 807 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 808 809 if (!voltd) 810 return SCMI_INVALID_PARAMETERS; 811 812 if (voltd->regulator) { 813 *level_uv = regulator_get_voltage(voltd->regulator); 814 return SCMI_SUCCESS; 815 } 816 817 return SCMI_DENIED; 818 } 819 820 int32_t plat_scmi_voltd_set_level(unsigned int channel_id, unsigned int scmi_id, 821 long level_uv) 822 { 823 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 824 825 if (!voltd) 826 return SCMI_NOT_FOUND; 827 828 if (voltd->regulator) { 829 TEE_Result res = TEE_ERROR_GENERIC; 830 831 if (level_uv < INT_MIN || level_uv > INT_MAX) 832 return SCMI_OUT_OF_RANGE; 833 834 res = regulator_set_voltage(voltd->regulator, level_uv); 835 if (res) 836 return SCMI_GENERIC_ERROR; 837 else 838 return SCMI_SUCCESS; 839 } 840 841 return SCMI_DENIED; 842 } 843 844 int32_t plat_scmi_voltd_get_config(unsigned int channel_id, 845 unsigned int scmi_id, uint32_t *config) 846 { 847 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 848 849 if (!voltd) 850 return SCMI_NOT_FOUND; 851 852 if (voltd->regulator) { 853 if (voltd->state) 854 *config = SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 855 else 856 *config = SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 857 858 return SCMI_SUCCESS; 859 } 860 861 return SCMI_DENIED; 862 } 863 864 int32_t plat_scmi_voltd_set_config(unsigned int channel_id, 865 unsigned int scmi_id, uint32_t config) 866 { 867 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 868 869 if (!voltd) 870 return SCMI_NOT_FOUND; 871 872 if (voltd->regulator) { 873 switch (config) { 874 case SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON: 875 if (!voltd->state) { 876 if (regulator_enable(voltd->regulator)) 877 return SCMI_GENERIC_ERROR; 878 879 voltd->state = true; 880 } 881 break; 882 case SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF: 883 if (voltd->state) { 884 if (regulator_disable(voltd->regulator)) 885 return SCMI_GENERIC_ERROR; 886 887 voltd->state = false; 888 } 889 break; 890 default: 891 return SCMI_INVALID_PARAMETERS; 892 } 893 894 return SCMI_SUCCESS; 895 } 896 897 return SCMI_DENIED; 898 } 899 900 static void get_voltd_regulator(struct stm32_scmi_voltd *voltd) 901 { 902 switch (voltd->priv_dev) { 903 case VOLTD_PWR: 904 voltd->regulator = stm32mp1_pwr_get_regulator(voltd->priv_id); 905 break; 906 case VOLTD_PMIC: 907 voltd->regulator = stm32mp_pmic_get_regulator(voltd->priv_name); 908 break; 909 case VOLTD_VREFBUF: 910 voltd->regulator = stm32_vrefbuf_regulator(); 911 break; 912 case VOLTD_IOD: 913 voltd->regulator = stm32mp1_get_iod_regulator(voltd->priv_id); 914 break; 915 default: 916 break; 917 } 918 919 if (voltd->regulator && voltd->regulator->flags & REGULATOR_BOOT_ON) 920 regulator_enable(voltd->regulator); 921 } 922 923 /* 924 * Initialize platform SCMI resources 925 */ 926 static TEE_Result stm32mp1_init_scmi_server(void) 927 { 928 size_t i = 0; 929 size_t j = 0; 930 931 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 932 const struct channel_resources *res = scmi_channel + i; 933 struct scmi_msg_channel *chan = res->channel; 934 935 if (chan->shm_addr.pa) { 936 struct io_pa_va *addr = &chan->shm_addr; 937 938 /* Enforce non-secure shm mapped as device memory */ 939 addr->va = (vaddr_t)phys_to_virt(addr->pa, 940 MEM_AREA_IO_NSEC, 941 chan->shm_size); 942 assert(addr->va); 943 944 scmi_smt_init_agent_channel(chan); 945 } 946 947 for (j = 0; j < res->clock_count; j++) { 948 struct stm32_scmi_clk *clk = &res->clock[j]; 949 950 if (!clk->name || 951 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 952 panic("SCMI clock name invalid"); 953 954 clk->clk = stm32mp_rcc_clock_id_to_clk(clk->clock_id); 955 assert(clk->clk); 956 957 /* Sync SCMI clocks with their targeted initial state */ 958 if (clk->enabled && 959 nsec_can_access_resource(clk->etzpc_id)) 960 clk_enable(clk->clk); 961 } 962 963 for (j = 0; j < res->rd_count; j++) { 964 struct stm32_scmi_rd *rd = &res->rd[j]; 965 struct rstctrl *rstctrl = NULL; 966 967 if (!rd->name || 968 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 969 panic("SCMI reset domain name invalid"); 970 971 rstctrl = stm32mp_rcc_reset_id_to_rstctrl(rd->reset_id); 972 assert(rstctrl); 973 if (rstctrl_get_exclusive(rstctrl)) 974 continue; 975 976 rd->rstctrl = rstctrl; 977 } 978 979 for (j = 0; j < res->voltd_count; j++) { 980 struct stm32_scmi_voltd *voltd = &res->voltd[j]; 981 982 if (!voltd->name || 983 strlen(voltd->name) >= SCMI_VOLTD_NAME_SIZE) 984 panic("SCMI voltage domain name invalid"); 985 986 get_voltd_regulator(voltd); 987 } 988 } 989 990 return TEE_SUCCESS; 991 } 992 993 driver_init_late(stm32mp1_init_scmi_server); 994