1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019-2022, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <confine_array_index.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/rstctrl.h> 11 #include <drivers/scmi-msg.h> 12 #include <drivers/scmi.h> 13 #include <drivers/stm32mp1_pmic.h> 14 #include <drivers/stm32mp1_pwr.h> 15 #include <drivers/stpmic1.h> 16 #include <drivers/stpmic1_regulator.h> 17 #include <drivers/stm32mp_dt_bindings.h> 18 #include <initcall.h> 19 #include <mm/core_memprot.h> 20 #include <mm/core_mmu.h> 21 #include <platform_config.h> 22 #include <stdint.h> 23 #include <speculation_barrier.h> 24 #include <stm32_util.h> 25 #include <string.h> 26 #include <tee_api_defines.h> 27 #include <util.h> 28 29 #define TIMEOUT_US_1MS 1000 30 31 #define SCMI_CLOCK_NAME_SIZE 16 32 #define SCMI_RD_NAME_SIZE 16 33 #define SCMI_VOLTD_NAME_SIZE 16 34 35 /* 36 * struct stm32_scmi_clk - Data for the exposed clock 37 * @clock_id: Clock identifier in RCC clock driver 38 * @name: Clock string ID exposed to channel 39 * @enabled: State of the SCMI clock 40 */ 41 struct stm32_scmi_clk { 42 unsigned long clock_id; 43 struct clk *clk; 44 const char *name; 45 bool enabled; 46 }; 47 48 /* 49 * struct stm32_scmi_rd - Data for the exposed reset controller 50 * @reset_id: Reset identifier in RCC reset driver 51 * @name: Reset string ID exposed to channel 52 * @rstctrl: Reset controller device 53 */ 54 struct stm32_scmi_rd { 55 unsigned long reset_id; 56 const char *name; 57 struct rstctrl *rstctrl; 58 }; 59 60 enum voltd_device { 61 VOLTD_PWR, 62 VOLTD_PMIC, 63 /* Stub regulator until regulator framework is merged */ 64 VOLTD_STUB, 65 }; 66 67 /* 68 * struct stm32_scmi_voltd - Data for the exposed voltage domains 69 * @name: Power regulator string ID exposed to channel 70 * @priv_id: Internal string ID for the regulator 71 * @priv_dev: Internal ID for the device implementing the regulator 72 */ 73 struct stm32_scmi_voltd { 74 const char *name; 75 const char *priv_id; 76 enum voltd_device priv_dev; 77 78 }; 79 80 #if CFG_STM32MP1_SCMI_SHM_BASE 81 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 82 CFG_STM32MP1_SCMI_SHM_SIZE); 83 84 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 85 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 86 87 #if (SMT_BUFFER_BASE + SMT_BUF_SLOT_SIZE > \ 88 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 89 #error "SCMI shared memory mismatch" 90 #endif 91 #endif /*CFG_STM32MP1_SCMI_SHM_BASE*/ 92 93 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 94 [(_scmi_id)] = { \ 95 .clock_id = (_id), \ 96 .name = (_name), \ 97 .enabled = (_init_enabled), \ 98 } 99 100 #define RESET_CELL(_scmi_id, _id, _name) \ 101 [(_scmi_id)] = { \ 102 .reset_id = (_id), \ 103 .name = (_name), \ 104 } 105 106 #define VOLTD_CELL(_scmi_id, _dev_id, _priv_id, _name) \ 107 [(_scmi_id)] = { \ 108 .priv_id = (_priv_id), \ 109 .priv_dev = (_dev_id), \ 110 .name = (_name), \ 111 } 112 113 #ifdef CFG_STM32MP13 114 static struct stm32_scmi_clk stm32_scmi_clock[] = { 115 CLOCK_CELL(CK_SCMI_HSE, CK_HSE, "ck_hse", true), 116 CLOCK_CELL(CK_SCMI_HSI, CK_HSI, "ck_hsi", true), 117 CLOCK_CELL(CK_SCMI_CSI, CK_CSI, "ck_csi", true), 118 CLOCK_CELL(CK_SCMI_LSE, CK_LSE, "ck_lse", true), 119 CLOCK_CELL(CK_SCMI_LSI, CK_LSI, "ck_lsi", true), 120 CLOCK_CELL(CK_SCMI_HSE_DIV2, CK_HSE_DIV2, "clk-hse-div2", true), 121 CLOCK_CELL(CK_SCMI_PLL2_Q, PLL2_Q, "pll2_q", true), 122 CLOCK_CELL(CK_SCMI_PLL2_R, PLL2_R, "pll2_r", true), 123 CLOCK_CELL(CK_SCMI_PLL3_P, PLL3_P, "pll3_p", true), 124 CLOCK_CELL(CK_SCMI_PLL3_Q, PLL3_Q, "pll3_q", true), 125 CLOCK_CELL(CK_SCMI_PLL3_R, PLL3_R, "pll3_r", true), 126 CLOCK_CELL(CK_SCMI_PLL4_P, PLL4_P, "pll4_p", true), 127 CLOCK_CELL(CK_SCMI_PLL4_Q, PLL4_Q, "pll4_q", true), 128 CLOCK_CELL(CK_SCMI_PLL4_R, PLL4_R, "pll4_r", true), 129 CLOCK_CELL(CK_SCMI_MPU, CK_MPU, "ck_mpu", true), 130 CLOCK_CELL(CK_SCMI_AXI, CK_AXI, "ck_axi", true), 131 CLOCK_CELL(CK_SCMI_MLAHB, CK_MLAHB, "ck_mlahb", true), 132 CLOCK_CELL(CK_SCMI_CKPER, CK_PER, "ck_per", true), 133 CLOCK_CELL(CK_SCMI_PCLK1, PCLK1, "pclk1", true), 134 CLOCK_CELL(CK_SCMI_PCLK2, PCLK2, "pclk2", true), 135 CLOCK_CELL(CK_SCMI_PCLK3, PCLK3, "pclk3", true), 136 CLOCK_CELL(CK_SCMI_PCLK4, PCLK4, "pclk4", true), 137 CLOCK_CELL(CK_SCMI_PCLK5, PCLK5, "pclk5", true), 138 CLOCK_CELL(CK_SCMI_PCLK6, PCLK6, "pclk6", true), 139 CLOCK_CELL(CK_SCMI_CKTIMG1, CK_TIMG1, "timg1_ck", true), 140 CLOCK_CELL(CK_SCMI_CKTIMG2, CK_TIMG2, "timg2_ck", true), 141 CLOCK_CELL(CK_SCMI_CKTIMG3, CK_TIMG3, "timg3_ck", true), 142 CLOCK_CELL(CK_SCMI_RTC, RTC, "ck_rtc", true), 143 CLOCK_CELL(CK_SCMI_RTCAPB, RTCAPB, "rtcapb", true), 144 CLOCK_CELL(CK_SCMI_BSEC, BSEC, "bsec", true), 145 }; 146 #endif 147 148 #ifdef CFG_STM32MP15 149 static struct stm32_scmi_clk stm32_scmi_clock[] = { 150 CLOCK_CELL(CK_SCMI_HSE, CK_HSE, "ck_hse", true), 151 CLOCK_CELL(CK_SCMI_HSI, CK_HSI, "ck_hsi", true), 152 CLOCK_CELL(CK_SCMI_CSI, CK_CSI, "ck_csi", true), 153 CLOCK_CELL(CK_SCMI_LSE, CK_LSE, "ck_lse", true), 154 CLOCK_CELL(CK_SCMI_LSI, CK_LSI, "ck_lsi", true), 155 CLOCK_CELL(CK_SCMI_PLL2_Q, PLL2_Q, "pll2_q", true), 156 CLOCK_CELL(CK_SCMI_PLL2_R, PLL2_R, "pll2_r", true), 157 CLOCK_CELL(CK_SCMI_MPU, CK_MPU, "ck_mpu", true), 158 CLOCK_CELL(CK_SCMI_AXI, CK_AXI, "ck_axi", true), 159 CLOCK_CELL(CK_SCMI_BSEC, BSEC, "bsec", true), 160 CLOCK_CELL(CK_SCMI_CRYP1, CRYP1, "cryp1", false), 161 CLOCK_CELL(CK_SCMI_GPIOZ, GPIOZ, "gpioz", false), 162 CLOCK_CELL(CK_SCMI_HASH1, HASH1, "hash1", false), 163 CLOCK_CELL(CK_SCMI_I2C4, I2C4_K, "i2c4_k", false), 164 CLOCK_CELL(CK_SCMI_I2C6, I2C6_K, "i2c6_k", false), 165 CLOCK_CELL(CK_SCMI_IWDG1, IWDG1, "iwdg1", false), 166 CLOCK_CELL(CK_SCMI_RNG1, RNG1_K, "rng1_k", true), 167 CLOCK_CELL(CK_SCMI_RTC, RTC, "ck_rtc", true), 168 CLOCK_CELL(CK_SCMI_RTCAPB, RTCAPB, "rtcapb", true), 169 CLOCK_CELL(CK_SCMI_SPI6, SPI6_K, "spi6_k", false), 170 CLOCK_CELL(CK_SCMI_USART1, USART1_K, "usart1_k", false), 171 }; 172 #endif 173 174 #ifdef CFG_STM32MP13 175 static struct stm32_scmi_rd stm32_scmi_reset_domain[] = { 176 RESET_CELL(RST_SCMI_LTDC, LTDC_R, "ltdc"), 177 RESET_CELL(RST_SCMI_MDMA, MDMA_R, "mdma"), 178 }; 179 #endif 180 181 #ifdef CFG_STM32MP15 182 static struct stm32_scmi_rd stm32_scmi_reset_domain[] = { 183 RESET_CELL(RST_SCMI_SPI6, SPI6_R, "spi6"), 184 RESET_CELL(RST_SCMI_I2C4, I2C4_R, "i2c4"), 185 RESET_CELL(RST_SCMI_I2C6, I2C6_R, "i2c6"), 186 RESET_CELL(RST_SCMI_USART1, USART1_R, "usart1"), 187 RESET_CELL(RST_SCMI_STGEN, STGEN_R, "stgen"), 188 RESET_CELL(RST_SCMI_GPIOZ, GPIOZ_R, "gpioz"), 189 RESET_CELL(RST_SCMI_CRYP1, CRYP1_R, "cryp1"), 190 RESET_CELL(RST_SCMI_HASH1, HASH1_R, "hash1"), 191 RESET_CELL(RST_SCMI_RNG1, RNG1_R, "rng1"), 192 RESET_CELL(RST_SCMI_MDMA, MDMA_R, "mdma"), 193 RESET_CELL(RST_SCMI_MCU, MCU_R, "mcu"), 194 RESET_CELL(RST_SCMI_MCU_HOLD_BOOT, MCU_HOLD_BOOT_R, "mcu_hold_boot"), 195 }; 196 #endif 197 198 #define PWR_REG11_NAME_ID "0" 199 #define PWR_REG18_NAME_ID "1" 200 #define PWR_USB33_NAME_ID "2" 201 202 #define STUB_SDMMC1_IO_NAME_ID "sdmmc1" 203 #define STUB_SDMMC2_IO_NAME_ID "sdmmc2" 204 #define STUB_VREFBUF_NAME_ID "vrefbuf" 205 206 #ifdef CFG_STM32MP13 207 struct stm32_scmi_voltd scmi_voltage_domain[] = { 208 VOLTD_CELL(VOLTD_SCMI_REG11, VOLTD_PWR, PWR_REG11_NAME_ID, "reg11"), 209 VOLTD_CELL(VOLTD_SCMI_REG18, VOLTD_PWR, PWR_REG18_NAME_ID, "reg18"), 210 VOLTD_CELL(VOLTD_SCMI_USB33, VOLTD_PWR, PWR_USB33_NAME_ID, "usb33"), 211 VOLTD_CELL(VOLTD_SCMI_SDMMC1_IO, VOLTD_STUB, STUB_SDMMC1_IO_NAME_ID, 212 "sdmmc1"), 213 VOLTD_CELL(VOLTD_SCMI_SDMMC2_IO, VOLTD_STUB, STUB_SDMMC2_IO_NAME_ID, 214 "sdmmc2"), 215 VOLTD_CELL(VOLTD_SCMI_VREFBUF, VOLTD_STUB, STUB_VREFBUF_NAME_ID, 216 "vrefbuf"), 217 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK1, VOLTD_PMIC, "buck1", "buck1"), 218 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK2, VOLTD_PMIC, "buck2", "buck2"), 219 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK3, VOLTD_PMIC, "buck3", "buck3"), 220 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK4, VOLTD_PMIC, "buck4", "buck4"), 221 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO1, VOLTD_PMIC, "ldo1", "ldo1"), 222 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO2, VOLTD_PMIC, "ldo2", "ldo2"), 223 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO3, VOLTD_PMIC, "ldo3", "ldo3"), 224 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO4, VOLTD_PMIC, "ldo4", "ldo4"), 225 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO5, VOLTD_PMIC, "ldo5", "ldo5"), 226 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO6, VOLTD_PMIC, "ldo6", "ldo6"), 227 VOLTD_CELL(VOLTD_SCMI_STPMIC1_VREFDDR, VOLTD_PMIC, "vref_ddr", 228 "vref_ddr"), 229 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BOOST, VOLTD_PMIC, "boost", "bst_out"), 230 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW1, VOLTD_PMIC, "pwr_sw1", 231 "pwr_sw1"), 232 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW2, VOLTD_PMIC, "pwr_sw2", 233 "pwr_sw2"), 234 }; 235 #endif 236 237 #ifdef CFG_STM32MP15 238 struct stm32_scmi_voltd scmi_voltage_domain[] = { 239 VOLTD_CELL(VOLTD_SCMI_REG11, VOLTD_PWR, PWR_REG11_NAME_ID, "reg11"), 240 VOLTD_CELL(VOLTD_SCMI_REG18, VOLTD_PWR, PWR_REG18_NAME_ID, "reg18"), 241 VOLTD_CELL(VOLTD_SCMI_USB33, VOLTD_PWR, PWR_USB33_NAME_ID, "usb33"), 242 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK1, VOLTD_PMIC, "buck1", "vddcore"), 243 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK2, VOLTD_PMIC, "buck2", "vdd_ddr"), 244 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK3, VOLTD_PMIC, "buck3", "vdd"), 245 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK4, VOLTD_PMIC, "buck4", "v3v3"), 246 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO1, VOLTD_PMIC, "ldo1", "v1v8_audio"), 247 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO2, VOLTD_PMIC, "ldo2", "v3v3_hdmi"), 248 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO3, VOLTD_PMIC, "ldo3", "vtt_ddr"), 249 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO4, VOLTD_PMIC, "ldo4", "vdd_usb"), 250 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO5, VOLTD_PMIC, "ldo5", "vdda"), 251 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO6, VOLTD_PMIC, "ldo6", "v1v2_hdmi"), 252 VOLTD_CELL(VOLTD_SCMI_STPMIC1_VREFDDR, VOLTD_PMIC, "vref_ddr", 253 "vref_ddr"), 254 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BOOST, VOLTD_PMIC, "boost", "bst_out"), 255 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW1, VOLTD_PMIC, "pwr_sw1", 256 "vbus_otg"), 257 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW2, VOLTD_PMIC, "pwr_sw2", 258 "vbus_sw"), 259 }; 260 #endif 261 262 struct channel_resources { 263 struct scmi_msg_channel *channel; 264 struct stm32_scmi_clk *clock; 265 size_t clock_count; 266 struct stm32_scmi_rd *rd; 267 size_t rd_count; 268 struct stm32_scmi_voltd *voltd; 269 size_t voltd_count; 270 }; 271 272 static const struct channel_resources scmi_channel[] = { 273 [0] = { 274 .channel = &(struct scmi_msg_channel){ 275 #ifdef SMT_BUFFER_BASE 276 .shm_addr = { .pa = SMT_BUFFER_BASE }, 277 .shm_size = SMT_BUF_SLOT_SIZE, 278 #endif 279 }, 280 .clock = stm32_scmi_clock, 281 .clock_count = ARRAY_SIZE(stm32_scmi_clock), 282 .rd = stm32_scmi_reset_domain, 283 .rd_count = ARRAY_SIZE(stm32_scmi_reset_domain), 284 .voltd = scmi_voltage_domain, 285 .voltd_count = ARRAY_SIZE(scmi_voltage_domain), 286 }, 287 }; 288 289 static const struct channel_resources *find_resource(unsigned int channel_id) 290 { 291 assert(channel_id < ARRAY_SIZE(scmi_channel)); 292 293 return scmi_channel + channel_id; 294 } 295 296 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int channel_id) 297 { 298 const size_t max_id = ARRAY_SIZE(scmi_channel); 299 unsigned int confined_id = confine_array_index(channel_id, max_id); 300 301 if (channel_id >= max_id) 302 return NULL; 303 304 return find_resource(confined_id)->channel; 305 } 306 307 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 308 { 309 unsigned int n = 0; 310 unsigned int count = 0; 311 const size_t channel_count = ARRAY_SIZE(scmi_channel); 312 313 for (n = 0; n < channel_count; n++) 314 if (scmi_channel[n].clock_count) 315 break; 316 if (n < channel_count) 317 count++; 318 319 for (n = 0; n < channel_count; n++) 320 if (scmi_channel[n].rd_count) 321 break; 322 if (n < channel_count) 323 count++; 324 325 for (n = 0; n < channel_count; n++) 326 if (scmi_channel[n].voltd_count) 327 break; 328 if (n < channel_count) 329 count++; 330 331 return count; 332 } 333 334 static const char vendor[] = "ST"; 335 static const char sub_vendor[] = ""; 336 337 const char *plat_scmi_vendor_name(void) 338 { 339 return vendor; 340 } 341 342 const char *plat_scmi_sub_vendor_name(void) 343 { 344 return sub_vendor; 345 } 346 347 /* Currently supporting Clocks and Reset Domains */ 348 static const uint8_t plat_protocol_list[] = { 349 SCMI_PROTOCOL_ID_CLOCK, 350 SCMI_PROTOCOL_ID_RESET_DOMAIN, 351 SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, 352 0 /* Null termination */ 353 }; 354 355 size_t plat_scmi_protocol_count(void) 356 { 357 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 358 359 assert(count == plat_scmi_protocol_count_paranoid()); 360 361 return count; 362 } 363 364 const uint8_t *plat_scmi_protocol_list(unsigned int channel_id __unused) 365 { 366 assert(plat_scmi_protocol_count_paranoid() == 367 (ARRAY_SIZE(plat_protocol_list) - 1)); 368 369 return plat_protocol_list; 370 } 371 372 /* 373 * Platform SCMI clocks 374 */ 375 static struct stm32_scmi_clk *find_clock(unsigned int channel_id, 376 unsigned int scmi_id) 377 { 378 const struct channel_resources *resource = find_resource(channel_id); 379 size_t n = 0; 380 381 if (resource) { 382 for (n = 0; n < resource->clock_count; n++) 383 if (n == scmi_id) 384 return &resource->clock[n]; 385 } 386 387 return NULL; 388 } 389 390 size_t plat_scmi_clock_count(unsigned int channel_id) 391 { 392 const struct channel_resources *resource = find_resource(channel_id); 393 394 if (!resource) 395 return 0; 396 397 return resource->clock_count; 398 } 399 400 const char *plat_scmi_clock_get_name(unsigned int channel_id, 401 unsigned int scmi_id) 402 { 403 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 404 405 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 406 return NULL; 407 408 return clock->name; 409 } 410 411 int32_t plat_scmi_clock_rates_array(unsigned int channel_id, 412 unsigned int scmi_id, size_t start_index, 413 unsigned long *array, size_t *nb_elts) 414 { 415 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 416 417 if (!clock) 418 return SCMI_NOT_FOUND; 419 420 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 421 return SCMI_DENIED; 422 423 /* Exposed clocks are currently fixed rate clocks */ 424 if (start_index) 425 return SCMI_INVALID_PARAMETERS; 426 427 if (!array) 428 *nb_elts = 1; 429 else if (*nb_elts == 1) 430 *array = clk_get_rate(clock->clk); 431 else 432 return SCMI_GENERIC_ERROR; 433 434 return SCMI_SUCCESS; 435 } 436 437 unsigned long plat_scmi_clock_get_rate(unsigned int channel_id, 438 unsigned int scmi_id) 439 { 440 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 441 442 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 443 return 0; 444 445 return clk_get_rate(clock->clk); 446 } 447 448 int32_t plat_scmi_clock_get_state(unsigned int channel_id, unsigned int scmi_id) 449 { 450 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 451 452 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 453 return 0; 454 455 return (int32_t)clock->enabled; 456 } 457 458 int32_t plat_scmi_clock_set_state(unsigned int channel_id, unsigned int scmi_id, 459 bool enable_not_disable) 460 { 461 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 462 463 if (!clock) 464 return SCMI_NOT_FOUND; 465 466 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 467 return SCMI_DENIED; 468 469 if (enable_not_disable) { 470 if (!clock->enabled) { 471 FMSG("SCMI clock %u enable", scmi_id); 472 clk_enable(clock->clk); 473 clock->enabled = true; 474 } 475 } else { 476 if (clock->enabled) { 477 FMSG("SCMI clock %u disable", scmi_id); 478 clk_disable(clock->clk); 479 clock->enabled = false; 480 } 481 } 482 483 return SCMI_SUCCESS; 484 } 485 486 /* 487 * Platform SCMI reset domains 488 */ 489 static struct stm32_scmi_rd *find_rd(unsigned int channel_id, 490 unsigned int scmi_id) 491 { 492 const struct channel_resources *resource = find_resource(channel_id); 493 size_t n = 0; 494 495 if (resource) { 496 for (n = 0; n < resource->rd_count; n++) 497 if (n == scmi_id) 498 return &resource->rd[n]; 499 } 500 501 return NULL; 502 } 503 504 const char *plat_scmi_rd_get_name(unsigned int channel_id, unsigned int scmi_id) 505 { 506 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 507 508 if (!rd) 509 return NULL; 510 511 return rd->name; 512 } 513 514 size_t plat_scmi_rd_count(unsigned int channel_id) 515 { 516 const struct channel_resources *resource = find_resource(channel_id); 517 518 if (!resource) 519 return 0; 520 521 return resource->rd_count; 522 } 523 524 int32_t plat_scmi_rd_autonomous(unsigned int channel_id, unsigned int scmi_id, 525 uint32_t state) 526 { 527 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 528 529 if (!rd) 530 return SCMI_NOT_FOUND; 531 532 if (!rd->rstctrl || !stm32mp_nsec_can_access_reset(rd->reset_id)) 533 return SCMI_DENIED; 534 assert(rd->rstctrl); 535 536 #ifdef CFG_STM32MP15 537 if (rd->reset_id == MCU_HOLD_BOOT_R) 538 return SCMI_NOT_SUPPORTED; 539 #endif 540 541 /* Supports only reset with context loss */ 542 if (state) 543 return SCMI_NOT_SUPPORTED; 544 545 FMSG("SCMI reset %u cycle", scmi_id); 546 547 if (rstctrl_assert_to(rd->rstctrl, TIMEOUT_US_1MS)) 548 return SCMI_HARDWARE_ERROR; 549 550 if (rstctrl_deassert_to(rd->rstctrl, TIMEOUT_US_1MS)) 551 return SCMI_HARDWARE_ERROR; 552 553 return SCMI_SUCCESS; 554 } 555 556 int32_t plat_scmi_rd_set_state(unsigned int channel_id, unsigned int scmi_id, 557 bool assert_not_deassert) 558 { 559 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 560 TEE_Result res = TEE_ERROR_GENERIC; 561 562 if (!rd) 563 return SCMI_NOT_FOUND; 564 565 if (!rd->rstctrl || !stm32mp_nsec_can_access_reset(rd->reset_id)) 566 return SCMI_DENIED; 567 assert(rd->rstctrl); 568 569 if (assert_not_deassert) { 570 FMSG("SCMI reset %u set", scmi_id); 571 res = rstctrl_assert(rd->rstctrl); 572 } else { 573 FMSG("SCMI reset %u release", scmi_id); 574 res = rstctrl_deassert(rd->rstctrl); 575 } 576 577 if (res) 578 return SCMI_HARDWARE_ERROR; 579 580 return SCMI_SUCCESS; 581 } 582 583 /* 584 * Platform SCMI voltage domains 585 */ 586 static struct stm32_scmi_voltd *find_voltd(unsigned int channel_id, 587 unsigned int scmi_id) 588 { 589 const struct channel_resources *resource = find_resource(channel_id); 590 size_t n = 0; 591 592 if (resource) { 593 for (n = 0; n < resource->voltd_count; n++) 594 if (n == scmi_id) 595 return &resource->voltd[n]; 596 } 597 598 return NULL; 599 } 600 601 size_t plat_scmi_voltd_count(unsigned int channel_id) 602 { 603 const struct channel_resources *resource = find_resource(channel_id); 604 605 if (!resource) 606 return 0; 607 608 return resource->voltd_count; 609 } 610 611 const char *plat_scmi_voltd_get_name(unsigned int channel_id, 612 unsigned int scmi_id) 613 { 614 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 615 616 /* Currently non-secure is allowed to access all PWR regulators */ 617 if (!voltd) 618 return NULL; 619 620 return voltd->name; 621 } 622 623 static enum pwr_regulator pwr_scmi_to_regu_id(struct stm32_scmi_voltd *voltd) 624 { 625 if (!strcmp(voltd->priv_id, PWR_REG11_NAME_ID)) 626 return PWR_REG11; 627 if (!strcmp(voltd->priv_id, PWR_REG18_NAME_ID)) 628 return PWR_REG18; 629 if (!strcmp(voltd->priv_id, PWR_USB33_NAME_ID)) 630 return PWR_USB33; 631 632 panic(); 633 } 634 635 static long pwr_get_level(struct stm32_scmi_voltd *voltd) 636 { 637 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 638 639 return (long)stm32mp1_pwr_regulator_mv(regu_id) * 1000; 640 } 641 642 static int32_t pwr_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 643 { 644 if (level_uv != pwr_get_level(voltd)) 645 return SCMI_INVALID_PARAMETERS; 646 647 return SCMI_SUCCESS; 648 } 649 650 static int32_t pwr_describe_levels(struct stm32_scmi_voltd *voltd, 651 size_t start_index, long *microvolt, 652 size_t *nb_elts) 653 { 654 if (start_index) 655 return SCMI_INVALID_PARAMETERS; 656 657 if (!microvolt) { 658 *nb_elts = 1; 659 return SCMI_SUCCESS; 660 } 661 662 if (*nb_elts < 1) 663 return SCMI_GENERIC_ERROR; 664 665 *nb_elts = 1; 666 *microvolt = pwr_get_level(voltd); 667 668 return SCMI_SUCCESS; 669 } 670 671 static uint32_t pwr_get_state(struct stm32_scmi_voltd *voltd) 672 { 673 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 674 675 if (stm32mp1_pwr_regulator_is_enabled(regu_id)) 676 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 677 678 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 679 } 680 681 static void pwr_set_state(struct stm32_scmi_voltd *voltd, bool enable) 682 { 683 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 684 685 FMSG("%sable PWR %s (was %s)", enable ? "En" : "Dis", voltd->name, 686 stm32mp1_pwr_regulator_is_enabled(regu_id) ? "on" : "off"); 687 688 stm32mp1_pwr_regulator_set_state(regu_id, enable); 689 } 690 691 static int32_t pmic_describe_levels(struct stm32_scmi_voltd *voltd, 692 size_t start_index, long *microvolt, 693 size_t *nb_elts) 694 { 695 const uint16_t *levels = NULL; 696 size_t full_count = 0; 697 size_t out_count = 0; 698 size_t i = 0; 699 700 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 701 return SCMI_DENIED; 702 703 stpmic1_regulator_levels_mv(voltd->priv_id, &levels, &full_count); 704 705 if (!microvolt) { 706 *nb_elts = full_count - start_index; 707 return SCMI_SUCCESS; 708 } 709 710 if (SUB_OVERFLOW(full_count, start_index, &out_count)) 711 return SCMI_GENERIC_ERROR; 712 713 out_count = MIN(out_count, *nb_elts); 714 715 FMSG("%zu levels: start %zu requested %zu output %zu", 716 full_count, start_index, *nb_elts, out_count); 717 718 for (i = 0; i < out_count; i++) 719 microvolt[i] = levels[start_index + i] * 1000; 720 721 *nb_elts = out_count; 722 723 return SCMI_SUCCESS; 724 } 725 726 static long pmic_get_level(struct stm32_scmi_voltd *voltd) 727 { 728 unsigned long level_mv = 0; 729 730 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 731 return 0; 732 733 stm32mp_get_pmic(); 734 level_mv = stpmic1_regulator_voltage_get(voltd->priv_id); 735 stm32mp_put_pmic(); 736 737 return (long)level_mv * 1000; 738 } 739 740 static int32_t pmic_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 741 { 742 int rc = 0; 743 unsigned int level_mv = 0; 744 745 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 746 return SCMI_DENIED; 747 748 if (level_uv < 0 || level_uv > (UINT16_MAX * 1000)) 749 return SCMI_INVALID_PARAMETERS; 750 751 level_mv = (unsigned int)level_uv / 1000; 752 753 FMSG("Set STPMIC1 regulator %s level to %dmV", voltd->name, level_mv); 754 755 stm32mp_get_pmic(); 756 rc = stpmic1_regulator_voltage_set(voltd->priv_id, level_mv); 757 stm32mp_put_pmic(); 758 759 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 760 } 761 762 static uint32_t pmic_get_state(struct stm32_scmi_voltd *voltd) 763 { 764 bool enabled = false; 765 766 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 767 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 768 769 stm32mp_get_pmic(); 770 enabled = stpmic1_is_regulator_enabled(voltd->priv_id); 771 stm32mp_put_pmic(); 772 773 if (enabled) 774 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 775 776 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 777 } 778 779 static int32_t pmic_set_state(struct stm32_scmi_voltd *voltd, bool enable) 780 { 781 int rc = 0; 782 783 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 784 return SCMI_DENIED; 785 786 stm32mp_get_pmic(); 787 788 FMSG("%sable STPMIC1 %s (was %s)", enable ? "En" : "Dis", voltd->name, 789 stpmic1_is_regulator_enabled(voltd->priv_id) ? "on" : "off"); 790 791 if (enable) 792 rc = stpmic1_regulator_enable(voltd->priv_id); 793 else 794 rc = stpmic1_regulator_disable(voltd->priv_id); 795 796 stm32mp_put_pmic(); 797 798 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 799 } 800 801 static long stub_get_level_uv(struct stm32_scmi_voltd *voltd) 802 { 803 if (!strcmp(voltd->priv_id, STUB_SDMMC1_IO_NAME_ID) || 804 !strcmp(voltd->priv_id, STUB_SDMMC2_IO_NAME_ID)) 805 return 3300000; 806 807 if (!strcmp(voltd->priv_id, STUB_VREFBUF_NAME_ID)) 808 return 0; 809 810 panic(); 811 } 812 813 static int32_t stub_describe_levels(struct stm32_scmi_voltd *voltd __unused, 814 size_t start_index, long *microvolt, 815 size_t *nb_elts) 816 { 817 if (start_index) 818 return SCMI_INVALID_PARAMETERS; 819 820 if (!microvolt || !*nb_elts) { 821 *nb_elts = 1; 822 return SCMI_SUCCESS; 823 } 824 825 microvolt[0] = stub_get_level_uv(voltd); 826 *nb_elts = 1; 827 828 return SCMI_SUCCESS; 829 } 830 831 int32_t plat_scmi_voltd_levels_array(unsigned int channel_id, 832 unsigned int scmi_id, size_t start_index, 833 long *levels, size_t *nb_elts) 834 835 { 836 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 837 838 if (!voltd) 839 return SCMI_NOT_FOUND; 840 841 switch (voltd->priv_dev) { 842 case VOLTD_PWR: 843 return pwr_describe_levels(voltd, start_index, levels, nb_elts); 844 case VOLTD_PMIC: 845 return pmic_describe_levels(voltd, start_index, levels, 846 nb_elts); 847 case VOLTD_STUB: 848 return stub_describe_levels(voltd, start_index, levels, 849 nb_elts); 850 default: 851 return SCMI_GENERIC_ERROR; 852 } 853 } 854 855 int32_t plat_scmi_voltd_get_level(unsigned int channel_id, unsigned int scmi_id, 856 long *level) 857 { 858 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 859 long voltage = 0; 860 861 if (!voltd) 862 return SCMI_INVALID_PARAMETERS; 863 864 switch (voltd->priv_dev) { 865 case VOLTD_PWR: 866 *level = pwr_get_level(voltd); 867 return SCMI_SUCCESS; 868 case VOLTD_PMIC: 869 voltage = pmic_get_level(voltd); 870 if (voltage > 0) { 871 *level = voltage; 872 return SCMI_SUCCESS; 873 } else { 874 return SCMI_GENERIC_ERROR; 875 } 876 case VOLTD_STUB: 877 *level = stub_get_level_uv(voltd); 878 return SCMI_SUCCESS; 879 default: 880 panic(); 881 } 882 } 883 884 int32_t plat_scmi_voltd_set_level(unsigned int channel_id, unsigned int scmi_id, 885 long level) 886 { 887 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 888 889 if (!voltd) 890 return SCMI_NOT_FOUND; 891 892 switch (voltd->priv_dev) { 893 case VOLTD_PWR: 894 return pwr_set_level(voltd, level); 895 case VOLTD_PMIC: 896 return pmic_set_level(voltd, level); 897 case VOLTD_STUB: 898 return SCMI_SUCCESS; 899 default: 900 return SCMI_GENERIC_ERROR; 901 } 902 } 903 904 int32_t plat_scmi_voltd_get_config(unsigned int channel_id, 905 unsigned int scmi_id, uint32_t *config) 906 { 907 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 908 909 if (!voltd) 910 return SCMI_NOT_FOUND; 911 912 switch (voltd->priv_dev) { 913 case VOLTD_PWR: 914 *config = pwr_get_state(voltd); 915 break; 916 case VOLTD_PMIC: 917 *config = pmic_get_state(voltd); 918 break; 919 case VOLTD_STUB: 920 *config = SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 921 return SCMI_SUCCESS; 922 default: 923 return SCMI_GENERIC_ERROR; 924 } 925 926 return SCMI_SUCCESS; 927 } 928 929 int32_t plat_scmi_voltd_set_config(unsigned int channel_id, 930 unsigned int scmi_id, uint32_t config) 931 { 932 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 933 int32_t rc = SCMI_SUCCESS; 934 935 if (!voltd) 936 return SCMI_NOT_FOUND; 937 938 switch (voltd->priv_dev) { 939 case VOLTD_PWR: 940 pwr_set_state(voltd, config); 941 break; 942 case VOLTD_PMIC: 943 rc = pmic_set_state(voltd, config); 944 break; 945 case VOLTD_STUB: 946 break; 947 default: 948 return SCMI_GENERIC_ERROR; 949 } 950 951 return rc; 952 } 953 954 /* 955 * Initialize platform SCMI resources 956 */ 957 static TEE_Result stm32mp1_init_scmi_server(void) 958 { 959 size_t i = 0; 960 size_t j = 0; 961 962 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 963 const struct channel_resources *res = scmi_channel + i; 964 struct scmi_msg_channel *chan = res->channel; 965 966 if (chan->shm_addr.pa) { 967 struct io_pa_va *addr = &chan->shm_addr; 968 969 /* Enforce non-secure shm mapped as device memory */ 970 addr->va = (vaddr_t)phys_to_virt(addr->pa, 971 MEM_AREA_IO_NSEC, 972 chan->shm_size); 973 assert(addr->va); 974 975 scmi_smt_init_agent_channel(chan); 976 } 977 978 for (j = 0; j < res->clock_count; j++) { 979 struct stm32_scmi_clk *clk = &res->clock[j]; 980 981 if (!clk->name || 982 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 983 panic("SCMI clock name invalid"); 984 985 clk->clk = stm32mp_rcc_clock_id_to_clk(clk->clock_id); 986 assert(clk->clk); 987 988 /* Sync SCMI clocks with their targeted initial state */ 989 if (clk->enabled && 990 stm32mp_nsec_can_access_clock(clk->clock_id)) 991 clk_enable(clk->clk); 992 } 993 994 for (j = 0; j < res->rd_count; j++) { 995 struct stm32_scmi_rd *rd = &res->rd[j]; 996 struct rstctrl *rstctrl = NULL; 997 998 if (!rd->name || 999 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 1000 panic("SCMI reset domain name invalid"); 1001 1002 if (stm32mp_nsec_can_access_clock(rd->reset_id)) 1003 continue; 1004 1005 rstctrl = stm32mp_rcc_reset_id_to_rstctrl(rd->reset_id); 1006 assert(rstctrl); 1007 if (rstctrl_get_exclusive(rstctrl)) 1008 continue; 1009 1010 rd->rstctrl = rstctrl; 1011 } 1012 1013 for (j = 0; j < res->voltd_count; j++) { 1014 struct stm32_scmi_voltd *voltd = &res->voltd[j]; 1015 1016 if (!voltd->name || 1017 strlen(voltd->name) >= SCMI_VOLTD_NAME_SIZE) 1018 panic("SCMI voltage domain name invalid"); 1019 } 1020 } 1021 1022 return TEE_SUCCESS; 1023 } 1024 1025 driver_init_late(stm32mp1_init_scmi_server); 1026