1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019-2022, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <confine_array_index.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/rstctrl.h> 11 #include <drivers/scmi-msg.h> 12 #include <drivers/scmi.h> 13 #include <drivers/stm32mp1_pmic.h> 14 #include <drivers/stm32mp1_pwr.h> 15 #include <drivers/stpmic1.h> 16 #include <drivers/stpmic1_regulator.h> 17 #include <drivers/stm32mp_dt_bindings.h> 18 #include <initcall.h> 19 #include <mm/core_memprot.h> 20 #include <mm/core_mmu.h> 21 #include <platform_config.h> 22 #include <stdint.h> 23 #include <speculation_barrier.h> 24 #include <stm32_util.h> 25 #include <string.h> 26 #include <tee_api_defines.h> 27 #include <util.h> 28 29 #define TIMEOUT_US_1MS 1000 30 31 #define SCMI_CLOCK_NAME_SIZE 16 32 #define SCMI_RD_NAME_SIZE 16 33 #define SCMI_VOLTD_NAME_SIZE 16 34 35 /* 36 * struct stm32_scmi_clk - Data for the exposed clock 37 * @clock_id: Clock identifier in RCC clock driver 38 * @name: Clock string ID exposed to channel 39 * @enabled: State of the SCMI clock 40 */ 41 struct stm32_scmi_clk { 42 unsigned long clock_id; 43 struct clk *clk; 44 const char *name; 45 bool enabled; 46 }; 47 48 /* 49 * struct stm32_scmi_rd - Data for the exposed reset controller 50 * @reset_id: Reset identifier in RCC reset driver 51 * @name: Reset string ID exposed to channel 52 * @rstctrl: Reset controller device 53 */ 54 struct stm32_scmi_rd { 55 unsigned long reset_id; 56 const char *name; 57 struct rstctrl *rstctrl; 58 }; 59 60 enum voltd_device { 61 VOLTD_PWR, 62 VOLTD_PMIC, 63 }; 64 65 /* 66 * struct stm32_scmi_voltd - Data for the exposed voltage domains 67 * @name: Power regulator string ID exposed to channel 68 * @priv_id: Internal string ID for the regulator 69 * @priv_dev: Internal ID for the device implementing the regulator 70 */ 71 struct stm32_scmi_voltd { 72 const char *name; 73 const char *priv_id; 74 enum voltd_device priv_dev; 75 76 }; 77 78 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 79 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 80 81 #if (SMT_BUFFER_BASE + SMT_BUF_SLOT_SIZE > \ 82 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 83 #error "SCMI shared memory mismatch" 84 #endif 85 86 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 87 CFG_STM32MP1_SCMI_SHM_SIZE); 88 89 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 90 [(_scmi_id)] = { \ 91 .clock_id = (_id), \ 92 .name = (_name), \ 93 .enabled = (_init_enabled), \ 94 } 95 96 #define RESET_CELL(_scmi_id, _id, _name) \ 97 [(_scmi_id)] = { \ 98 .reset_id = (_id), \ 99 .name = (_name), \ 100 } 101 102 #define VOLTD_CELL(_scmi_id, _dev_id, _priv_id, _name) \ 103 [(_scmi_id)] = { \ 104 .priv_id = (_priv_id), \ 105 .priv_dev = (_dev_id), \ 106 .name = (_name), \ 107 } 108 109 #ifdef CFG_STM32MP13 110 static struct stm32_scmi_clk stm32_scmi_clock[] = { 111 CLOCK_CELL(CK_SCMI_HSE, CK_HSE, "ck_hse", true), 112 CLOCK_CELL(CK_SCMI_HSI, CK_HSI, "ck_hsi", true), 113 CLOCK_CELL(CK_SCMI_CSI, CK_CSI, "ck_csi", true), 114 CLOCK_CELL(CK_SCMI_LSE, CK_LSE, "ck_lse", true), 115 CLOCK_CELL(CK_SCMI_LSI, CK_LSI, "ck_lsi", true), 116 CLOCK_CELL(CK_SCMI_HSE_DIV2, CK_HSE_DIV2, "clk-hse-div2", true), 117 CLOCK_CELL(CK_SCMI_PLL2_Q, PLL2_Q, "pll2_q", true), 118 CLOCK_CELL(CK_SCMI_PLL2_R, PLL2_R, "pll2_r", true), 119 CLOCK_CELL(CK_SCMI_PLL3_P, PLL3_P, "pll3_p", true), 120 CLOCK_CELL(CK_SCMI_PLL3_Q, PLL3_Q, "pll3_q", true), 121 CLOCK_CELL(CK_SCMI_PLL3_R, PLL3_R, "pll3_r", true), 122 CLOCK_CELL(CK_SCMI_PLL4_P, PLL4_P, "pll4_p", true), 123 CLOCK_CELL(CK_SCMI_PLL4_Q, PLL4_Q, "pll4_q", true), 124 CLOCK_CELL(CK_SCMI_PLL4_R, PLL4_R, "pll4_r", true), 125 CLOCK_CELL(CK_SCMI_MPU, CK_MPU, "ck_mpu", true), 126 CLOCK_CELL(CK_SCMI_AXI, CK_AXI, "ck_axi", true), 127 CLOCK_CELL(CK_SCMI_MLAHB, CK_MLAHB, "ck_mlahb", true), 128 CLOCK_CELL(CK_SCMI_CKPER, CK_PER, "ck_per", true), 129 CLOCK_CELL(CK_SCMI_PCLK1, PCLK1, "pclk1", true), 130 CLOCK_CELL(CK_SCMI_PCLK2, PCLK2, "pclk2", true), 131 CLOCK_CELL(CK_SCMI_PCLK3, PCLK3, "pclk3", true), 132 CLOCK_CELL(CK_SCMI_PCLK4, PCLK4, "pclk4", true), 133 CLOCK_CELL(CK_SCMI_PCLK5, PCLK5, "pclk5", true), 134 CLOCK_CELL(CK_SCMI_PCLK6, PCLK6, "pclk6", true), 135 CLOCK_CELL(CK_SCMI_CKTIMG1, CK_TIMG1, "timg1_ck", true), 136 CLOCK_CELL(CK_SCMI_CKTIMG2, CK_TIMG2, "timg2_ck", true), 137 CLOCK_CELL(CK_SCMI_CKTIMG3, CK_TIMG3, "timg3_ck", true), 138 CLOCK_CELL(CK_SCMI_RTC, RTC, "ck_rtc", true), 139 CLOCK_CELL(CK_SCMI_RTCAPB, RTCAPB, "rtcapb", true), 140 CLOCK_CELL(CK_SCMI_BSEC, BSEC, "bsec", true), 141 }; 142 #endif 143 144 #ifdef CFG_STM32MP15 145 static struct stm32_scmi_clk stm32_scmi_clock[] = { 146 CLOCK_CELL(CK_SCMI_HSE, CK_HSE, "ck_hse", true), 147 CLOCK_CELL(CK_SCMI_HSI, CK_HSI, "ck_hsi", true), 148 CLOCK_CELL(CK_SCMI_CSI, CK_CSI, "ck_csi", true), 149 CLOCK_CELL(CK_SCMI_LSE, CK_LSE, "ck_lse", true), 150 CLOCK_CELL(CK_SCMI_LSI, CK_LSI, "ck_lsi", true), 151 CLOCK_CELL(CK_SCMI_PLL2_Q, PLL2_Q, "pll2_q", true), 152 CLOCK_CELL(CK_SCMI_PLL2_R, PLL2_R, "pll2_r", true), 153 CLOCK_CELL(CK_SCMI_MPU, CK_MPU, "ck_mpu", true), 154 CLOCK_CELL(CK_SCMI_AXI, CK_AXI, "ck_axi", true), 155 CLOCK_CELL(CK_SCMI_BSEC, BSEC, "bsec", true), 156 CLOCK_CELL(CK_SCMI_CRYP1, CRYP1, "cryp1", false), 157 CLOCK_CELL(CK_SCMI_GPIOZ, GPIOZ, "gpioz", false), 158 CLOCK_CELL(CK_SCMI_HASH1, HASH1, "hash1", false), 159 CLOCK_CELL(CK_SCMI_I2C4, I2C4_K, "i2c4_k", false), 160 CLOCK_CELL(CK_SCMI_I2C6, I2C6_K, "i2c6_k", false), 161 CLOCK_CELL(CK_SCMI_IWDG1, IWDG1, "iwdg1", false), 162 CLOCK_CELL(CK_SCMI_RNG1, RNG1_K, "rng1_k", true), 163 CLOCK_CELL(CK_SCMI_RTC, RTC, "ck_rtc", true), 164 CLOCK_CELL(CK_SCMI_RTCAPB, RTCAPB, "rtcapb", true), 165 CLOCK_CELL(CK_SCMI_SPI6, SPI6_K, "spi6_k", false), 166 CLOCK_CELL(CK_SCMI_USART1, USART1_K, "usart1_k", false), 167 }; 168 #endif 169 170 #ifdef CFG_STM32MP13 171 static struct stm32_scmi_rd stm32_scmi_reset_domain[] = { 172 RESET_CELL(RST_SCMI_LTDC, LTDC_R, "ltdc"), 173 RESET_CELL(RST_SCMI_MDMA, MDMA_R, "mdma"), 174 }; 175 #endif 176 177 #ifdef CFG_STM32MP15 178 static struct stm32_scmi_rd stm32_scmi_reset_domain[] = { 179 RESET_CELL(RST_SCMI_SPI6, SPI6_R, "spi6"), 180 RESET_CELL(RST_SCMI_I2C4, I2C4_R, "i2c4"), 181 RESET_CELL(RST_SCMI_I2C6, I2C6_R, "i2c6"), 182 RESET_CELL(RST_SCMI_USART1, USART1_R, "usart1"), 183 RESET_CELL(RST_SCMI_STGEN, STGEN_R, "stgen"), 184 RESET_CELL(RST_SCMI_GPIOZ, GPIOZ_R, "gpioz"), 185 RESET_CELL(RST_SCMI_CRYP1, CRYP1_R, "cryp1"), 186 RESET_CELL(RST_SCMI_HASH1, HASH1_R, "hash1"), 187 RESET_CELL(RST_SCMI_RNG1, RNG1_R, "rng1"), 188 RESET_CELL(RST_SCMI_MDMA, MDMA_R, "mdma"), 189 RESET_CELL(RST_SCMI_MCU, MCU_R, "mcu"), 190 RESET_CELL(RST_SCMI_MCU_HOLD_BOOT, MCU_HOLD_BOOT_R, "mcu_hold_boot"), 191 }; 192 #endif 193 194 #define PWR_REG11_NAME_ID "0" 195 #define PWR_REG18_NAME_ID "1" 196 #define PWR_USB33_NAME_ID "2" 197 #define PWR_SDMMC1_IO_NAME_ID "3" 198 #define PWR_SDMMC2_IO_NAME_ID "4" 199 #define PWR_VREFBUF_NAME_ID "5" 200 201 #ifdef CFG_STM32MP13 202 struct stm32_scmi_voltd scmi_voltage_domain[] = { 203 VOLTD_CELL(VOLTD_SCMI_REG11, VOLTD_PWR, PWR_REG11_NAME_ID, "reg11"), 204 VOLTD_CELL(VOLTD_SCMI_REG18, VOLTD_PWR, PWR_REG18_NAME_ID, "reg18"), 205 VOLTD_CELL(VOLTD_SCMI_USB33, VOLTD_PWR, PWR_USB33_NAME_ID, "usb33"), 206 VOLTD_CELL(VOLTD_SCMI_SDMMC1_IO, VOLTD_PWR, PWR_SDMMC1_IO_NAME_ID, 207 "sdmmc1"), 208 VOLTD_CELL(VOLTD_SCMI_SDMMC2_IO, VOLTD_PWR, PWR_SDMMC2_IO_NAME_ID, 209 "sdmmc2"), 210 VOLTD_CELL(VOLTD_SCMI_VREFBUF, VOLTD_PWR, PWR_VREFBUF_NAME_ID, 211 "vrefbuf"), 212 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK1, VOLTD_PMIC, "buck1", "buck1"), 213 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK2, VOLTD_PMIC, "buck2", "buck2"), 214 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK3, VOLTD_PMIC, "buck3", "buck3"), 215 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK4, VOLTD_PMIC, "buck4", "buck4"), 216 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO1, VOLTD_PMIC, "ldo1", "ldo1"), 217 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO2, VOLTD_PMIC, "ldo2", "ldo2"), 218 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO3, VOLTD_PMIC, "ldo3", "ldo3"), 219 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO4, VOLTD_PMIC, "ldo4", "ldo4"), 220 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO5, VOLTD_PMIC, "ldo5", "ldo5"), 221 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO6, VOLTD_PMIC, "ldo6", "ldo6"), 222 VOLTD_CELL(VOLTD_SCMI_STPMIC1_VREFDDR, VOLTD_PMIC, "vref_ddr", 223 "vref_ddr"), 224 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BOOST, VOLTD_PMIC, "boost", "bst_out"), 225 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW1, VOLTD_PMIC, "pwr_sw1", 226 "pwr_sw1"), 227 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW2, VOLTD_PMIC, "pwr_sw2", 228 "pwr_sw2"), 229 }; 230 #endif 231 232 #ifdef CFG_STM32MP15 233 struct stm32_scmi_voltd scmi_voltage_domain[] = { 234 VOLTD_CELL(VOLTD_SCMI_REG11, VOLTD_PWR, PWR_REG11_NAME_ID, "reg11"), 235 VOLTD_CELL(VOLTD_SCMI_REG18, VOLTD_PWR, PWR_REG18_NAME_ID, "reg18"), 236 VOLTD_CELL(VOLTD_SCMI_USB33, VOLTD_PWR, PWR_USB33_NAME_ID, "usb33"), 237 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK1, VOLTD_PMIC, "buck1", "vddcore"), 238 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK2, VOLTD_PMIC, "buck2", "vdd_ddr"), 239 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK3, VOLTD_PMIC, "buck3", "vdd"), 240 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BUCK4, VOLTD_PMIC, "buck4", "v3v3"), 241 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO1, VOLTD_PMIC, "ldo1", "v1v8_audio"), 242 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO2, VOLTD_PMIC, "ldo2", "v3v3_hdmi"), 243 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO3, VOLTD_PMIC, "ldo3", "vtt_ddr"), 244 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO4, VOLTD_PMIC, "ldo4", "vdd_usb"), 245 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO5, VOLTD_PMIC, "ldo5", "vdda"), 246 VOLTD_CELL(VOLTD_SCMI_STPMIC1_LDO6, VOLTD_PMIC, "ldo6", "v1v2_hdmi"), 247 VOLTD_CELL(VOLTD_SCMI_STPMIC1_VREFDDR, VOLTD_PMIC, "vref_ddr", 248 "vref_ddr"), 249 VOLTD_CELL(VOLTD_SCMI_STPMIC1_BOOST, VOLTD_PMIC, "boost", "bst_out"), 250 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW1, VOLTD_PMIC, "pwr_sw1", 251 "vbus_otg"), 252 VOLTD_CELL(VOLTD_SCMI_STPMIC1_PWR_SW2, VOLTD_PMIC, "pwr_sw2", 253 "vbus_sw"), 254 }; 255 #endif 256 257 struct channel_resources { 258 struct scmi_msg_channel *channel; 259 struct stm32_scmi_clk *clock; 260 size_t clock_count; 261 struct stm32_scmi_rd *rd; 262 size_t rd_count; 263 struct stm32_scmi_voltd *voltd; 264 size_t voltd_count; 265 }; 266 267 static const struct channel_resources scmi_channel[] = { 268 [0] = { 269 .channel = &(struct scmi_msg_channel){ 270 .shm_addr = { .pa = SMT_BUFFER_BASE }, 271 .shm_size = SMT_BUF_SLOT_SIZE, 272 }, 273 .clock = stm32_scmi_clock, 274 .clock_count = ARRAY_SIZE(stm32_scmi_clock), 275 .rd = stm32_scmi_reset_domain, 276 .rd_count = ARRAY_SIZE(stm32_scmi_reset_domain), 277 .voltd = scmi_voltage_domain, 278 .voltd_count = ARRAY_SIZE(scmi_voltage_domain), 279 }, 280 }; 281 282 static const struct channel_resources *find_resource(unsigned int channel_id) 283 { 284 assert(channel_id < ARRAY_SIZE(scmi_channel)); 285 286 return scmi_channel + channel_id; 287 } 288 289 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int channel_id) 290 { 291 const size_t max_id = ARRAY_SIZE(scmi_channel); 292 unsigned int confined_id = confine_array_index(channel_id, max_id); 293 294 if (channel_id >= max_id) 295 return NULL; 296 297 return find_resource(confined_id)->channel; 298 } 299 300 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 301 { 302 unsigned int n = 0; 303 unsigned int count = 0; 304 const size_t channel_count = ARRAY_SIZE(scmi_channel); 305 306 for (n = 0; n < channel_count; n++) 307 if (scmi_channel[n].clock_count) 308 break; 309 if (n < channel_count) 310 count++; 311 312 for (n = 0; n < channel_count; n++) 313 if (scmi_channel[n].rd_count) 314 break; 315 if (n < channel_count) 316 count++; 317 318 for (n = 0; n < channel_count; n++) 319 if (scmi_channel[n].voltd_count) 320 break; 321 if (n < channel_count) 322 count++; 323 324 return count; 325 } 326 327 static const char vendor[] = "ST"; 328 static const char sub_vendor[] = ""; 329 330 const char *plat_scmi_vendor_name(void) 331 { 332 return vendor; 333 } 334 335 const char *plat_scmi_sub_vendor_name(void) 336 { 337 return sub_vendor; 338 } 339 340 /* Currently supporting Clocks and Reset Domains */ 341 static const uint8_t plat_protocol_list[] = { 342 SCMI_PROTOCOL_ID_CLOCK, 343 SCMI_PROTOCOL_ID_RESET_DOMAIN, 344 SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, 345 0 /* Null termination */ 346 }; 347 348 size_t plat_scmi_protocol_count(void) 349 { 350 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 351 352 assert(count == plat_scmi_protocol_count_paranoid()); 353 354 return count; 355 } 356 357 const uint8_t *plat_scmi_protocol_list(unsigned int channel_id __unused) 358 { 359 assert(plat_scmi_protocol_count_paranoid() == 360 (ARRAY_SIZE(plat_protocol_list) - 1)); 361 362 return plat_protocol_list; 363 } 364 365 /* 366 * Platform SCMI clocks 367 */ 368 static struct stm32_scmi_clk *find_clock(unsigned int channel_id, 369 unsigned int scmi_id) 370 { 371 const struct channel_resources *resource = find_resource(channel_id); 372 size_t n = 0; 373 374 if (resource) { 375 for (n = 0; n < resource->clock_count; n++) 376 if (n == scmi_id) 377 return &resource->clock[n]; 378 } 379 380 return NULL; 381 } 382 383 size_t plat_scmi_clock_count(unsigned int channel_id) 384 { 385 const struct channel_resources *resource = find_resource(channel_id); 386 387 if (!resource) 388 return 0; 389 390 return resource->clock_count; 391 } 392 393 const char *plat_scmi_clock_get_name(unsigned int channel_id, 394 unsigned int scmi_id) 395 { 396 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 397 398 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 399 return NULL; 400 401 return clock->name; 402 } 403 404 int32_t plat_scmi_clock_rates_array(unsigned int channel_id, 405 unsigned int scmi_id, size_t start_index, 406 unsigned long *array, size_t *nb_elts) 407 { 408 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 409 410 if (!clock) 411 return SCMI_NOT_FOUND; 412 413 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 414 return SCMI_DENIED; 415 416 /* Exposed clocks are currently fixed rate clocks */ 417 if (start_index) 418 return SCMI_INVALID_PARAMETERS; 419 420 if (!array) 421 *nb_elts = 1; 422 else if (*nb_elts == 1) 423 *array = clk_get_rate(clock->clk); 424 else 425 return SCMI_GENERIC_ERROR; 426 427 return SCMI_SUCCESS; 428 } 429 430 unsigned long plat_scmi_clock_get_rate(unsigned int channel_id, 431 unsigned int scmi_id) 432 { 433 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 434 435 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 436 return 0; 437 438 return clk_get_rate(clock->clk); 439 } 440 441 int32_t plat_scmi_clock_get_state(unsigned int channel_id, unsigned int scmi_id) 442 { 443 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 444 445 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 446 return 0; 447 448 return (int32_t)clock->enabled; 449 } 450 451 int32_t plat_scmi_clock_set_state(unsigned int channel_id, unsigned int scmi_id, 452 bool enable_not_disable) 453 { 454 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); 455 456 if (!clock) 457 return SCMI_NOT_FOUND; 458 459 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 460 return SCMI_DENIED; 461 462 if (enable_not_disable) { 463 if (!clock->enabled) { 464 DMSG("SCMI clock %u enable", scmi_id); 465 clk_enable(clock->clk); 466 clock->enabled = true; 467 } 468 } else { 469 if (clock->enabled) { 470 DMSG("SCMI clock %u disable", scmi_id); 471 clk_disable(clock->clk); 472 clock->enabled = false; 473 } 474 } 475 476 return SCMI_SUCCESS; 477 } 478 479 /* 480 * Platform SCMI reset domains 481 */ 482 static struct stm32_scmi_rd *find_rd(unsigned int channel_id, 483 unsigned int scmi_id) 484 { 485 const struct channel_resources *resource = find_resource(channel_id); 486 size_t n = 0; 487 488 if (resource) { 489 for (n = 0; n < resource->rd_count; n++) 490 if (n == scmi_id) 491 return &resource->rd[n]; 492 } 493 494 return NULL; 495 } 496 497 const char *plat_scmi_rd_get_name(unsigned int channel_id, unsigned int scmi_id) 498 { 499 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 500 501 if (!rd) 502 return NULL; 503 504 return rd->name; 505 } 506 507 size_t plat_scmi_rd_count(unsigned int channel_id) 508 { 509 const struct channel_resources *resource = find_resource(channel_id); 510 511 if (!resource) 512 return 0; 513 514 return resource->rd_count; 515 } 516 517 int32_t plat_scmi_rd_autonomous(unsigned int channel_id, unsigned int scmi_id, 518 uint32_t state) 519 { 520 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 521 522 if (!rd) 523 return SCMI_NOT_FOUND; 524 525 if (!rd->rstctrl || !stm32mp_nsec_can_access_reset(rd->reset_id)) 526 return SCMI_DENIED; 527 assert(rd->rstctrl); 528 529 #ifdef CFG_STM32MP15 530 if (rd->reset_id == MCU_HOLD_BOOT_R) 531 return SCMI_NOT_SUPPORTED; 532 #endif 533 534 /* Supports only reset with context loss */ 535 if (state) 536 return SCMI_NOT_SUPPORTED; 537 538 DMSG("SCMI reset %u cycle", scmi_id); 539 540 if (rstctrl_assert_to(rd->rstctrl, TIMEOUT_US_1MS)) 541 return SCMI_HARDWARE_ERROR; 542 543 if (rstctrl_deassert_to(rd->rstctrl, TIMEOUT_US_1MS)) 544 return SCMI_HARDWARE_ERROR; 545 546 return SCMI_SUCCESS; 547 } 548 549 int32_t plat_scmi_rd_set_state(unsigned int channel_id, unsigned int scmi_id, 550 bool assert_not_deassert) 551 { 552 const struct stm32_scmi_rd *rd = find_rd(channel_id, scmi_id); 553 TEE_Result res = TEE_ERROR_GENERIC; 554 555 if (!rd) 556 return SCMI_NOT_FOUND; 557 558 if (!rd->rstctrl || !stm32mp_nsec_can_access_reset(rd->reset_id)) 559 return SCMI_DENIED; 560 assert(rd->rstctrl); 561 562 if (assert_not_deassert) { 563 DMSG("SCMI reset %u set", scmi_id); 564 res = rstctrl_assert(rd->rstctrl); 565 } else { 566 DMSG("SCMI reset %u release", scmi_id); 567 res = rstctrl_deassert(rd->rstctrl); 568 } 569 570 if (res) 571 return SCMI_HARDWARE_ERROR; 572 573 return SCMI_SUCCESS; 574 } 575 576 /* 577 * Platform SCMI voltage domains 578 */ 579 static struct stm32_scmi_voltd *find_voltd(unsigned int channel_id, 580 unsigned int scmi_id) 581 { 582 const struct channel_resources *resource = find_resource(channel_id); 583 size_t n = 0; 584 585 if (resource) { 586 for (n = 0; n < resource->voltd_count; n++) 587 if (n == scmi_id) 588 return &resource->voltd[n]; 589 } 590 591 return NULL; 592 } 593 594 size_t plat_scmi_voltd_count(unsigned int channel_id) 595 { 596 const struct channel_resources *resource = find_resource(channel_id); 597 598 if (!resource) 599 return 0; 600 601 return resource->voltd_count; 602 } 603 604 const char *plat_scmi_voltd_get_name(unsigned int channel_id, 605 unsigned int scmi_id) 606 { 607 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 608 609 /* Currently non-secure is allowed to access all PWR regulators */ 610 if (!voltd) 611 return NULL; 612 613 return voltd->name; 614 } 615 616 static enum pwr_regulator pwr_scmi_to_regu_id(struct stm32_scmi_voltd *voltd) 617 { 618 if (!strcmp(voltd->priv_id, PWR_REG11_NAME_ID)) 619 return PWR_REG11; 620 if (!strcmp(voltd->priv_id, PWR_REG18_NAME_ID)) 621 return PWR_REG18; 622 if (!strcmp(voltd->priv_id, PWR_USB33_NAME_ID)) 623 return PWR_USB33; 624 625 panic(); 626 } 627 628 static long pwr_get_level(struct stm32_scmi_voltd *voltd) 629 { 630 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 631 632 return (long)stm32mp1_pwr_regulator_mv(regu_id) * 1000; 633 } 634 635 static int32_t pwr_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 636 { 637 if (level_uv != pwr_get_level(voltd)) 638 return SCMI_INVALID_PARAMETERS; 639 640 return SCMI_SUCCESS; 641 } 642 643 static int32_t pwr_describe_levels(struct stm32_scmi_voltd *voltd, 644 size_t start_index, long *microvolt, 645 size_t *nb_elts) 646 { 647 if (start_index) 648 return SCMI_INVALID_PARAMETERS; 649 650 if (!microvolt) { 651 *nb_elts = 1; 652 return SCMI_SUCCESS; 653 } 654 655 if (*nb_elts < 1) 656 return SCMI_GENERIC_ERROR; 657 658 *nb_elts = 1; 659 *microvolt = pwr_get_level(voltd); 660 661 return SCMI_SUCCESS; 662 } 663 664 static uint32_t pwr_get_state(struct stm32_scmi_voltd *voltd) 665 { 666 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 667 668 if (stm32mp1_pwr_regulator_is_enabled(regu_id)) 669 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 670 671 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 672 } 673 674 static void pwr_set_state(struct stm32_scmi_voltd *voltd, bool enable) 675 { 676 enum pwr_regulator regu_id = pwr_scmi_to_regu_id(voltd); 677 678 DMSG("%sable PWR %s (was %s)", enable ? "En" : "Dis", voltd->name, 679 stm32mp1_pwr_regulator_is_enabled(regu_id) ? "on" : "off"); 680 681 stm32mp1_pwr_regulator_set_state(regu_id, enable); 682 } 683 684 static int32_t pmic_describe_levels(struct stm32_scmi_voltd *voltd, 685 size_t start_index, long *microvolt, 686 size_t *nb_elts) 687 { 688 const uint16_t *levels = NULL; 689 size_t full_count = 0; 690 size_t out_count = 0; 691 size_t i = 0; 692 693 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 694 return SCMI_DENIED; 695 696 stpmic1_regulator_levels_mv(voltd->priv_id, &levels, &full_count); 697 698 if (!microvolt) { 699 *nb_elts = full_count - start_index; 700 return SCMI_SUCCESS; 701 } 702 703 if (SUB_OVERFLOW(full_count, start_index, &out_count)) 704 return SCMI_GENERIC_ERROR; 705 706 out_count = MIN(out_count, *nb_elts); 707 708 FMSG("%zu levels: start %zu requested %zu output %zu", 709 full_count, start_index, *nb_elts, out_count); 710 711 for (i = 0; i < out_count; i++) 712 microvolt[i] = levels[start_index + i] * 1000; 713 714 *nb_elts = out_count; 715 716 return SCMI_SUCCESS; 717 } 718 719 static long pmic_get_level(struct stm32_scmi_voltd *voltd) 720 { 721 unsigned long level_mv = 0; 722 723 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 724 return 0; 725 726 stm32mp_get_pmic(); 727 level_mv = stpmic1_regulator_voltage_get(voltd->priv_id); 728 stm32mp_put_pmic(); 729 730 return (long)level_mv * 1000; 731 } 732 733 static int32_t pmic_set_level(struct stm32_scmi_voltd *voltd, long level_uv) 734 { 735 int rc = 0; 736 unsigned int level_mv = 0; 737 738 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 739 return SCMI_DENIED; 740 741 if (level_uv < 0 || level_uv > (UINT16_MAX * 1000)) 742 return SCMI_INVALID_PARAMETERS; 743 744 level_mv = (unsigned int)level_uv / 1000; 745 746 DMSG("Set STPMIC1 regulator %s level to %dmV", voltd->name, level_mv); 747 748 stm32mp_get_pmic(); 749 rc = stpmic1_regulator_voltage_set(voltd->priv_id, level_mv); 750 stm32mp_put_pmic(); 751 752 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 753 } 754 755 static uint32_t pmic_get_state(struct stm32_scmi_voltd *voltd) 756 { 757 bool enabled = false; 758 759 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 760 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 761 762 stm32mp_get_pmic(); 763 enabled = stpmic1_is_regulator_enabled(voltd->priv_id); 764 stm32mp_put_pmic(); 765 766 if (enabled) 767 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON; 768 769 return SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF; 770 } 771 772 static int32_t pmic_set_state(struct stm32_scmi_voltd *voltd, bool enable) 773 { 774 int rc = 0; 775 776 if (!stm32mp_nsec_can_access_pmic_regu(voltd->priv_id)) 777 return SCMI_DENIED; 778 779 stm32mp_get_pmic(); 780 781 DMSG("%sable STPMIC1 %s (was %s)", enable ? "En" : "Dis", voltd->name, 782 stpmic1_is_regulator_enabled(voltd->priv_id) ? "on" : "off"); 783 784 if (enable) 785 rc = stpmic1_regulator_enable(voltd->priv_id); 786 else 787 rc = stpmic1_regulator_disable(voltd->priv_id); 788 789 stm32mp_put_pmic(); 790 791 return rc ? SCMI_GENERIC_ERROR : SCMI_SUCCESS; 792 } 793 794 int32_t plat_scmi_voltd_levels_array(unsigned int channel_id, 795 unsigned int scmi_id, size_t start_index, 796 long *levels, size_t *nb_elts) 797 798 { 799 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 800 801 if (!voltd) 802 return SCMI_NOT_FOUND; 803 804 switch (voltd->priv_dev) { 805 case VOLTD_PWR: 806 return pwr_describe_levels(voltd, start_index, levels, nb_elts); 807 case VOLTD_PMIC: 808 return pmic_describe_levels(voltd, start_index, levels, 809 nb_elts); 810 default: 811 return SCMI_GENERIC_ERROR; 812 } 813 } 814 815 long plat_scmi_voltd_get_level(unsigned int channel_id, unsigned int scmi_id) 816 { 817 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 818 819 if (!voltd) 820 return 0; 821 822 switch (voltd->priv_dev) { 823 case VOLTD_PWR: 824 return pwr_get_level(voltd); 825 case VOLTD_PMIC: 826 return pmic_get_level(voltd); 827 default: 828 panic(); 829 } 830 } 831 832 int32_t plat_scmi_voltd_set_level(unsigned int channel_id, unsigned int scmi_id, 833 long level) 834 { 835 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 836 837 if (!voltd) 838 return SCMI_NOT_FOUND; 839 840 switch (voltd->priv_dev) { 841 case VOLTD_PWR: 842 return pwr_set_level(voltd, level); 843 case VOLTD_PMIC: 844 return pmic_set_level(voltd, level); 845 default: 846 return SCMI_GENERIC_ERROR; 847 } 848 } 849 850 int32_t plat_scmi_voltd_get_config(unsigned int channel_id, 851 unsigned int scmi_id, uint32_t *config) 852 { 853 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 854 855 if (!voltd) 856 return SCMI_NOT_FOUND; 857 858 switch (voltd->priv_dev) { 859 case VOLTD_PWR: 860 *config = pwr_get_state(voltd); 861 break; 862 case VOLTD_PMIC: 863 *config = pmic_get_state(voltd); 864 break; 865 default: 866 return SCMI_GENERIC_ERROR; 867 } 868 869 return SCMI_SUCCESS; 870 } 871 872 int32_t plat_scmi_voltd_set_config(unsigned int channel_id, 873 unsigned int scmi_id, uint32_t config) 874 { 875 struct stm32_scmi_voltd *voltd = find_voltd(channel_id, scmi_id); 876 int32_t rc = SCMI_SUCCESS; 877 878 if (!voltd) 879 return SCMI_NOT_FOUND; 880 881 switch (voltd->priv_dev) { 882 case VOLTD_PWR: 883 pwr_set_state(voltd, config); 884 break; 885 case VOLTD_PMIC: 886 rc = pmic_set_state(voltd, config); 887 break; 888 default: 889 return SCMI_GENERIC_ERROR; 890 } 891 892 return rc; 893 } 894 895 /* 896 * Initialize platform SCMI resources 897 */ 898 static TEE_Result stm32mp1_init_scmi_server(void) 899 { 900 size_t i = 0; 901 size_t j = 0; 902 903 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 904 const struct channel_resources *res = scmi_channel + i; 905 struct scmi_msg_channel *chan = res->channel; 906 907 /* Enforce non-secure shm mapped as device memory */ 908 chan->shm_addr.va = (vaddr_t)phys_to_virt(chan->shm_addr.pa, 909 MEM_AREA_IO_NSEC, 1); 910 assert(chan->shm_addr.va); 911 912 scmi_smt_init_agent_channel(chan); 913 914 for (j = 0; j < res->clock_count; j++) { 915 struct stm32_scmi_clk *clk = &res->clock[j]; 916 917 if (!clk->name || 918 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 919 panic("SCMI clock name invalid"); 920 921 clk->clk = stm32mp_rcc_clock_id_to_clk(clk->clock_id); 922 assert(clk->clk); 923 924 /* Sync SCMI clocks with their targeted initial state */ 925 if (clk->enabled && 926 stm32mp_nsec_can_access_clock(clk->clock_id)) 927 clk_enable(clk->clk); 928 } 929 930 for (j = 0; j < res->rd_count; j++) { 931 struct stm32_scmi_rd *rd = &res->rd[j]; 932 struct rstctrl *rstctrl = NULL; 933 934 if (!rd->name || 935 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 936 panic("SCMI reset domain name invalid"); 937 938 if (stm32mp_nsec_can_access_clock(rd->reset_id)) 939 continue; 940 941 rstctrl = stm32mp_rcc_reset_id_to_rstctrl(rd->reset_id); 942 assert(rstctrl); 943 if (rstctrl_get_exclusive(rstctrl)) 944 continue; 945 946 rd->rstctrl = rstctrl; 947 } 948 949 for (j = 0; j < res->voltd_count; j++) { 950 struct stm32_scmi_voltd *voltd = &res->voltd[j]; 951 952 if (!voltd->name || 953 strlen(voltd->name) >= SCMI_VOLTD_NAME_SIZE) 954 panic("SCMI voltage domain name invalid"); 955 } 956 } 957 958 return TEE_SUCCESS; 959 } 960 961 driver_init_late(stm32mp1_init_scmi_server); 962