1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <drivers/scmi-msg.h> 8 #include <drivers/scmi.h> 9 #include <dt-bindings/clock/stm32mp1-clks.h> 10 #include <dt-bindings/reset/stm32mp1-resets.h> 11 #include <initcall.h> 12 #include <mm/core_memprot.h> 13 #include <mm/core_mmu.h> 14 #include <platform_config.h> 15 #include <stdint.h> 16 #include <speculation_barrier.h> 17 #include <stm32_util.h> 18 #include <string.h> 19 #include <tee_api_defines.h> 20 #include <util.h> 21 22 #define TIMEOUT_US_1MS 1000 23 24 #define SCMI_CLOCK_NAME_SIZE 16 25 #define SCMI_RD_NAME_SIZE 16 26 27 /* 28 * struct stm32_scmi_clk - Data for the exposed clock 29 * @clock_id: Clock identifier in RCC clock driver 30 * @name: Clock string ID exposed to agent 31 * @enabled: State of the SCMI clock 32 */ 33 struct stm32_scmi_clk { 34 unsigned long clock_id; 35 const char *name; 36 bool enabled; 37 }; 38 39 /* 40 * struct stm32_scmi_rd - Data for the exposed reset controller 41 * @reset_id: Reset identifier in RCC reset driver 42 * @name: Reset string ID exposed to agent 43 */ 44 struct stm32_scmi_rd { 45 unsigned long reset_id; 46 const char *name; 47 }; 48 49 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 50 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 51 #define SMT_BUFFER0_BASE SMT_BUFFER_BASE 52 #define SMT_BUFFER1_BASE (SMT_BUFFER_BASE + 0x200) 53 54 #if (SMT_BUFFER1_BASE + SMT_BUF_SLOT_SIZE > \ 55 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 56 #error "SCMI shared memory mismatch" 57 #endif 58 59 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 60 CFG_STM32MP1_SCMI_SHM_SIZE); 61 62 static struct scmi_msg_channel scmi_channel[] = { 63 [0] = { 64 .agent_name = "stm32mp1-agent-0", 65 .shm_addr = { .pa = SMT_BUFFER0_BASE, }, 66 .shm_size = SMT_BUF_SLOT_SIZE, 67 }, 68 [1] = { 69 .agent_name = "stm32mp1-agent-1", 70 .shm_addr = { .pa = SMT_BUFFER1_BASE, }, 71 .shm_size = SMT_BUF_SLOT_SIZE, 72 }, 73 }; 74 75 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int agent_id) 76 { 77 assert(agent_id < ARRAY_SIZE(scmi_channel)); 78 79 return &scmi_channel[agent_id]; 80 } 81 82 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 83 [_scmi_id] = { \ 84 .clock_id = _id, \ 85 .name = _name, \ 86 .enabled = _init_enabled, \ 87 } 88 89 struct stm32_scmi_clk stm32_scmi0_clock[] = { 90 CLOCK_CELL(CK_SCMI0_HSE, CK_HSE, "ck_hse", true), 91 CLOCK_CELL(CK_SCMI0_HSI, CK_HSI, "ck_hsi", true), 92 CLOCK_CELL(CK_SCMI0_CSI, CK_CSI, "ck_csi", true), 93 CLOCK_CELL(CK_SCMI0_LSE, CK_LSE, "ck_lse", true), 94 CLOCK_CELL(CK_SCMI0_LSI, CK_LSI, "ck_lsi", true), 95 CLOCK_CELL(CK_SCMI0_PLL2_Q, PLL2_Q, "pll2_q", true), 96 CLOCK_CELL(CK_SCMI0_PLL2_R, PLL2_R, "pll2_r", true), 97 CLOCK_CELL(CK_SCMI0_MPU, CK_MPU, "ck_mpu", true), 98 CLOCK_CELL(CK_SCMI0_AXI, CK_AXI, "ck_axi", true), 99 CLOCK_CELL(CK_SCMI0_BSEC, BSEC, "bsec", true), 100 CLOCK_CELL(CK_SCMI0_CRYP1, CRYP1, "cryp1", false), 101 CLOCK_CELL(CK_SCMI0_GPIOZ, GPIOZ, "gpioz", false), 102 CLOCK_CELL(CK_SCMI0_HASH1, HASH1, "hash1", false), 103 CLOCK_CELL(CK_SCMI0_I2C4, I2C4_K, "i2c4_k", false), 104 CLOCK_CELL(CK_SCMI0_I2C6, I2C6_K, "i2c6_k", false), 105 CLOCK_CELL(CK_SCMI0_IWDG1, IWDG1, "iwdg1", false), 106 CLOCK_CELL(CK_SCMI0_RNG1, RNG1_K, "rng1_k", true), 107 CLOCK_CELL(CK_SCMI0_RTC, RTC, "ck_rtc", true), 108 CLOCK_CELL(CK_SCMI0_RTCAPB, RTCAPB, "rtcapb", true), 109 CLOCK_CELL(CK_SCMI0_SPI6, SPI6_K, "spi6_k", false), 110 CLOCK_CELL(CK_SCMI0_USART1, USART1_K, "usart1_k", false), 111 }; 112 113 struct stm32_scmi_clk stm32_scmi1_clock[] = { 114 CLOCK_CELL(CK_SCMI1_PLL3_Q, PLL3_Q, "pll3_q", true), 115 CLOCK_CELL(CK_SCMI1_PLL3_R, PLL3_R, "pll3_r", true), 116 CLOCK_CELL(CK_SCMI1_MCU, CK_MCU, "ck_mcu", false), 117 }; 118 119 #define RESET_CELL(_scmi_id, _id, _name) \ 120 [_scmi_id] = { \ 121 .reset_id = _id, \ 122 .name = _name, \ 123 } 124 125 struct stm32_scmi_rd stm32_scmi0_reset_domain[] = { 126 RESET_CELL(RST_SCMI0_SPI6, SPI6_R, "spi6"), 127 RESET_CELL(RST_SCMI0_I2C4, I2C4_R, "i2c4"), 128 RESET_CELL(RST_SCMI0_I2C6, I2C6_R, "i2c6"), 129 RESET_CELL(RST_SCMI0_USART1, USART1_R, "usart1"), 130 RESET_CELL(RST_SCMI0_STGEN, STGEN_R, "stgen"), 131 RESET_CELL(RST_SCMI0_GPIOZ, GPIOZ_R, "gpioz"), 132 RESET_CELL(RST_SCMI0_CRYP1, CRYP1_R, "cryp1"), 133 RESET_CELL(RST_SCMI0_HASH1, HASH1_R, "hash1"), 134 RESET_CELL(RST_SCMI0_RNG1, RNG1_R, "rng1"), 135 RESET_CELL(RST_SCMI0_MDMA, MDMA_R, "mdma"), 136 RESET_CELL(RST_SCMI0_MCU, MCU_R, "mcu"), 137 }; 138 139 struct scmi_agent_resources { 140 struct stm32_scmi_clk *clock; 141 size_t clock_count; 142 struct stm32_scmi_rd *rd; 143 size_t rd_count; 144 struct stm32_scmi_pd *pd; 145 size_t pd_count; 146 struct stm32_scmi_perfs *perfs; 147 size_t perfs_count; 148 }; 149 150 const struct scmi_agent_resources agent_resources[] = { 151 [0] = { 152 .clock = stm32_scmi0_clock, 153 .clock_count = ARRAY_SIZE(stm32_scmi0_clock), 154 .rd = stm32_scmi0_reset_domain, 155 .rd_count = ARRAY_SIZE(stm32_scmi0_reset_domain), 156 }, 157 [1] = { 158 .clock = stm32_scmi1_clock, 159 .clock_count = ARRAY_SIZE(stm32_scmi1_clock), 160 }, 161 }; 162 163 static const struct scmi_agent_resources *find_resource(unsigned int agent_id) 164 { 165 assert(agent_id < ARRAY_SIZE(agent_resources)); 166 167 return &agent_resources[agent_id]; 168 } 169 170 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 171 { 172 unsigned int n = 0; 173 unsigned int count = 0; 174 const size_t agent_count = ARRAY_SIZE(agent_resources); 175 176 for (n = 0; n < agent_count; n++) 177 if (agent_resources[n].clock_count) 178 break; 179 if (n < agent_count) 180 count++; 181 182 for (n = 0; n < agent_count; n++) 183 if (agent_resources[n].rd_count) 184 break; 185 if (n < agent_count) 186 count++; 187 188 for (n = 0; n < agent_count; n++) 189 if (agent_resources[n].pd_count) 190 break; 191 if (n < agent_count) 192 count++; 193 194 for (n = 0; n < agent_count; n++) 195 if (agent_resources[n].perfs_count) 196 break; 197 if (n < agent_count) 198 count++; 199 200 return count; 201 } 202 203 static const char vendor[] = "ST"; 204 static const char sub_vendor[] = ""; 205 206 const char *plat_scmi_vendor_name(void) 207 { 208 return vendor; 209 } 210 211 const char *plat_scmi_sub_vendor_name(void) 212 { 213 return sub_vendor; 214 } 215 216 /* Currently supporting Clocks and Reset Domains */ 217 static const uint8_t plat_protocol_list[] = { 218 SCMI_PROTOCOL_ID_CLOCK, 219 SCMI_PROTOCOL_ID_RESET_DOMAIN, 220 0 /* Null termination */ 221 }; 222 223 size_t plat_scmi_protocol_count(void) 224 { 225 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 226 227 assert(count == plat_scmi_protocol_count_paranoid()); 228 229 return count; 230 } 231 232 const uint8_t *plat_scmi_protocol_list(unsigned int agent_id __unused) 233 { 234 assert(plat_scmi_protocol_count_paranoid() == 235 (ARRAY_SIZE(plat_protocol_list) - 1)); 236 237 return plat_protocol_list; 238 } 239 240 /* 241 * Platform SCMI clocks 242 */ 243 static struct stm32_scmi_clk *find_clock(unsigned int agent_id, 244 unsigned int scmi_id) 245 { 246 const struct scmi_agent_resources *resource = find_resource(agent_id); 247 size_t n = 0; 248 249 if (resource) { 250 for (n = 0U; n < resource->clock_count; n++) 251 if (n == scmi_id) 252 return &resource->clock[n]; 253 } 254 255 return NULL; 256 } 257 258 size_t plat_scmi_clock_count(unsigned int agent_id) 259 { 260 const struct scmi_agent_resources *resource = find_resource(agent_id); 261 262 if (!resource) 263 return 0; 264 265 return resource->clock_count; 266 } 267 268 const char *plat_scmi_clock_get_name(unsigned int agent_id, 269 unsigned int scmi_id) 270 { 271 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 272 273 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 274 return NULL; 275 276 return clock->name; 277 } 278 279 int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id, 280 size_t start_index, unsigned long *array, 281 size_t *nb_elts) 282 { 283 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 284 285 if (!clock) 286 return SCMI_NOT_FOUND; 287 288 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 289 return SCMI_DENIED; 290 291 /* Exposed clocks are currently fixed rate clocks */ 292 if (start_index) 293 return SCMI_INVALID_PARAMETERS; 294 295 if (!array) 296 *nb_elts = 1; 297 else if (*nb_elts == 1) 298 *array = stm32_clock_get_rate(clock->clock_id); 299 else 300 return SCMI_GENERIC_ERROR; 301 302 return SCMI_SUCCESS; 303 } 304 305 unsigned long plat_scmi_clock_get_rate(unsigned int agent_id, 306 unsigned int scmi_id) 307 { 308 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 309 310 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 311 return 0; 312 313 return stm32_clock_get_rate(clock->clock_id); 314 } 315 316 int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id) 317 { 318 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 319 320 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 321 return 0; 322 323 return (int32_t)clock->enabled; 324 } 325 326 int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id, 327 bool enable_not_disable) 328 { 329 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 330 331 if (!clock) 332 return SCMI_NOT_FOUND; 333 334 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 335 return SCMI_DENIED; 336 337 if (enable_not_disable) { 338 if (!clock->enabled) { 339 DMSG("SCMI clock %u enable", scmi_id); 340 stm32_clock_enable(clock->clock_id); 341 clock->enabled = true; 342 } 343 } else { 344 if (clock->enabled) { 345 DMSG("SCMI clock %u disable", scmi_id); 346 stm32_clock_disable(clock->clock_id); 347 clock->enabled = false; 348 } 349 } 350 351 return SCMI_SUCCESS; 352 } 353 354 /* 355 * Platform SCMI reset domains 356 */ 357 static struct stm32_scmi_rd *find_rd(unsigned int agent_id, 358 unsigned int scmi_id) 359 { 360 const struct scmi_agent_resources *resource = find_resource(agent_id); 361 size_t n = 0; 362 363 if (resource) { 364 for (n = 0; n < resource->rd_count; n++) 365 if (n == scmi_id) 366 return &resource->rd[n]; 367 } 368 369 return NULL; 370 } 371 372 const char *plat_scmi_rd_get_name(unsigned int agent_id, unsigned int scmi_id) 373 { 374 const struct stm32_scmi_rd *rd = find_rd(agent_id, scmi_id); 375 376 if (!rd) 377 return NULL; 378 379 return rd->name; 380 } 381 382 size_t plat_scmi_rd_count(unsigned int agent_id) 383 { 384 const struct scmi_agent_resources *resource = find_resource(agent_id); 385 386 if (!resource) 387 return 0; 388 389 return resource->rd_count; 390 } 391 392 int32_t plat_scmi_rd_autonomous(unsigned int agent_id, unsigned int scmi_id, 393 uint32_t state) 394 { 395 const struct stm32_scmi_rd *rd = find_rd(agent_id, scmi_id); 396 397 if (!rd) 398 return SCMI_NOT_FOUND; 399 400 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 401 return SCMI_DENIED; 402 403 /* Supports only reset with context loss */ 404 if (state) 405 return SCMI_NOT_SUPPORTED; 406 407 DMSG("SCMI reset %u cycle", scmi_id); 408 409 if (stm32_reset_assert(rd->reset_id, TIMEOUT_US_1MS)) 410 return SCMI_HARDWARE_ERROR; 411 412 if (stm32_reset_deassert(rd->reset_id, TIMEOUT_US_1MS)) 413 return SCMI_HARDWARE_ERROR; 414 415 return SCMI_SUCCESS; 416 } 417 418 int32_t plat_scmi_rd_set_state(unsigned int agent_id, unsigned int scmi_id, 419 bool assert_not_deassert) 420 { 421 const struct stm32_scmi_rd *rd = find_rd(agent_id, scmi_id); 422 423 if (!rd) 424 return SCMI_NOT_FOUND; 425 426 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 427 return SCMI_DENIED; 428 429 if (assert_not_deassert) { 430 DMSG("SCMI reset %u set", scmi_id); 431 stm32_reset_set(rd->reset_id); 432 } else { 433 DMSG("SCMI reset %u release", scmi_id); 434 stm32_reset_release(rd->reset_id); 435 } 436 437 return SCMI_SUCCESS; 438 } 439 440 /* 441 * Initialize platform SCMI resources 442 */ 443 static TEE_Result stm32mp1_init_scmi_server(void) 444 { 445 size_t i = 0; 446 size_t j = 0; 447 448 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 449 struct scmi_msg_channel *chan = &scmi_channel[i]; 450 451 /* Enforce non-secure shm mapped as device memory */ 452 chan->shm_addr.va = (vaddr_t)phys_to_virt(chan->shm_addr.pa, 453 MEM_AREA_IO_NSEC); 454 assert(chan->shm_addr.va); 455 456 scmi_smt_init_agent_channel(chan); 457 } 458 459 for (i = 0; i < ARRAY_SIZE(agent_resources); i++) { 460 const struct scmi_agent_resources *res = &agent_resources[i]; 461 462 for (j = 0; j < res->clock_count; j++) { 463 struct stm32_scmi_clk *clk = &res->clock[j]; 464 465 if (!clk->name || 466 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 467 panic("SCMI clock name invalid"); 468 469 /* Sync SCMI clocks with their targeted initial state */ 470 if (clk->enabled && 471 stm32mp_nsec_can_access_clock(clk->clock_id)) 472 stm32_clock_enable(clk->clock_id); 473 } 474 475 for (j = 0; j < res->rd_count; j++) { 476 struct stm32_scmi_rd *rd = &res->rd[j]; 477 478 if (!rd->name || 479 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 480 panic("SCMI reset domain name invalid"); 481 } 482 } 483 484 return TEE_SUCCESS; 485 } 486 487 driver_init_late(stm32mp1_init_scmi_server); 488