1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2022, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/stm32_etzpc.h> 12 #include <drivers/stm32_iwdg.h> 13 #include <drivers/stm32_tamp.h> 14 #include <drivers/stm32_uart.h> 15 #include <drivers/stm32mp1_etzpc.h> 16 #include <drivers/stm32mp_dt_bindings.h> 17 #include <io.h> 18 #include <kernel/boot.h> 19 #include <kernel/dt.h> 20 #include <kernel/interrupt.h> 21 #include <kernel/misc.h> 22 #include <kernel/panic.h> 23 #include <kernel/spinlock.h> 24 #include <mm/core_memprot.h> 25 #include <platform_config.h> 26 #include <sm/psci.h> 27 #include <stm32_util.h> 28 #include <string.h> 29 #include <trace.h> 30 31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB1_BASE, APB1_SIZE); 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB2_BASE, APB2_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB3_BASE, APB3_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB4_BASE, APB4_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB5_BASE, APB5_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB4_BASE, AHB4_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB5_BASE, AHB5_SIZE); 38 39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB1_BASE, APB1_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB3_BASE, APB3_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB4_BASE, APB4_SIZE); 42 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB5_BASE, APB5_SIZE); 43 #ifdef CFG_STM32MP13 44 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB6_BASE, APB6_SIZE); 45 #endif 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB4_BASE, AHB4_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB5_BASE, AHB5_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 49 50 #ifdef CFG_STM32MP1_SCMI_SHM_BASE 51 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 52 CFG_STM32MP1_SCMI_SHM_SIZE); 53 #endif 54 55 register_ddr(DDR_BASE, CFG_DRAM_SIZE); 56 57 #define _ID2STR(id) (#id) 58 #define ID2STR(id) _ID2STR(id) 59 60 static TEE_Result platform_banner(void) 61 { 62 IMSG("Platform stm32mp1: flavor %s - DT %s", 63 ID2STR(PLATFORM_FLAVOR), 64 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 65 66 return TEE_SUCCESS; 67 } 68 service_init(platform_banner); 69 70 /* 71 * Console 72 * 73 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 74 * trace console. Value 0 disables the early console. 75 * 76 * We cannot use the generic serial_console support since probing 77 * the console requires the platform clock driver to be already 78 * up and ready which is done only once service_init are completed. 79 */ 80 static struct stm32_uart_pdata console_data; 81 82 void console_init(void) 83 { 84 /* Early console initialization before MMU setup */ 85 struct uart { 86 paddr_t pa; 87 bool secure; 88 } uarts[] = { 89 [0] = { .pa = 0 }, 90 [1] = { .pa = USART1_BASE, .secure = true, }, 91 [2] = { .pa = USART2_BASE, .secure = false, }, 92 [3] = { .pa = USART3_BASE, .secure = false, }, 93 [4] = { .pa = UART4_BASE, .secure = false, }, 94 [5] = { .pa = UART5_BASE, .secure = false, }, 95 [6] = { .pa = USART6_BASE, .secure = false, }, 96 [7] = { .pa = UART7_BASE, .secure = false, }, 97 [8] = { .pa = UART8_BASE, .secure = false, }, 98 }; 99 100 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 101 102 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 103 return; 104 105 /* No clock yet bound to the UART console */ 106 console_data.clock = NULL; 107 108 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 109 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 110 111 register_serial_console(&console_data.chip); 112 113 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 114 } 115 116 static TEE_Result init_console_from_dt(void) 117 { 118 struct stm32_uart_pdata *pd = NULL; 119 void *fdt = NULL; 120 int node = 0; 121 TEE_Result res = TEE_ERROR_GENERIC; 122 123 fdt = get_embedded_dt(); 124 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 125 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 126 fdt = get_external_dt(); 127 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 128 if (res == TEE_ERROR_ITEM_NOT_FOUND) 129 return TEE_SUCCESS; 130 if (res != TEE_SUCCESS) 131 return res; 132 } 133 134 pd = stm32_uart_init_from_dt_node(fdt, node); 135 if (!pd) { 136 IMSG("DTB disables console"); 137 register_serial_console(NULL); 138 return TEE_SUCCESS; 139 } 140 141 /* Replace early console with the new one */ 142 console_flush(); 143 console_data = *pd; 144 register_serial_console(&console_data.chip); 145 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 146 free(pd); 147 148 return TEE_SUCCESS; 149 } 150 151 /* Probe console from DT once clock inits (service init level) are completed */ 152 service_init_late(init_console_from_dt); 153 154 /* 155 * GIC init, used also for primary/secondary boot core wake completion 156 */ 157 static struct gic_data gic_data; 158 159 void itr_core_handler(void) 160 { 161 gic_it_handle(&gic_data); 162 } 163 164 void main_init_gic(void) 165 { 166 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 167 itr_init(&gic_data.chip); 168 169 stm32mp_register_online_cpu(); 170 } 171 172 void main_secondary_init_gic(void) 173 { 174 gic_cpu_init(&gic_data); 175 176 stm32mp_register_online_cpu(); 177 } 178 179 #ifdef CFG_STM32MP13 180 #ifdef CFG_STM32_ETZPC 181 /* Configure ETZPC cell and lock it when resource is secure */ 182 static void config_lock_decprot(uint32_t decprot_id, 183 enum etzpc_decprot_attributes decprot_attr) 184 { 185 etzpc_configure_decprot(decprot_id, decprot_attr); 186 187 if (decprot_attr == ETZPC_DECPROT_S_RW) 188 etzpc_lock_decprot(decprot_id); 189 } 190 191 static TEE_Result set_etzpc_secure_configuration(void) 192 { 193 config_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); 194 config_lock_decprot(STM32MP1_ETZPC_DDRCTRLPHY_ID, 195 ETZPC_DECPROT_NS_R_S_W); 196 197 /* Configure ETZPC with peripheral registering */ 198 config_lock_decprot(STM32MP1_ETZPC_ADC1_ID, ETZPC_DECPROT_NS_RW); 199 config_lock_decprot(STM32MP1_ETZPC_ADC2_ID, ETZPC_DECPROT_NS_RW); 200 config_lock_decprot(STM32MP1_ETZPC_CRYP_ID, ETZPC_DECPROT_NS_RW); 201 config_lock_decprot(STM32MP1_ETZPC_DCMIPP_ID, ETZPC_DECPROT_NS_RW); 202 config_lock_decprot(STM32MP1_ETZPC_ETH1_ID, ETZPC_DECPROT_NS_RW); 203 config_lock_decprot(STM32MP1_ETZPC_ETH2_ID, ETZPC_DECPROT_NS_RW); 204 config_lock_decprot(STM32MP1_ETZPC_FMC_ID, ETZPC_DECPROT_NS_RW); 205 /* HASH is secure */ 206 config_lock_decprot(STM32MP1_ETZPC_HASH_ID, ETZPC_DECPROT_S_RW); 207 config_lock_decprot(STM32MP1_ETZPC_I2C3_ID, ETZPC_DECPROT_NS_RW); 208 /* I2C4 is secure */ 209 config_lock_decprot(STM32MP1_ETZPC_I2C4_ID, ETZPC_DECPROT_S_RW); 210 config_lock_decprot(STM32MP1_ETZPC_I2C5_ID, ETZPC_DECPROT_NS_RW); 211 /* IWDG1 is secure */ 212 config_lock_decprot(STM32MP1_ETZPC_IWDG1_ID, ETZPC_DECPROT_S_RW); 213 config_lock_decprot(STM32MP1_ETZPC_LPTIM2_ID, ETZPC_DECPROT_NS_RW); 214 /* LPTIM3 is secure */ 215 config_lock_decprot(STM32MP1_ETZPC_LPTIM3_ID, ETZPC_DECPROT_S_RW); 216 config_lock_decprot(STM32MP1_ETZPC_LTDC_ID, ETZPC_DECPROT_NS_RW); 217 /* MCE is secure */ 218 config_lock_decprot(STM32MP1_ETZPC_MCE_ID, ETZPC_DECPROT_S_RW); 219 config_lock_decprot(STM32MP1_ETZPC_OTG_ID, ETZPC_DECPROT_NS_RW); 220 /* PKA is secure */ 221 config_lock_decprot(STM32MP1_ETZPC_PKA_ID, ETZPC_DECPROT_S_RW); 222 config_lock_decprot(STM32MP1_ETZPC_QSPI_ID, ETZPC_DECPROT_NS_RW); 223 /* RNG is secure */ 224 config_lock_decprot(STM32MP1_ETZPC_RNG_ID, ETZPC_DECPROT_S_RW); 225 /* SAES is secure */ 226 config_lock_decprot(STM32MP1_ETZPC_SAES_ID, ETZPC_DECPROT_NS_RW); 227 config_lock_decprot(STM32MP1_ETZPC_SDMMC1_ID, ETZPC_DECPROT_NS_RW); 228 config_lock_decprot(STM32MP1_ETZPC_SDMMC2_ID, ETZPC_DECPROT_NS_RW); 229 config_lock_decprot(STM32MP1_ETZPC_SPI4_ID, ETZPC_DECPROT_NS_RW); 230 config_lock_decprot(STM32MP1_ETZPC_SPI5_ID, ETZPC_DECPROT_NS_RW); 231 config_lock_decprot(STM32MP1_ETZPC_SRAM1_ID, ETZPC_DECPROT_NS_RW); 232 config_lock_decprot(STM32MP1_ETZPC_SRAM2_ID, ETZPC_DECPROT_NS_RW); 233 /* SRAM3 is secure */ 234 config_lock_decprot(STM32MP1_ETZPC_SRAM3_ID, ETZPC_DECPROT_S_RW); 235 /* STGENC is secure */ 236 config_lock_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); 237 /* TIM12 is secure */ 238 config_lock_decprot(STM32MP1_ETZPC_TIM12_ID, ETZPC_DECPROT_S_RW); 239 config_lock_decprot(STM32MP1_ETZPC_TIM13_ID, ETZPC_DECPROT_NS_RW); 240 config_lock_decprot(STM32MP1_ETZPC_TIM14_ID, ETZPC_DECPROT_NS_RW); 241 /* TIM15 is secure */ 242 config_lock_decprot(STM32MP1_ETZPC_TIM15_ID, ETZPC_DECPROT_S_RW); 243 config_lock_decprot(STM32MP1_ETZPC_TIM16_ID, ETZPC_DECPROT_NS_RW); 244 config_lock_decprot(STM32MP1_ETZPC_TIM17_ID, ETZPC_DECPROT_NS_RW); 245 config_lock_decprot(STM32MP1_ETZPC_USART1_ID, ETZPC_DECPROT_NS_RW); 246 config_lock_decprot(STM32MP1_ETZPC_USART2_ID, ETZPC_DECPROT_NS_RW); 247 config_lock_decprot(STM32MP1_ETZPC_USBPHYCTRL_ID, ETZPC_DECPROT_NS_RW); 248 config_lock_decprot(STM32MP1_ETZPC_VREFBUF_ID, ETZPC_DECPROT_NS_RW); 249 250 return TEE_SUCCESS; 251 } 252 253 driver_init_late(set_etzpc_secure_configuration); 254 #endif /* CFG_STM32_ETZPC */ 255 256 #ifdef CFG_STM32_GPIO 257 258 #define NB_PINS_PER_BANK U(16) 259 #define NB_PINS_BANK_H U(14) 260 #define NB_PINS_BANK_I U(8) 261 262 static TEE_Result set_all_gpios_non_secure(void) 263 { 264 unsigned int bank = 0; 265 unsigned int pin = 0; 266 unsigned int nb_pin_bank = 0; 267 268 for (bank = 0; bank <= GPIO_BANK_I; bank++) { 269 switch (bank) { 270 case GPIO_BANK_H: 271 nb_pin_bank = NB_PINS_BANK_H; 272 break; 273 case GPIO_BANK_I: 274 nb_pin_bank = NB_PINS_BANK_I; 275 break; 276 default: 277 nb_pin_bank = NB_PINS_PER_BANK; 278 break; 279 } 280 281 for (pin = 0; pin <= nb_pin_bank; pin++) 282 stm32_gpio_set_secure_cfg(bank, pin, false); 283 } 284 285 return TEE_SUCCESS; 286 } 287 288 early_init_late(set_all_gpios_non_secure); 289 #endif /* CFG_STM32_GPIO */ 290 #endif /* CFG_STM32MP13 */ 291 292 static TEE_Result init_stm32mp1_drivers(void) 293 { 294 /* Secure internal memories for the platform, once ETZPC is ready */ 295 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 296 etzpc_lock_tzma(0); 297 298 #ifdef CFG_TZSRAM_START 299 COMPILE_TIME_ASSERT(((SYSRAM_BASE + SYSRAM_SIZE) <= CFG_TZSRAM_START) || 300 ((SYSRAM_BASE <= CFG_TZSRAM_START) && 301 (SYSRAM_SEC_SIZE >= CFG_TZSRAM_SIZE))); 302 #endif /* CFG_TZSRAM_START */ 303 304 etzpc_configure_tzma(1, SYSRAM_SEC_SIZE >> SMALL_PAGE_SHIFT); 305 etzpc_lock_tzma(1); 306 307 if (SYSRAM_SIZE > SYSRAM_SEC_SIZE) { 308 size_t nsec_size = SYSRAM_SIZE - SYSRAM_SEC_SIZE; 309 paddr_t nsec_start = SYSRAM_BASE + SYSRAM_SEC_SIZE; 310 uint8_t *va = phys_to_virt(nsec_start, MEM_AREA_IO_NSEC, 311 nsec_size); 312 313 IMSG("Non-secure SYSRAM [%p %p]", va, va + nsec_size - 1); 314 315 /* Clear content from the non-secure part */ 316 memset(va, 0, nsec_size); 317 } 318 319 return TEE_SUCCESS; 320 } 321 322 service_init_late(init_stm32mp1_drivers); 323 324 static TEE_Result init_late_stm32mp1_drivers(void) 325 { 326 TEE_Result res = TEE_ERROR_GENERIC; 327 328 /* Set access permission to TAM backup registers */ 329 if (IS_ENABLED(CFG_STM32_TAMP)) { 330 struct stm32_bkpregs_conf conf = { 331 .nb_zone1_regs = TAMP_BKP_REGISTER_ZONE1_COUNT, 332 .nb_zone2_regs = TAMP_BKP_REGISTER_ZONE2_COUNT, 333 }; 334 335 res = stm32_tamp_set_secure_bkpregs(&conf); 336 if (res == TEE_ERROR_DEFER_DRIVER_INIT) { 337 /* TAMP driver was not probed if disabled in the DT */ 338 res = TEE_SUCCESS; 339 } 340 if (res) 341 panic(); 342 } 343 344 return TEE_SUCCESS; 345 } 346 347 driver_init_late(init_late_stm32mp1_drivers); 348 349 vaddr_t stm32_rcc_base(void) 350 { 351 static struct io_pa_va base = { .pa = RCC_BASE }; 352 353 return io_pa_or_va_secure(&base, 1); 354 } 355 356 vaddr_t get_gicd_base(void) 357 { 358 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 359 360 return io_pa_or_va_secure(&base, 1); 361 } 362 363 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 364 { 365 cfg->base = BSEC_BASE; 366 cfg->upper_start = STM32MP1_UPPER_OTP_START; 367 cfg->max_id = STM32MP1_OTP_MAX_ID; 368 } 369 370 bool __weak stm32mp_with_pmic(void) 371 { 372 return false; 373 } 374 375 uint32_t may_spin_lock(unsigned int *lock) 376 { 377 if (!lock || !cpu_mmu_enabled()) 378 return 0; 379 380 return cpu_spin_lock_xsave(lock); 381 } 382 383 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 384 { 385 if (!lock || !cpu_mmu_enabled()) 386 return; 387 388 cpu_spin_unlock_xrestore(lock, exceptions); 389 } 390 391 static vaddr_t stm32_tamp_base(void) 392 { 393 static struct io_pa_va base = { .pa = TAMP_BASE }; 394 395 return io_pa_or_va_secure(&base, 1); 396 } 397 398 static vaddr_t bkpreg_base(void) 399 { 400 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 401 } 402 403 vaddr_t stm32mp_bkpreg(unsigned int idx) 404 { 405 return bkpreg_base() + (idx * sizeof(uint32_t)); 406 } 407 408 static bool __maybe_unused bank_is_valid(unsigned int bank) 409 { 410 if (IS_ENABLED(CFG_STM32MP15)) 411 return bank == GPIO_BANK_Z || bank <= GPIO_BANK_K; 412 413 if (IS_ENABLED(CFG_STM32MP13)) 414 return bank <= GPIO_BANK_I; 415 416 panic(); 417 } 418 419 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 420 { 421 static struct io_pa_va base = { .pa = GPIOA_BASE }; 422 423 static_assert(GPIO_BANK_A == 0); 424 assert(bank_is_valid(bank)); 425 426 if (IS_ENABLED(CFG_STM32MP15)) { 427 static struct io_pa_va zbase = { .pa = GPIOZ_BASE }; 428 429 /* Get secure mapping address for GPIOZ */ 430 if (bank == GPIO_BANK_Z) 431 return io_pa_or_va_secure(&zbase, GPIO_BANK_OFFSET); 432 433 /* Other are mapped non-secure */ 434 return io_pa_or_va_nsec(&base, (bank + 1) * GPIO_BANK_OFFSET) + 435 (bank * GPIO_BANK_OFFSET); 436 } 437 438 if (IS_ENABLED(CFG_STM32MP13)) 439 return io_pa_or_va_secure(&base, 440 (bank + 1) * GPIO_BANK_OFFSET) + 441 (bank * GPIO_BANK_OFFSET); 442 443 panic(); 444 } 445 446 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 447 { 448 assert(bank_is_valid(bank)); 449 450 if (bank == GPIO_BANK_Z) 451 return 0; 452 453 return bank * GPIO_BANK_OFFSET; 454 } 455 456 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 457 { 458 assert(bank_is_valid(bank)); 459 460 #ifdef CFG_STM32MP15 461 if (bank == GPIO_BANK_Z) 462 return GPIOZ; 463 #endif 464 465 return GPIOA + bank; 466 } 467 468 struct clk *stm32_get_gpio_bank_clk(unsigned int bank) 469 { 470 assert(bank_is_valid(bank)); 471 472 if (!IS_ENABLED(CFG_DRIVERS_CLK)) 473 return NULL; 474 475 return stm32mp_rcc_clock_id_to_clk(stm32_get_gpio_bank_clock(bank)); 476 } 477 478 #ifdef CFG_STM32_IWDG 479 TEE_Result stm32_get_iwdg_otp_config(paddr_t pbase, 480 struct stm32_iwdg_otp_data *otp_data) 481 { 482 unsigned int idx = 0; 483 uint32_t otp_id = 0; 484 size_t bit_len = 0; 485 uint32_t otp_value = 0; 486 487 switch (pbase) { 488 case IWDG1_BASE: 489 idx = 0; 490 break; 491 case IWDG2_BASE: 492 idx = 1; 493 break; 494 default: 495 panic(); 496 } 497 498 if (stm32_bsec_find_otp_in_nvmem_layout("hw2_otp", &otp_id, &bit_len) || 499 bit_len != 32) 500 panic(); 501 502 if (stm32_bsec_read_otp(&otp_value, otp_id)) 503 panic(); 504 505 otp_data->hw_enabled = otp_value & 506 BIT(idx + HW2_OTP_IWDG_HW_ENABLE_SHIFT); 507 otp_data->disable_on_stop = otp_value & 508 BIT(idx + HW2_OTP_IWDG_FZ_STOP_SHIFT); 509 otp_data->disable_on_standby = otp_value & 510 BIT(idx + HW2_OTP_IWDG_FZ_STANDBY_SHIFT); 511 512 return TEE_SUCCESS; 513 } 514 #endif /*CFG_STM32_IWDG*/ 515 516 #ifdef CFG_STM32_DEBUG_ACCESS 517 static TEE_Result init_debug(void) 518 { 519 TEE_Result res = TEE_SUCCESS; 520 uint32_t conf = stm32_bsec_read_debug_conf(); 521 struct clk *dbg_clk = stm32mp_rcc_clock_id_to_clk(CK_DBG); 522 uint32_t state = 0; 523 524 res = stm32_bsec_get_state(&state); 525 if (res) 526 return res; 527 528 if (state != BSEC_STATE_SEC_CLOSED && conf) { 529 if (IS_ENABLED(CFG_WARN_INSECURE)) 530 IMSG("WARNING: All debug accesses are allowed"); 531 532 res = stm32_bsec_write_debug_conf(conf | BSEC_DEBUG_ALL); 533 if (res) 534 return res; 535 536 /* 537 * Enable DBG clock as used to access coprocessor 538 * debug registers 539 */ 540 clk_enable(dbg_clk); 541 } 542 543 return TEE_SUCCESS; 544 } 545 early_init_late(init_debug); 546 #endif /* CFG_STM32_DEBUG_ACCESS */ 547