1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_etzpc.h> 11 #include <drivers/stm32_uart.h> 12 #include <drivers/stm32mp1_etzpc.h> 13 #include <dt-bindings/clock/stm32mp1-clks.h> 14 #include <kernel/generic_boot.h> 15 #include <kernel/dt.h> 16 #include <kernel/misc.h> 17 #include <kernel/panic.h> 18 #include <kernel/pm_stubs.h> 19 #include <kernel/spinlock.h> 20 #include <mm/core_memprot.h> 21 #include <platform_config.h> 22 #include <sm/psci.h> 23 #include <stm32_util.h> 24 #include <tee/entry_std.h> 25 #include <tee/entry_fast.h> 26 #include <trace.h> 27 28 #ifdef CFG_WITH_NSEC_GPIOS 29 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIOS_NSEC_BASE, GPIOS_NSEC_SIZE); 30 #endif 31 #ifdef CFG_WITH_NSEC_UARTS 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 40 #endif 41 42 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BSEC_BASE, SMALL_PAGE_SIZE); 43 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ETZPC_BASE, SMALL_PAGE_SIZE); 44 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 45 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GPIOZ_BASE, SMALL_PAGE_SIZE); 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 50 51 static void main_fiq(void); 52 53 static const struct thread_handlers handlers = { 54 .std_smc = tee_entry_std, 55 .fast_smc = tee_entry_fast, 56 .nintr = main_fiq, 57 .cpu_on = pm_panic, 58 .cpu_off = pm_panic, 59 .cpu_suspend = pm_panic, 60 .cpu_resume = pm_panic, 61 .system_off = pm_panic, 62 .system_reset = pm_panic, 63 }; 64 65 const struct thread_handlers *generic_boot_get_handlers(void) 66 { 67 return &handlers; 68 } 69 70 #define _ID2STR(id) (#id) 71 #define ID2STR(id) _ID2STR(id) 72 73 static TEE_Result platform_banner(void) 74 { 75 #ifdef CFG_EMBED_DTB 76 IMSG("Platform stm32mp1: flavor %s - DT %s", 77 ID2STR(PLATFORM_FLAVOR), 78 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 79 #else 80 IMSG("Platform stm32mp1: flavor %s - no device tree", 81 ID2STR(PLATFORM_FLAVOR)); 82 #endif 83 84 return TEE_SUCCESS; 85 } 86 service_init(platform_banner); 87 88 /* 89 * Console 90 * 91 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 92 * trace console. Value 0 disables the early console. 93 * 94 * We cannot use the generic serial_console support since probing 95 * the console requires the platform clock driver to be already 96 * up and ready which is done only once service_init are completed. 97 */ 98 static struct stm32_uart_pdata console_data; 99 100 void console_init(void) 101 { 102 /* Early console initialization before MMU setup */ 103 struct uart { 104 uintptr_t pa; 105 bool secure; 106 } uarts[] = { 107 [0] = { .pa = 0 }, 108 [1] = { .pa = USART1_BASE, .secure = true, }, 109 [2] = { .pa = USART2_BASE, .secure = false, }, 110 [3] = { .pa = USART3_BASE, .secure = false, }, 111 [4] = { .pa = UART4_BASE, .secure = false, }, 112 [5] = { .pa = UART5_BASE, .secure = false, }, 113 [6] = { .pa = USART6_BASE, .secure = false, }, 114 [7] = { .pa = UART7_BASE, .secure = false, }, 115 [8] = { .pa = UART8_BASE, .secure = false, }, 116 }; 117 118 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 119 assert(!cpu_mmu_enabled()); 120 121 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 122 return; 123 124 /* No clock yet bound to the UART console */ 125 console_data.clock = DT_INFO_INVALID_CLOCK; 126 127 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 128 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 129 130 register_serial_console(&console_data.chip); 131 132 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 133 } 134 135 #ifdef CFG_DT 136 static TEE_Result init_console_from_dt(void) 137 { 138 struct stm32_uart_pdata *pd; 139 void *fdt; 140 int node; 141 142 if (get_console_node_from_dt(&fdt, &node, NULL, NULL)) 143 return TEE_SUCCESS; 144 145 pd = stm32_uart_init_from_dt_node(fdt, node); 146 if (!pd) { 147 IMSG("DTB disables console"); 148 register_serial_console(NULL); 149 return TEE_SUCCESS; 150 } 151 152 /* Replace early console with the new one */ 153 console_flush(); 154 console_data = *pd; 155 free(pd); 156 register_serial_console(&console_data.chip); 157 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 158 159 return TEE_SUCCESS; 160 } 161 162 /* Probe console from DT once clock inits (service init level) are completed */ 163 service_init_late(init_console_from_dt); 164 #endif 165 166 /* 167 * GIC init, used also for primary/secondary boot core wake completion 168 */ 169 static struct gic_data gic_data; 170 171 static void main_fiq(void) 172 { 173 gic_it_handle(&gic_data); 174 } 175 176 void main_init_gic(void) 177 { 178 assert(cpu_mmu_enabled()); 179 180 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 181 itr_init(&gic_data.chip); 182 183 stm32mp_register_online_cpu(); 184 } 185 186 void main_secondary_init_gic(void) 187 { 188 gic_cpu_init(&gic_data); 189 190 stm32mp_register_online_cpu(); 191 } 192 193 #ifndef CFG_EMBED_DTB 194 static TEE_Result init_stm32mp1_drivers(void) 195 { 196 /* Without secure DTB support, some drivers must be inited */ 197 stm32_etzpc_init(ETZPC_BASE); 198 199 return TEE_SUCCESS; 200 } 201 driver_init(init_stm32mp1_drivers); 202 #endif /*!CFG_EMBED_DTB*/ 203 204 /* Platform initializations once all drivers are ready */ 205 static TEE_Result init_late_stm32mp1_drivers(void) 206 { 207 /* Secure internal memories for the platform, once ETZPC is ready */ 208 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 209 etzpc_lock_tzma(0); 210 etzpc_configure_tzma(1, ETZPC_TZMA_ALL_SECURE); 211 etzpc_lock_tzma(1); 212 213 /* Static secure DECPROT configuration */ 214 etzpc_configure_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); 215 etzpc_configure_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); 216 etzpc_configure_decprot(STM32MP1_ETZPC_IWDG1_ID, ETZPC_DECPROT_S_RW); 217 etzpc_configure_decprot(STM32MP1_ETZPC_DDRCTRL_ID, ETZPC_DECPROT_S_RW); 218 etzpc_configure_decprot(STM32MP1_ETZPC_DDRPHYC_ID, ETZPC_DECPROT_S_RW); 219 etzpc_lock_decprot(STM32MP1_ETZPC_STGENC_ID); 220 etzpc_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID); 221 etzpc_lock_decprot(STM32MP1_ETZPC_IWDG1_ID); 222 etzpc_lock_decprot(STM32MP1_ETZPC_DDRCTRL_ID); 223 etzpc_lock_decprot(STM32MP1_ETZPC_DDRPHYC_ID); 224 /* Static non-secure DECPROT configuration */ 225 etzpc_configure_decprot(STM32MP1_ETZPC_I2C4_ID, ETZPC_DECPROT_NS_RW); 226 etzpc_configure_decprot(STM32MP1_ETZPC_RNG1_ID, ETZPC_DECPROT_NS_RW); 227 etzpc_configure_decprot(STM32MP1_ETZPC_HASH1_ID, ETZPC_DECPROT_NS_RW); 228 etzpc_configure_decprot(STM32MP1_ETZPC_CRYP1_ID, ETZPC_DECPROT_NS_RW); 229 /* Release few resource to the non-secure world */ 230 etzpc_configure_decprot(STM32MP1_ETZPC_USART1_ID, ETZPC_DECPROT_NS_RW); 231 etzpc_configure_decprot(STM32MP1_ETZPC_SPI6_ID, ETZPC_DECPROT_NS_RW); 232 etzpc_configure_decprot(STM32MP1_ETZPC_I2C6_ID, ETZPC_DECPROT_NS_RW); 233 234 return TEE_SUCCESS; 235 } 236 driver_init_late(init_late_stm32mp1_drivers); 237 238 uintptr_t get_gicc_base(void) 239 { 240 uintptr_t pbase = GIC_BASE + GICC_OFFSET; 241 242 if (cpu_mmu_enabled()) 243 return (uintptr_t)phys_to_virt_io(pbase); 244 245 return pbase; 246 } 247 248 uintptr_t get_gicd_base(void) 249 { 250 uintptr_t pbase = GIC_BASE + GICD_OFFSET; 251 252 if (cpu_mmu_enabled()) 253 return (uintptr_t)phys_to_virt_io(pbase); 254 255 return pbase; 256 } 257 258 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 259 { 260 cfg->base = BSEC_BASE; 261 cfg->upper_start = STM32MP1_UPPER_OTP_START; 262 cfg->max_id = STM32MP1_OTP_MAX_ID; 263 cfg->closed_device_id = DATA0_OTP; 264 cfg->closed_device_position = DATA0_OTP_SECURED_POS; 265 } 266 267 uint32_t may_spin_lock(unsigned int *lock) 268 { 269 if (!lock || !cpu_mmu_enabled()) 270 return 0; 271 272 return cpu_spin_lock_xsave(lock); 273 } 274 275 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 276 { 277 if (!lock || !cpu_mmu_enabled()) 278 return; 279 280 cpu_spin_unlock_xrestore(lock, exceptions); 281 } 282 283 static uintptr_t stm32_tamp_base(void) 284 { 285 static struct io_pa_va base = { .pa = TAMP_BASE }; 286 287 return io_pa_or_va(&base); 288 } 289 290 static uintptr_t bkpreg_base(void) 291 { 292 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 293 } 294 295 uintptr_t stm32mp_bkpreg(unsigned int idx) 296 { 297 return bkpreg_base() + (idx * sizeof(uint32_t)); 298 } 299 300 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 301 { 302 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 303 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 304 305 if (bank == GPIO_BANK_Z) 306 return io_pa_or_va(&gpioz_base); 307 308 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 309 assert(bank <= GPIO_BANK_K); 310 311 return io_pa_or_va(&gpios_nsec_base) + (bank * GPIO_BANK_OFFSET); 312 } 313 314 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 315 { 316 if (bank == GPIO_BANK_Z) 317 return 0; 318 319 assert(bank <= GPIO_BANK_K); 320 return bank * GPIO_BANK_OFFSET; 321 } 322 323 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 324 { 325 if (bank == GPIO_BANK_Z) 326 return GPIOZ; 327 328 assert(bank <= GPIO_BANK_K); 329 return GPIOA + bank; 330 } 331