1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/stm32_etzpc.h> 12 #include <drivers/stm32mp1_etzpc.h> 13 #include <drivers/stm32_uart.h> 14 #include <dt-bindings/clock/stm32mp1-clks.h> 15 #include <kernel/dt.h> 16 #include <kernel/generic_boot.h> 17 #include <kernel/interrupt.h> 18 #include <kernel/misc.h> 19 #include <kernel/panic.h> 20 #include <kernel/pm_stubs.h> 21 #include <kernel/spinlock.h> 22 #include <mm/core_memprot.h> 23 #include <platform_config.h> 24 #include <sm/psci.h> 25 #include <stm32_util.h> 26 #include <tee/entry_fast.h> 27 #include <tee/entry_std.h> 28 #include <trace.h> 29 30 #ifdef CFG_WITH_NSEC_GPIOS 31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIOS_NSEC_BASE, GPIOS_NSEC_SIZE); 32 #endif 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C4_BASE, SMALL_PAGE_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C6_BASE, SMALL_PAGE_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, RNG1_BASE, SMALL_PAGE_SIZE); 36 #ifdef CFG_WITH_NSEC_UARTS 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 42 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 43 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 44 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 45 #endif 46 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BSEC_BASE, SMALL_PAGE_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ETZPC_BASE, SMALL_PAGE_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GPIOZ_BASE, SMALL_PAGE_SIZE); 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C4_BASE, SMALL_PAGE_SIZE); 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C6_BASE, SMALL_PAGE_SIZE); 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG1_BASE, SMALL_PAGE_SIZE); 56 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 57 register_phys_mem_pgdir(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 58 59 #if DDR_BASE < CFG_TZDRAM_START 60 register_dynamic_shm(DDR_BASE, CFG_TZDRAM_START - DDR_BASE); 61 #endif 62 63 #define DRAM_END (DDR_BASE + CFG_DRAM_SIZE) 64 #define TZDRAM_END (CFG_TZDRAM_START + CFG_TZDRAM_SIZE) 65 66 #if DRAM_END > TZDRAM_END 67 register_dynamic_shm(TZDRAM_END, DRAM_END - TZDRAM_END); 68 #endif 69 70 static const struct thread_handlers handlers = { 71 .cpu_on = pm_panic, 72 .cpu_off = pm_panic, 73 .cpu_suspend = pm_panic, 74 .cpu_resume = pm_panic, 75 .system_off = pm_panic, 76 .system_reset = pm_panic, 77 }; 78 79 const struct thread_handlers *generic_boot_get_handlers(void) 80 { 81 return &handlers; 82 } 83 84 #define _ID2STR(id) (#id) 85 #define ID2STR(id) _ID2STR(id) 86 87 static TEE_Result platform_banner(void) 88 { 89 #ifdef CFG_EMBED_DTB 90 IMSG("Platform stm32mp1: flavor %s - DT %s", 91 ID2STR(PLATFORM_FLAVOR), 92 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 93 #else 94 IMSG("Platform stm32mp1: flavor %s - no device tree", 95 ID2STR(PLATFORM_FLAVOR)); 96 #endif 97 98 return TEE_SUCCESS; 99 } 100 service_init(platform_banner); 101 102 /* 103 * Console 104 * 105 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 106 * trace console. Value 0 disables the early console. 107 * 108 * We cannot use the generic serial_console support since probing 109 * the console requires the platform clock driver to be already 110 * up and ready which is done only once service_init are completed. 111 */ 112 static struct stm32_uart_pdata console_data; 113 114 void console_init(void) 115 { 116 /* Early console initialization before MMU setup */ 117 struct uart { 118 paddr_t pa; 119 bool secure; 120 } uarts[] = { 121 [0] = { .pa = 0 }, 122 [1] = { .pa = USART1_BASE, .secure = true, }, 123 [2] = { .pa = USART2_BASE, .secure = false, }, 124 [3] = { .pa = USART3_BASE, .secure = false, }, 125 [4] = { .pa = UART4_BASE, .secure = false, }, 126 [5] = { .pa = UART5_BASE, .secure = false, }, 127 [6] = { .pa = USART6_BASE, .secure = false, }, 128 [7] = { .pa = UART7_BASE, .secure = false, }, 129 [8] = { .pa = UART8_BASE, .secure = false, }, 130 }; 131 132 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 133 134 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 135 return; 136 137 /* No clock yet bound to the UART console */ 138 console_data.clock = DT_INFO_INVALID_CLOCK; 139 140 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 141 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 142 143 register_serial_console(&console_data.chip); 144 145 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 146 } 147 148 #ifdef CFG_DT 149 static TEE_Result init_console_from_dt(void) 150 { 151 struct stm32_uart_pdata *pd = NULL; 152 void *fdt = NULL; 153 int node = 0; 154 TEE_Result res = TEE_ERROR_GENERIC; 155 156 fdt = get_embedded_dt(); 157 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 158 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 159 fdt = get_external_dt(); 160 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 161 if (res == TEE_ERROR_ITEM_NOT_FOUND) 162 return TEE_SUCCESS; 163 if (res != TEE_SUCCESS) 164 return res; 165 } 166 167 pd = stm32_uart_init_from_dt_node(fdt, node); 168 if (!pd) { 169 IMSG("DTB disables console"); 170 register_serial_console(NULL); 171 return TEE_SUCCESS; 172 } 173 174 /* Replace early console with the new one */ 175 console_flush(); 176 console_data = *pd; 177 free(pd); 178 register_serial_console(&console_data.chip); 179 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 180 181 return TEE_SUCCESS; 182 } 183 184 /* Probe console from DT once clock inits (service init level) are completed */ 185 service_init_late(init_console_from_dt); 186 #endif 187 188 /* 189 * GIC init, used also for primary/secondary boot core wake completion 190 */ 191 static struct gic_data gic_data; 192 193 void itr_core_handler(void) 194 { 195 gic_it_handle(&gic_data); 196 } 197 198 void main_init_gic(void) 199 { 200 assert(cpu_mmu_enabled()); 201 202 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 203 itr_init(&gic_data.chip); 204 205 stm32mp_register_online_cpu(); 206 } 207 208 void main_secondary_init_gic(void) 209 { 210 gic_cpu_init(&gic_data); 211 212 stm32mp_register_online_cpu(); 213 } 214 215 static TEE_Result init_stm32mp1_drivers(void) 216 { 217 /* Without secure DTB support, some drivers must be inited */ 218 if (!IS_ENABLED(CFG_EMBED_DTB)) 219 stm32_etzpc_init(ETZPC_BASE); 220 221 /* Secure internal memories for the platform, once ETZPC is ready */ 222 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 223 etzpc_lock_tzma(0); 224 225 COMPILE_TIME_ASSERT(((SYSRAM_BASE + SYSRAM_SIZE) <= CFG_TZSRAM_START) || 226 ((SYSRAM_BASE <= CFG_TZSRAM_START) && 227 (SYSRAM_SEC_SIZE >= CFG_TZSRAM_SIZE))); 228 229 etzpc_configure_tzma(1, SYSRAM_SEC_SIZE >> SMALL_PAGE_SHIFT); 230 etzpc_lock_tzma(1); 231 232 return TEE_SUCCESS; 233 } 234 service_init_late(init_stm32mp1_drivers); 235 236 vaddr_t get_gicc_base(void) 237 { 238 struct io_pa_va base = { .pa = GIC_BASE + GICC_OFFSET }; 239 240 return io_pa_or_va_secure(&base); 241 } 242 243 vaddr_t get_gicd_base(void) 244 { 245 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 246 247 return io_pa_or_va_secure(&base); 248 } 249 250 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 251 { 252 cfg->base = BSEC_BASE; 253 cfg->upper_start = STM32MP1_UPPER_OTP_START; 254 cfg->max_id = STM32MP1_OTP_MAX_ID; 255 } 256 257 bool stm32mp_is_closed_device(void) 258 { 259 uint32_t otp = 0; 260 TEE_Result result = TEE_ERROR_GENERIC; 261 262 /* Non closed_device platform expects fuse well programmed to 0 */ 263 result = stm32_bsec_shadow_read_otp(&otp, DATA0_OTP); 264 if (!result && !(otp & BIT(DATA0_OTP_SECURED_POS))) 265 return false; 266 267 return true; 268 } 269 270 uint32_t may_spin_lock(unsigned int *lock) 271 { 272 if (!lock || !cpu_mmu_enabled()) 273 return 0; 274 275 return cpu_spin_lock_xsave(lock); 276 } 277 278 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 279 { 280 if (!lock || !cpu_mmu_enabled()) 281 return; 282 283 cpu_spin_unlock_xrestore(lock, exceptions); 284 } 285 286 static vaddr_t stm32_tamp_base(void) 287 { 288 static struct io_pa_va base = { .pa = TAMP_BASE }; 289 290 return io_pa_or_va_secure(&base); 291 } 292 293 static vaddr_t bkpreg_base(void) 294 { 295 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 296 } 297 298 vaddr_t stm32mp_bkpreg(unsigned int idx) 299 { 300 return bkpreg_base() + (idx * sizeof(uint32_t)); 301 } 302 303 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 304 { 305 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 306 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 307 308 /* Get secure mapping address for GPIOZ */ 309 if (bank == GPIO_BANK_Z) 310 return io_pa_or_va_secure(&gpioz_base); 311 312 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 313 assert(bank <= GPIO_BANK_K); 314 315 return io_pa_or_va_nsec(&gpios_nsec_base) + (bank * GPIO_BANK_OFFSET); 316 } 317 318 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 319 { 320 if (bank == GPIO_BANK_Z) 321 return 0; 322 323 assert(bank <= GPIO_BANK_K); 324 return bank * GPIO_BANK_OFFSET; 325 } 326 327 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 328 { 329 if (bank == GPIO_BANK_Z) 330 return GPIOZ; 331 332 assert(bank <= GPIO_BANK_K); 333 return GPIOA + bank; 334 } 335