1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/stm32_etzpc.h> 12 #include <drivers/stm32mp1_etzpc.h> 13 #include <drivers/stm32_uart.h> 14 #include <dt-bindings/clock/stm32mp1-clks.h> 15 #include <kernel/dt.h> 16 #include <kernel/generic_boot.h> 17 #include <kernel/interrupt.h> 18 #include <kernel/misc.h> 19 #include <kernel/panic.h> 20 #include <kernel/pm_stubs.h> 21 #include <kernel/spinlock.h> 22 #include <mm/core_memprot.h> 23 #include <platform_config.h> 24 #include <sm/psci.h> 25 #include <stm32_util.h> 26 #include <tee/entry_fast.h> 27 #include <tee/entry_std.h> 28 #include <trace.h> 29 30 #ifdef CFG_WITH_NSEC_GPIOS 31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIOS_NSEC_BASE, GPIOS_NSEC_SIZE); 32 #endif 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C4_BASE, SMALL_PAGE_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C6_BASE, SMALL_PAGE_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, RNG1_BASE, SMALL_PAGE_SIZE); 36 #ifdef CFG_WITH_NSEC_UARTS 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 42 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 43 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 44 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 45 #endif 46 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BSEC_BASE, SMALL_PAGE_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ETZPC_BASE, SMALL_PAGE_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GPIOZ_BASE, SMALL_PAGE_SIZE); 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C4_BASE, SMALL_PAGE_SIZE); 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C6_BASE, SMALL_PAGE_SIZE); 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG1_BASE, SMALL_PAGE_SIZE); 56 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 57 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC_BASE, SMALL_PAGE_SIZE); 58 register_phys_mem_pgdir(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 59 60 #if DDR_BASE < CFG_TZDRAM_START 61 register_dynamic_shm(DDR_BASE, CFG_TZDRAM_START - DDR_BASE); 62 #endif 63 64 #define DRAM_END (DDR_BASE + CFG_DRAM_SIZE) 65 #define TZDRAM_END (CFG_TZDRAM_START + CFG_TZDRAM_SIZE) 66 67 #if DRAM_END > TZDRAM_END 68 register_dynamic_shm(TZDRAM_END, DRAM_END - TZDRAM_END); 69 #endif 70 71 static const struct thread_handlers handlers = { 72 .cpu_on = pm_panic, 73 .cpu_off = pm_panic, 74 .cpu_suspend = pm_panic, 75 .cpu_resume = pm_panic, 76 .system_off = pm_panic, 77 .system_reset = pm_panic, 78 }; 79 80 const struct thread_handlers *generic_boot_get_handlers(void) 81 { 82 return &handlers; 83 } 84 85 #define _ID2STR(id) (#id) 86 #define ID2STR(id) _ID2STR(id) 87 88 static TEE_Result platform_banner(void) 89 { 90 #ifdef CFG_EMBED_DTB 91 IMSG("Platform stm32mp1: flavor %s - DT %s", 92 ID2STR(PLATFORM_FLAVOR), 93 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 94 #else 95 IMSG("Platform stm32mp1: flavor %s - no device tree", 96 ID2STR(PLATFORM_FLAVOR)); 97 #endif 98 99 return TEE_SUCCESS; 100 } 101 service_init(platform_banner); 102 103 /* 104 * Console 105 * 106 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 107 * trace console. Value 0 disables the early console. 108 * 109 * We cannot use the generic serial_console support since probing 110 * the console requires the platform clock driver to be already 111 * up and ready which is done only once service_init are completed. 112 */ 113 static struct stm32_uart_pdata console_data; 114 115 void console_init(void) 116 { 117 /* Early console initialization before MMU setup */ 118 struct uart { 119 paddr_t pa; 120 bool secure; 121 } uarts[] = { 122 [0] = { .pa = 0 }, 123 [1] = { .pa = USART1_BASE, .secure = true, }, 124 [2] = { .pa = USART2_BASE, .secure = false, }, 125 [3] = { .pa = USART3_BASE, .secure = false, }, 126 [4] = { .pa = UART4_BASE, .secure = false, }, 127 [5] = { .pa = UART5_BASE, .secure = false, }, 128 [6] = { .pa = USART6_BASE, .secure = false, }, 129 [7] = { .pa = UART7_BASE, .secure = false, }, 130 [8] = { .pa = UART8_BASE, .secure = false, }, 131 }; 132 133 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 134 135 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 136 return; 137 138 /* No clock yet bound to the UART console */ 139 console_data.clock = DT_INFO_INVALID_CLOCK; 140 141 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 142 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 143 144 register_serial_console(&console_data.chip); 145 146 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 147 } 148 149 #ifdef CFG_DT 150 static TEE_Result init_console_from_dt(void) 151 { 152 struct stm32_uart_pdata *pd = NULL; 153 void *fdt = NULL; 154 int node = 0; 155 TEE_Result res = TEE_ERROR_GENERIC; 156 157 fdt = get_embedded_dt(); 158 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 159 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 160 fdt = get_external_dt(); 161 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 162 if (res == TEE_ERROR_ITEM_NOT_FOUND) 163 return TEE_SUCCESS; 164 if (res != TEE_SUCCESS) 165 return res; 166 } 167 168 pd = stm32_uart_init_from_dt_node(fdt, node); 169 if (!pd) { 170 IMSG("DTB disables console"); 171 register_serial_console(NULL); 172 return TEE_SUCCESS; 173 } 174 175 /* Replace early console with the new one */ 176 console_flush(); 177 console_data = *pd; 178 free(pd); 179 register_serial_console(&console_data.chip); 180 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 181 182 return TEE_SUCCESS; 183 } 184 185 /* Probe console from DT once clock inits (service init level) are completed */ 186 service_init_late(init_console_from_dt); 187 #endif 188 189 /* 190 * GIC init, used also for primary/secondary boot core wake completion 191 */ 192 static struct gic_data gic_data; 193 194 void itr_core_handler(void) 195 { 196 gic_it_handle(&gic_data); 197 } 198 199 void main_init_gic(void) 200 { 201 assert(cpu_mmu_enabled()); 202 203 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 204 itr_init(&gic_data.chip); 205 206 stm32mp_register_online_cpu(); 207 } 208 209 void main_secondary_init_gic(void) 210 { 211 gic_cpu_init(&gic_data); 212 213 stm32mp_register_online_cpu(); 214 } 215 216 static TEE_Result init_stm32mp1_drivers(void) 217 { 218 /* Without secure DTB support, some drivers must be inited */ 219 if (!IS_ENABLED(CFG_EMBED_DTB)) 220 stm32_etzpc_init(ETZPC_BASE); 221 222 /* Secure internal memories for the platform, once ETZPC is ready */ 223 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 224 etzpc_lock_tzma(0); 225 226 COMPILE_TIME_ASSERT(((SYSRAM_BASE + SYSRAM_SIZE) <= CFG_TZSRAM_START) || 227 ((SYSRAM_BASE <= CFG_TZSRAM_START) && 228 (SYSRAM_SEC_SIZE >= CFG_TZSRAM_SIZE))); 229 230 etzpc_configure_tzma(1, SYSRAM_SEC_SIZE >> SMALL_PAGE_SHIFT); 231 etzpc_lock_tzma(1); 232 233 return TEE_SUCCESS; 234 } 235 service_init_late(init_stm32mp1_drivers); 236 237 vaddr_t get_gicc_base(void) 238 { 239 struct io_pa_va base = { .pa = GIC_BASE + GICC_OFFSET }; 240 241 return io_pa_or_va_secure(&base); 242 } 243 244 vaddr_t get_gicd_base(void) 245 { 246 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 247 248 return io_pa_or_va_secure(&base); 249 } 250 251 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 252 { 253 cfg->base = BSEC_BASE; 254 cfg->upper_start = STM32MP1_UPPER_OTP_START; 255 cfg->max_id = STM32MP1_OTP_MAX_ID; 256 } 257 258 bool stm32mp_is_closed_device(void) 259 { 260 uint32_t otp = 0; 261 TEE_Result result = TEE_ERROR_GENERIC; 262 263 /* Non closed_device platform expects fuse well programmed to 0 */ 264 result = stm32_bsec_shadow_read_otp(&otp, DATA0_OTP); 265 if (!result && !(otp & BIT(DATA0_OTP_SECURED_POS))) 266 return false; 267 268 return true; 269 } 270 271 bool __weak stm32mp_with_pmic(void) 272 { 273 return false; 274 } 275 276 uint32_t may_spin_lock(unsigned int *lock) 277 { 278 if (!lock || !cpu_mmu_enabled()) 279 return 0; 280 281 return cpu_spin_lock_xsave(lock); 282 } 283 284 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 285 { 286 if (!lock || !cpu_mmu_enabled()) 287 return; 288 289 cpu_spin_unlock_xrestore(lock, exceptions); 290 } 291 292 static vaddr_t stm32_tamp_base(void) 293 { 294 static struct io_pa_va base = { .pa = TAMP_BASE }; 295 296 return io_pa_or_va_secure(&base); 297 } 298 299 static vaddr_t bkpreg_base(void) 300 { 301 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 302 } 303 304 vaddr_t stm32mp_bkpreg(unsigned int idx) 305 { 306 return bkpreg_base() + (idx * sizeof(uint32_t)); 307 } 308 309 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 310 { 311 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 312 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 313 314 /* Get secure mapping address for GPIOZ */ 315 if (bank == GPIO_BANK_Z) 316 return io_pa_or_va_secure(&gpioz_base); 317 318 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 319 assert(bank <= GPIO_BANK_K); 320 321 return io_pa_or_va_nsec(&gpios_nsec_base) + (bank * GPIO_BANK_OFFSET); 322 } 323 324 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 325 { 326 if (bank == GPIO_BANK_Z) 327 return 0; 328 329 assert(bank <= GPIO_BANK_K); 330 return bank * GPIO_BANK_OFFSET; 331 } 332 333 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 334 { 335 if (bank == GPIO_BANK_Z) 336 return GPIOZ; 337 338 assert(bank <= GPIO_BANK_K); 339 return GPIOA + bank; 340 } 341