1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2025, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/firewall_device.h> 11 #include <drivers/gic.h> 12 #include <drivers/pinctrl.h> 13 #include <drivers/stm32_bsec.h> 14 #include <drivers/stm32_gpio.h> 15 #include <drivers/stm32_uart.h> 16 #include <drivers/stm32mp_dt_bindings.h> 17 #ifdef CFG_STM32MP15 18 #include <drivers/stm32mp1_rcc.h> 19 #endif 20 #include <io.h> 21 #include <kernel/boot.h> 22 #include <kernel/dt.h> 23 #include <kernel/dt_driver.h> 24 #include <kernel/misc.h> 25 #include <kernel/panic.h> 26 #include <kernel/spinlock.h> 27 #include <kernel/tee_misc.h> 28 #include <libfdt.h> 29 #include <mm/core_memprot.h> 30 #include <platform_config.h> 31 #include <sm/psci.h> 32 #include <stm32_util.h> 33 #include <string.h> 34 #include <trace.h> 35 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB1_BASE, APB1_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB2_BASE, APB2_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB3_BASE, APB3_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB4_BASE, APB4_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB5_BASE, APB5_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB4_BASE, AHB4_SIZE); 42 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB5_BASE, AHB5_SIZE); 43 44 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB1_BASE, APB1_SIZE); 45 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB3_BASE, APB3_SIZE); 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB4_BASE, APB4_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB5_BASE, APB5_SIZE); 48 #ifdef CFG_STM32MP13 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB6_BASE, APB6_SIZE); 50 #endif 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB4_BASE, AHB4_SIZE); 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB5_BASE, AHB5_SIZE); 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 54 55 register_ddr(DDR_BASE, CFG_DRAM_SIZE); 56 57 #define _ID2STR(id) (#id) 58 #define ID2STR(id) _ID2STR(id) 59 60 static TEE_Result platform_banner(void) 61 { 62 IMSG("Platform stm32mp1: flavor %s - DT %s", 63 ID2STR(PLATFORM_FLAVOR), 64 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 65 66 return TEE_SUCCESS; 67 } 68 service_init(platform_banner); 69 70 /* 71 * Console 72 * 73 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 74 * trace console. Value 0 disables the early console. 75 * 76 * We cannot use the generic serial_console support since probing 77 * the console requires the platform clock driver to be already 78 * up and ready which is done only once service_init are completed. 79 */ 80 static struct stm32_uart_pdata console_data; 81 82 void plat_console_init(void) 83 { 84 /* Early console initialization before MMU setup */ 85 struct uart { 86 paddr_t pa; 87 } uarts[] = { 88 [0] = { .pa = 0 }, 89 [1] = { .pa = USART1_BASE }, 90 [2] = { .pa = USART2_BASE }, 91 [3] = { .pa = USART3_BASE }, 92 [4] = { .pa = UART4_BASE }, 93 [5] = { .pa = UART5_BASE }, 94 [6] = { .pa = USART6_BASE }, 95 [7] = { .pa = UART7_BASE }, 96 [8] = { .pa = UART8_BASE }, 97 }; 98 99 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 100 101 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 102 return; 103 104 /* No clock yet bound to the UART console */ 105 console_data.clock = NULL; 106 107 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 108 109 register_serial_console(&console_data.chip); 110 111 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 112 } 113 114 static TEE_Result init_console_from_dt(void) 115 { 116 struct stm32_uart_pdata *pd = NULL; 117 void *fdt = NULL; 118 int node = 0; 119 TEE_Result res = TEE_ERROR_GENERIC; 120 121 fdt = get_embedded_dt(); 122 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 123 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 124 fdt = get_external_dt(); 125 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 126 if (res == TEE_ERROR_ITEM_NOT_FOUND) 127 return TEE_SUCCESS; 128 if (res != TEE_SUCCESS) 129 return res; 130 } 131 132 pd = stm32_uart_init_from_dt_node(fdt, node); 133 if (!pd) { 134 IMSG("DTB disables console"); 135 register_serial_console(NULL); 136 return TEE_SUCCESS; 137 } 138 139 /* Replace early console with the new one */ 140 console_flush(); 141 console_data = *pd; 142 register_serial_console(&console_data.chip); 143 IMSG("DTB enables console"); 144 free(pd); 145 146 return TEE_SUCCESS; 147 } 148 149 /* Probe console from DT once clock inits (service init level) are completed */ 150 service_init_late(init_console_from_dt); 151 152 static uintptr_t stm32_dbgmcu_base(void) 153 { 154 static void *va; 155 156 if (!cpu_mmu_enabled()) 157 return DBGMCU_BASE; 158 159 if (!va) 160 va = phys_to_virt(DBGMCU_BASE, MEM_AREA_IO_SEC, 1); 161 162 return (uintptr_t)va; 163 } 164 165 /* SoC device ID util, returns default ID if can't access DBGMCU */ 166 TEE_Result stm32mp1_dbgmcu_get_chip_dev_id(uint32_t *chip_dev_id) 167 { 168 uint32_t id = STM32MP1_CHIP_ID; 169 170 assert(chip_dev_id); 171 172 if (stm32_bsec_read_debug_conf() & BSEC_DBGSWGEN) 173 id = io_read32(stm32_dbgmcu_base() + DBGMCU_IDC) & 174 DBGMCU_IDC_DEV_ID_MASK; 175 176 *chip_dev_id = id; 177 178 return TEE_SUCCESS; 179 } 180 181 /* 182 * GIC init, used also for primary/secondary boot core wake completion 183 */ 184 void boot_primary_init_intc(void) 185 { 186 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 187 188 stm32mp_register_online_cpu(); 189 } 190 191 void boot_secondary_init_intc(void) 192 { 193 gic_init_per_cpu(); 194 195 stm32mp_register_online_cpu(); 196 } 197 198 #ifdef CFG_STM32MP15 199 /* 200 * This concerns OP-TEE pager for STM32MP1 to use secure internal 201 * RAMs to execute. TZSRAM refers the TZSRAM_BASE/TZSRAM_SIZE 202 * used in boot.c to locate secure unpaged memory. 203 * 204 * STM32MP15 variants embed 640kB of contiguous securable SRAMs 205 * 206 * +--------------+ <-- SYSRAM_BASE 207 * | | lower part can be assigned to secure world 208 * | SYSRAM 256kB | 4kB granule boundary 209 * | | upper part can be assigned to secure world 210 * +--------------+ <-- SRAM1_BASE (= SYSRAM_BASE + SYSRAM_SIZE) 211 | | full range assigned to non-secure world or 212 * | SRAM1 128kB | to secure world, or to- Cortex-M4 exclusive access 213 * +--------------+ <-- SRAM2_BASE (= SRAM1_BASE + SRAM1_SIZE) 214 | | full range assigned to non-secure world or 215 * | SRAM2 128kB | to secure world, or to- Cortex-M4 exclusive access 216 * +--------------+ <-- SRAM3_BASE (= SRAM2_BASE + SRAM2_SIZE) 217 | | full range assigned to non-secure world or 218 * | SRAM3 64kB | to secure world, or to- Cortex-M4 exclusive access 219 * +--------------+ <-- SRAM4_BASE (= SRAM3_BASE + SRAM3_SIZE) 220 | | full range assigned to non-secure world or 221 * | SRAM4 64kB | to secure world, or to- Cortex-M4 exclusive access 222 * +--------------+ <-- SRAM4_BASE + SRAM4_SIZE 223 * 224 * If SRAMx memories are not used for the companion Cortex-M4 225 * processor, OP-TEE can use this memory. 226 * 227 * SYSRAM configuration for secure/non-secure boundaries requires the 228 * secure SYSRAM memory to start at the SYSRAM physical base address and grow 229 * from there while the non-secure SYSRAM range lies at SYSRAM end addresses 230 * with a 4KB page granule. 231 * 232 * SRAM1, SRAM2, SRAM3 and SRAM4 are independently assigned to secure world, 233 * to non-secure world or possibly to Cortex-M4 exclusive access. Each 234 * assignment covers the full related SRAMx memory range. 235 * 236 * Using non-secure SYSRAM or one of the SRAMx for SCMI message communication 237 * can be done using CFG_STM32MP1_SCMI_SHM_BASE/CFG_STM32MP1_SCMI_SHM_SIZE. 238 * This imposes related memory area is assigned to non-secure world. 239 240 * Using secure internal memories (SYSRAM and/or some SRAMx) with STM32MP15 241 * shall meet this constraints known the TZSRAM physical memory range shall 242 * be contiguous. 243 */ 244 245 #define SYSRAM_END (SYSRAM_BASE + SYSRAM_SIZE) 246 #define SYSRAM_SEC_END (SYSRAM_BASE + SYSRAM_SEC_SIZE) 247 #define SRAMS_END (SRAM4_BASE + SRAM4_SIZE) 248 #define SRAMS_START SRAM1_BASE 249 #define TZSRAM_END (CFG_TZSRAM_START + CFG_TZSRAM_SIZE) 250 251 #define TZSRAM_FITS_IN_SYSRAM_SEC ((CFG_TZSRAM_START >= SYSRAM_BASE) && \ 252 (TZSRAM_END <= SYSRAM_SEC_END)) 253 254 #define TZSRAM_FITS_IN_SYSRAM_AND_SRAMS ((CFG_TZSRAM_START >= SYSRAM_BASE) && \ 255 (CFG_TZSRAM_START < SYSRAM_END) && \ 256 (TZSRAM_END > SYSRAM_END) && \ 257 (TZSRAM_END <= SRAMS_END) && \ 258 (SYSRAM_SIZE == SYSRAM_SEC_SIZE)) 259 260 #define TZSRAM_FITS_IN_SRAMS ((CFG_TZSRAM_START >= SRAMS_START) && \ 261 (CFG_TZSRAM_START < SRAMS_END) && \ 262 (TZSRAM_END <= SRAMS_END)) 263 264 #define TZSRAM_IS_IN_DRAM (CFG_TZSRAM_START >= CFG_DRAM_BASE) 265 266 #ifdef CFG_WITH_PAGER 267 /* 268 * At build time, we enforce that, when pager is used, 269 * either TZSRAM fully fits inside SYSRAM secure address range, 270 * or TZSRAM fully fits inside the full SYSRAM and spread inside SRAMx orderly, 271 * or TZSRAM fully fits some inside SRAMs address range, 272 * or TZSRAM is in DDR for debug and test purpose. 273 */ 274 static_assert(TZSRAM_FITS_IN_SYSRAM_SEC || TZSRAM_FITS_IN_SYSRAM_AND_SRAMS || 275 TZSRAM_FITS_IN_SRAMS || TZSRAM_IS_IN_DRAM); 276 #endif /* CFG_WITH_PAGER */ 277 #endif /* CFG_STM32MP15 */ 278 279 static TEE_Result secure_pager_ram(struct dt_driver_provider *fw_provider, 280 unsigned int decprot_id, 281 paddr_t base, size_t secure_size) 282 { 283 /* Lock firewall configuration for secure internal RAMs used by pager */ 284 uint32_t query_arg = DECPROT(decprot_id, DECPROT_S_RW, DECPROT_LOCK); 285 struct firewall_query fw_query = { 286 .ctrl = dt_driver_provider_priv_data(fw_provider), 287 .args = &query_arg, 288 .arg_count = 1, 289 }; 290 TEE_Result res = TEE_ERROR_GENERIC; 291 bool is_pager_ram = false; 292 293 #if defined(CFG_WITH_PAGER) 294 is_pager_ram = core_is_buffer_intersect(CFG_TZSRAM_START, 295 CFG_TZSRAM_SIZE, 296 base, secure_size); 297 #endif 298 if (!is_pager_ram) 299 return TEE_SUCCESS; 300 301 res = firewall_set_memory_configuration(&fw_query, base, secure_size); 302 if (res) 303 EMSG("Failed to configure secure SRAM %#"PRIxPA"..%#"PRIxPA, 304 base, base + secure_size); 305 306 return res; 307 } 308 309 static TEE_Result non_secure_scmi_ram(struct dt_driver_provider *fw_provider, 310 unsigned int decprot_id, 311 paddr_t base, size_t size) 312 { 313 /* Do not lock firewall configuration for non-secure internal RAMs */ 314 uint32_t query_arg = DECPROT(decprot_id, DECPROT_NS_RW, DECPROT_UNLOCK); 315 struct firewall_query fw_query = { 316 .ctrl = dt_driver_provider_priv_data(fw_provider), 317 .args = &query_arg, 318 .arg_count = 1, 319 }; 320 TEE_Result res = TEE_ERROR_GENERIC; 321 322 if (!core_is_buffer_intersect(CFG_STM32MP1_SCMI_SHM_BASE, 323 CFG_STM32MP1_SCMI_SHM_SIZE, 324 base, size)) 325 return TEE_SUCCESS; 326 327 res = firewall_set_memory_configuration(&fw_query, base, size); 328 if (res) 329 EMSG("Failed to configure non-secure SRAM %#"PRIxPA"..%#"PRIxPA, 330 base, base + size); 331 332 return res; 333 } 334 335 /* At run time we enforce that SRAM1 to SRAM4 are properly assigned if used */ 336 static void configure_srams(struct dt_driver_provider *fw_provider) 337 { 338 bool error = false; 339 340 if (IS_ENABLED(CFG_WITH_PAGER)) { 341 if (secure_pager_ram(fw_provider, STM32MP1_ETZPC_SRAM1_ID, 342 SRAM1_BASE, SRAM1_SIZE)) 343 error = true; 344 345 if (secure_pager_ram(fw_provider, STM32MP1_ETZPC_SRAM2_ID, 346 SRAM2_BASE, SRAM2_SIZE)) 347 error = true; 348 349 if (secure_pager_ram(fw_provider, STM32MP1_ETZPC_SRAM3_ID, 350 SRAM3_BASE, SRAM3_SIZE)) 351 error = true; 352 353 #if defined(CFG_STM32MP15) 354 if (secure_pager_ram(fw_provider, STM32MP1_ETZPC_SRAM4_ID, 355 SRAM4_BASE, SRAM4_SIZE)) 356 error = true; 357 #endif 358 } 359 if (CFG_STM32MP1_SCMI_SHM_BASE) { 360 if (non_secure_scmi_ram(fw_provider, STM32MP1_ETZPC_SRAM1_ID, 361 SRAM1_BASE, SRAM1_SIZE)) 362 error = true; 363 364 if (non_secure_scmi_ram(fw_provider, STM32MP1_ETZPC_SRAM2_ID, 365 SRAM2_BASE, SRAM2_SIZE)) 366 error = true; 367 368 if (non_secure_scmi_ram(fw_provider, STM32MP1_ETZPC_SRAM3_ID, 369 SRAM3_BASE, SRAM3_SIZE)) 370 error = true; 371 372 #if defined(CFG_STM32MP15) 373 if (non_secure_scmi_ram(fw_provider, STM32MP1_ETZPC_SRAM4_ID, 374 SRAM4_BASE, SRAM4_SIZE)) 375 error = true; 376 #endif 377 } 378 379 if (error) 380 panic(); 381 } 382 383 static void configure_sysram(struct dt_driver_provider *fw_provider) 384 { 385 uint32_t query_arg = DECPROT(ETZPC_TZMA1_ID, DECPROT_S_RW, 386 DECPROT_UNLOCK); 387 struct firewall_query firewall = { 388 .ctrl = dt_driver_provider_priv_data(fw_provider), 389 .args = &query_arg, 390 .arg_count = 1, 391 }; 392 TEE_Result res = TEE_ERROR_GENERIC; 393 394 res = firewall_set_memory_configuration(&firewall, SYSRAM_BASE, 395 SYSRAM_SEC_SIZE); 396 if (res) 397 panic("Unable to secure SYSRAM"); 398 399 if (SYSRAM_SIZE > SYSRAM_SEC_SIZE) { 400 size_t nsec_size = SYSRAM_SIZE - SYSRAM_SEC_SIZE; 401 paddr_t nsec_start = SYSRAM_BASE + SYSRAM_SEC_SIZE; 402 uint8_t *va = phys_to_virt(nsec_start, MEM_AREA_IO_NSEC, 403 nsec_size); 404 405 IMSG("Non-secure SYSRAM [%p %p]", va, va + nsec_size - 1); 406 407 /* Clear content from the non-secure part */ 408 memset(va, 0, nsec_size); 409 } 410 } 411 412 static TEE_Result init_late_stm32mp1_drivers(void) 413 { 414 uint32_t __maybe_unused state = 0; 415 416 /* Configure SYSRAM and SRAMx secure hardening */ 417 if (IS_ENABLED(CFG_STM32_ETZPC)) { 418 struct dt_driver_provider *prov = NULL; 419 int node = 0; 420 421 node = fdt_node_offset_by_compatible(get_embedded_dt(), -1, 422 "st,stm32-etzpc"); 423 if (node < 0) 424 panic("Could not get ETZPC node"); 425 426 prov = dt_driver_get_provider_by_node(node, DT_DRIVER_FIREWALL); 427 assert(prov); 428 429 configure_sysram(prov); 430 configure_srams(prov); 431 } 432 433 #ifdef CFG_STM32MP15 434 /* Device in Secure Closed state require RCC secure hardening */ 435 if (stm32_bsec_get_state(&state)) 436 panic(); 437 if (state == BSEC_STATE_SEC_CLOSED && !stm32_rcc_is_secure()) 438 panic("Closed device mandates secure RCC"); 439 #endif 440 441 return TEE_SUCCESS; 442 } 443 444 driver_init_late(init_late_stm32mp1_drivers); 445 446 vaddr_t stm32_rcc_base(void) 447 { 448 static struct io_pa_va base = { .pa = RCC_BASE }; 449 450 return io_pa_or_va_secure(&base, 1); 451 } 452 453 vaddr_t get_gicd_base(void) 454 { 455 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 456 457 return io_pa_or_va_secure(&base, 1); 458 } 459 460 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 461 { 462 cfg->base = BSEC_BASE; 463 cfg->upper_start = STM32MP1_UPPER_OTP_START; 464 cfg->max_id = STM32MP1_OTP_MAX_ID; 465 } 466 467 bool __weak stm32mp_with_pmic(void) 468 { 469 return false; 470 } 471 472 uint32_t may_spin_lock(unsigned int *lock) 473 { 474 if (!lock || !cpu_mmu_enabled()) 475 return 0; 476 477 return cpu_spin_lock_xsave(lock); 478 } 479 480 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 481 { 482 if (!lock || !cpu_mmu_enabled()) 483 return; 484 485 cpu_spin_unlock_xrestore(lock, exceptions); 486 } 487 488 static vaddr_t stm32_tamp_base(void) 489 { 490 static struct io_pa_va base = { .pa = TAMP_BASE }; 491 492 return io_pa_or_va_secure(&base, 1); 493 } 494 495 static vaddr_t bkpreg_base(void) 496 { 497 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 498 } 499 500 vaddr_t stm32mp_bkpreg(unsigned int idx) 501 { 502 return bkpreg_base() + (idx * sizeof(uint32_t)); 503 } 504 505 static bool __maybe_unused bank_is_valid(unsigned int bank) 506 { 507 if (IS_ENABLED(CFG_STM32MP15)) 508 return bank == GPIO_BANK_Z || bank <= GPIO_BANK_K; 509 510 if (IS_ENABLED(CFG_STM32MP13)) 511 return bank <= GPIO_BANK_I; 512 513 panic(); 514 } 515 516 #ifdef CFG_STM32_DEBUG_ACCESS 517 static TEE_Result init_debug(void) 518 { 519 TEE_Result res = TEE_SUCCESS; 520 uint32_t conf = stm32_bsec_read_debug_conf(); 521 struct clk *dbg_clk = stm32mp_rcc_clock_id_to_clk(CK_DBG); 522 uint32_t state = 0; 523 524 res = stm32_bsec_get_state(&state); 525 if (res) 526 return res; 527 528 if (state != BSEC_STATE_SEC_CLOSED && conf) { 529 if (IS_ENABLED(CFG_INSECURE)) 530 IMSG("WARNING: All debug accesses are allowed"); 531 532 res = stm32_bsec_write_debug_conf(conf | BSEC_DEBUG_ALL); 533 if (res) 534 return res; 535 536 /* 537 * Enable DBG clock as used to access coprocessor 538 * debug registers 539 */ 540 clk_enable(dbg_clk); 541 } 542 543 return TEE_SUCCESS; 544 } 545 early_init_late(init_debug); 546 #endif /* CFG_STM32_DEBUG_ACCESS */ 547 548 /* Some generic resources need to be unpaged */ 549 DECLARE_KEEP_PAGER(pinctrl_apply_state); 550 551 bool stm32mp_allow_probe_shared_device(const void *fdt, int node) 552 { 553 static int uart_console_node = -1; 554 const char *compat = NULL; 555 static bool once; 556 557 if (IS_ENABLED(CFG_STM32_ALLOW_UNSAFE_PROBE)) 558 return true; 559 560 if (!once) { 561 get_console_node_from_dt((void *)fdt, &uart_console_node, 562 NULL, NULL); 563 once = true; 564 } 565 566 compat = fdt_stringlist_get(fdt, node, "compatible", 0, NULL); 567 568 /* 569 * Allow OP-TEE console and MP15 I2C and RNG to be shared 570 * with non-secure world. 571 */ 572 if (node == uart_console_node || 573 !strcmp(compat, "st,stm32mp15-i2c-non-secure") || 574 (!strcmp(compat, "st,stm32-rng") && 575 IS_ENABLED(CFG_WITH_SOFTWARE_PRNG))) 576 return true; 577 578 return false; 579 } 580 581 #if defined(CFG_STM32MP15) && defined(CFG_WITH_PAGER) 582 paddr_t stm32mp1_pa_or_sram_alias_pa(paddr_t pa) 583 { 584 /* 585 * OP-TEE uses the alias physical addresses of SRAM1/2/3/4, 586 * not the standard physical addresses. This choice was initially 587 * driven by pager that needs physically contiguous memories 588 * for internal secure memories. 589 */ 590 if (core_is_buffer_inside(pa, 1, SRAM1_ALT_BASE, SRAM1_SIZE)) 591 pa += SRAM1_BASE - SRAM1_ALT_BASE; 592 else if (core_is_buffer_inside(pa, 1, SRAM2_ALT_BASE, SRAM2_SIZE)) 593 pa += SRAM2_BASE - SRAM2_ALT_BASE; 594 else if (core_is_buffer_inside(pa, 1, SRAM3_ALT_BASE, SRAM3_SIZE)) 595 pa += SRAM3_BASE - SRAM3_ALT_BASE; 596 else if (core_is_buffer_inside(pa, 1, SRAM4_ALT_BASE, SRAM4_SIZE)) 597 pa += SRAM4_BASE - SRAM4_ALT_BASE; 598 599 return pa; 600 } 601 602 bool stm32mp1_ram_intersect_pager_ram(paddr_t base, size_t size) 603 { 604 base = stm32mp1_pa_or_sram_alias_pa(base); 605 606 return core_is_buffer_intersect(base, size, CFG_TZSRAM_START, 607 CFG_TZSRAM_SIZE); 608 } 609 #endif 610 611 static TEE_Result get_chip_dev_id(uint32_t *dev_id) 612 { 613 #ifdef CFG_STM32MP13 614 *dev_id = stm32mp_syscfg_get_chip_dev_id(); 615 return TEE_SUCCESS; 616 #else /* assume CFG_STM32MP15 */ 617 return stm32mp1_dbgmcu_get_chip_dev_id(dev_id); 618 #endif 619 } 620 621 static TEE_Result get_part_number(uint32_t *part_nb) 622 { 623 static uint32_t part_number; 624 uint32_t dev_id = 0; 625 uint32_t otp = 0; 626 size_t bit_len = 0; 627 TEE_Result res = TEE_ERROR_GENERIC; 628 629 assert(part_nb); 630 631 if (part_number) { 632 *part_nb = part_number; 633 return TEE_SUCCESS; 634 } 635 636 res = get_chip_dev_id(&dev_id); 637 if (res) 638 return res; 639 640 res = stm32_bsec_find_otp_in_nvmem_layout("part_number_otp", 641 &otp, NULL, &bit_len); 642 if (res) 643 return res; 644 645 res = stm32_bsec_read_otp(&part_number, otp); 646 if (res) 647 return res; 648 649 assert(bit_len < 16); 650 part_number = (part_number & GENMASK_32(bit_len, 0)) | 651 SHIFT_U32(dev_id, 16); 652 653 *part_nb = part_number; 654 655 return TEE_SUCCESS; 656 } 657 658 bool stm32mp_supports_cpu_opp(uint32_t opp_id) 659 { 660 uint32_t part_number = 0; 661 uint32_t id = 0; 662 663 if (get_part_number(&part_number)) { 664 DMSG("Cannot get part number"); 665 panic(); 666 } 667 668 switch (part_number) { 669 case STM32MP135F_PART_NB: 670 case STM32MP135D_PART_NB: 671 case STM32MP133F_PART_NB: 672 case STM32MP133D_PART_NB: 673 case STM32MP131F_PART_NB: 674 case STM32MP131D_PART_NB: 675 case STM32MP157F_PART_NB: 676 case STM32MP157D_PART_NB: 677 case STM32MP153F_PART_NB: 678 case STM32MP153D_PART_NB: 679 case STM32MP151F_PART_NB: 680 case STM32MP151D_PART_NB: 681 id = BIT(1); 682 break; 683 default: 684 id = BIT(0); 685 break; 686 } 687 688 return opp_id & id; 689 } 690 691 bool stm32mp_supports_hw_cryp(void) 692 { 693 uint32_t part_number = 0; 694 695 if (!IS_ENABLED(CFG_STM32_CRYP)) 696 return false; 697 698 if (get_part_number(&part_number)) { 699 DMSG("Cannot get part number"); 700 panic(); 701 } 702 703 switch (part_number) { 704 case STM32MP135F_PART_NB: 705 case STM32MP135C_PART_NB: 706 case STM32MP133F_PART_NB: 707 case STM32MP133C_PART_NB: 708 case STM32MP131F_PART_NB: 709 case STM32MP131C_PART_NB: 710 return true; 711 case STM32MP157F_PART_NB: 712 case STM32MP157C_PART_NB: 713 case STM32MP153F_PART_NB: 714 case STM32MP153C_PART_NB: 715 case STM32MP151F_PART_NB: 716 case STM32MP151C_PART_NB: 717 return true; 718 default: 719 return false; 720 } 721 } 722 723 bool stm32mp_supports_second_core(void) 724 { 725 uint32_t part_number = 0; 726 727 if (CFG_TEE_CORE_NB_CORE == 1) 728 return false; 729 730 if (get_part_number(&part_number)) { 731 DMSG("Cannot get part number"); 732 panic(); 733 } 734 735 switch (part_number) { 736 case STM32MP151F_PART_NB: 737 case STM32MP151D_PART_NB: 738 case STM32MP151C_PART_NB: 739 case STM32MP151A_PART_NB: 740 return false; 741 default: 742 return true; 743 } 744 } 745