1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/stm32_etzpc.h> 12 #include <drivers/stm32mp1_etzpc.h> 13 #include <drivers/stm32_uart.h> 14 #include <dt-bindings/clock/stm32mp1-clks.h> 15 #include <kernel/boot.h> 16 #include <kernel/dt.h> 17 #include <kernel/interrupt.h> 18 #include <kernel/misc.h> 19 #include <kernel/panic.h> 20 #include <kernel/spinlock.h> 21 #include <mm/core_memprot.h> 22 #include <platform_config.h> 23 #include <sm/psci.h> 24 #include <stm32_util.h> 25 #include <trace.h> 26 27 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB1_BASE, APB1_SIZE); 28 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB2_BASE, APB2_SIZE); 29 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB3_BASE, APB3_SIZE); 30 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB4_BASE, APB4_SIZE); 31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB5_BASE, APB5_SIZE); 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB4_BASE, AHB4_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB5_BASE, AHB5_SIZE); 34 35 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB3_BASE, APB4_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB5_BASE, APB5_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB4_BASE, AHB4_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB5_BASE, AHB5_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 40 41 register_ddr(DDR_BASE, CFG_DRAM_SIZE); 42 43 #define _ID2STR(id) (#id) 44 #define ID2STR(id) _ID2STR(id) 45 46 static TEE_Result platform_banner(void) 47 { 48 #ifdef CFG_EMBED_DTB 49 IMSG("Platform stm32mp1: flavor %s - DT %s", 50 ID2STR(PLATFORM_FLAVOR), 51 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 52 #else 53 IMSG("Platform stm32mp1: flavor %s - no device tree", 54 ID2STR(PLATFORM_FLAVOR)); 55 #endif 56 57 return TEE_SUCCESS; 58 } 59 service_init(platform_banner); 60 61 /* 62 * Console 63 * 64 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 65 * trace console. Value 0 disables the early console. 66 * 67 * We cannot use the generic serial_console support since probing 68 * the console requires the platform clock driver to be already 69 * up and ready which is done only once service_init are completed. 70 */ 71 static struct stm32_uart_pdata console_data; 72 73 void console_init(void) 74 { 75 /* Early console initialization before MMU setup */ 76 struct uart { 77 paddr_t pa; 78 bool secure; 79 } uarts[] = { 80 [0] = { .pa = 0 }, 81 [1] = { .pa = USART1_BASE, .secure = true, }, 82 [2] = { .pa = USART2_BASE, .secure = false, }, 83 [3] = { .pa = USART3_BASE, .secure = false, }, 84 [4] = { .pa = UART4_BASE, .secure = false, }, 85 [5] = { .pa = UART5_BASE, .secure = false, }, 86 [6] = { .pa = USART6_BASE, .secure = false, }, 87 [7] = { .pa = UART7_BASE, .secure = false, }, 88 [8] = { .pa = UART8_BASE, .secure = false, }, 89 }; 90 91 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 92 93 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 94 return; 95 96 /* No clock yet bound to the UART console */ 97 console_data.clock = NULL; 98 99 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 100 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 101 102 register_serial_console(&console_data.chip); 103 104 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 105 } 106 107 #ifdef CFG_EMBED_DTB 108 static TEE_Result init_console_from_dt(void) 109 { 110 struct stm32_uart_pdata *pd = NULL; 111 void *fdt = NULL; 112 int node = 0; 113 TEE_Result res = TEE_ERROR_GENERIC; 114 115 fdt = get_embedded_dt(); 116 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 117 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 118 fdt = get_external_dt(); 119 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 120 if (res == TEE_ERROR_ITEM_NOT_FOUND) 121 return TEE_SUCCESS; 122 if (res != TEE_SUCCESS) 123 return res; 124 } 125 126 pd = stm32_uart_init_from_dt_node(fdt, node); 127 if (!pd) { 128 IMSG("DTB disables console"); 129 register_serial_console(NULL); 130 return TEE_SUCCESS; 131 } 132 133 /* Replace early console with the new one */ 134 console_flush(); 135 console_data = *pd; 136 free(pd); 137 register_serial_console(&console_data.chip); 138 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 139 140 return TEE_SUCCESS; 141 } 142 143 /* Probe console from DT once clock inits (service init level) are completed */ 144 service_init_late(init_console_from_dt); 145 #endif 146 147 /* 148 * GIC init, used also for primary/secondary boot core wake completion 149 */ 150 static struct gic_data gic_data; 151 152 void itr_core_handler(void) 153 { 154 gic_it_handle(&gic_data); 155 } 156 157 void main_init_gic(void) 158 { 159 assert(cpu_mmu_enabled()); 160 161 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 162 itr_init(&gic_data.chip); 163 164 stm32mp_register_online_cpu(); 165 } 166 167 void main_secondary_init_gic(void) 168 { 169 gic_cpu_init(&gic_data); 170 171 stm32mp_register_online_cpu(); 172 } 173 174 static TEE_Result init_stm32mp1_drivers(void) 175 { 176 /* Without secure DTB support, some drivers must be inited */ 177 if (!IS_ENABLED(CFG_EMBED_DTB)) 178 stm32_etzpc_init(ETZPC_BASE); 179 180 /* Secure internal memories for the platform, once ETZPC is ready */ 181 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 182 etzpc_lock_tzma(0); 183 184 COMPILE_TIME_ASSERT(((SYSRAM_BASE + SYSRAM_SIZE) <= CFG_TZSRAM_START) || 185 ((SYSRAM_BASE <= CFG_TZSRAM_START) && 186 (SYSRAM_SEC_SIZE >= CFG_TZSRAM_SIZE))); 187 188 etzpc_configure_tzma(1, SYSRAM_SEC_SIZE >> SMALL_PAGE_SHIFT); 189 etzpc_lock_tzma(1); 190 191 return TEE_SUCCESS; 192 } 193 service_init_late(init_stm32mp1_drivers); 194 195 vaddr_t get_gicc_base(void) 196 { 197 struct io_pa_va base = { .pa = GIC_BASE + GICC_OFFSET }; 198 199 return io_pa_or_va_secure(&base, 1); 200 } 201 202 vaddr_t get_gicd_base(void) 203 { 204 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 205 206 return io_pa_or_va_secure(&base, 1); 207 } 208 209 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 210 { 211 cfg->base = BSEC_BASE; 212 cfg->upper_start = STM32MP1_UPPER_OTP_START; 213 cfg->max_id = STM32MP1_OTP_MAX_ID; 214 } 215 216 bool stm32mp_is_closed_device(void) 217 { 218 uint32_t otp = 0; 219 TEE_Result result = TEE_ERROR_GENERIC; 220 221 /* Non closed_device platform expects fuse well programmed to 0 */ 222 result = stm32_bsec_shadow_read_otp(&otp, DATA0_OTP); 223 if (!result && !(otp & BIT(DATA0_OTP_SECURED_POS))) 224 return false; 225 226 return true; 227 } 228 229 bool __weak stm32mp_with_pmic(void) 230 { 231 return false; 232 } 233 234 uint32_t may_spin_lock(unsigned int *lock) 235 { 236 if (!lock || !cpu_mmu_enabled()) 237 return 0; 238 239 return cpu_spin_lock_xsave(lock); 240 } 241 242 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 243 { 244 if (!lock || !cpu_mmu_enabled()) 245 return; 246 247 cpu_spin_unlock_xrestore(lock, exceptions); 248 } 249 250 static vaddr_t stm32_tamp_base(void) 251 { 252 static struct io_pa_va base = { .pa = TAMP_BASE }; 253 254 return io_pa_or_va_secure(&base, 1); 255 } 256 257 static vaddr_t bkpreg_base(void) 258 { 259 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 260 } 261 262 vaddr_t stm32mp_bkpreg(unsigned int idx) 263 { 264 return bkpreg_base() + (idx * sizeof(uint32_t)); 265 } 266 267 #ifdef CFG_STM32_GPIO 268 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 269 { 270 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 271 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 272 273 /* Get secure mapping address for GPIOZ */ 274 if (bank == GPIO_BANK_Z) 275 return io_pa_or_va_secure(&gpioz_base, GPIO_BANK_OFFSET); 276 277 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 278 assert(bank <= GPIO_BANK_K); 279 280 return io_pa_or_va_nsec(&gpios_nsec_base, 281 (bank + 1) * GPIO_BANK_OFFSET) + 282 (bank * GPIO_BANK_OFFSET); 283 } 284 285 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 286 { 287 if (bank == GPIO_BANK_Z) 288 return 0; 289 290 assert(bank <= GPIO_BANK_K); 291 return bank * GPIO_BANK_OFFSET; 292 } 293 294 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 295 { 296 if (bank == GPIO_BANK_Z) 297 return GPIOZ; 298 299 assert(bank <= GPIO_BANK_K); 300 return GPIOA + bank; 301 } 302 303 #ifdef CFG_DRIVERS_CLK 304 struct clk *stm32_get_gpio_bank_clk(unsigned int bank) 305 { 306 if (bank == GPIO_BANK_Z) 307 return stm32mp_rcc_clock_id_to_clk(GPIOZ); 308 309 assert(bank <= GPIO_BANK_K); 310 return stm32mp_rcc_clock_id_to_clk(GPIOA + bank); 311 } 312 #endif 313 #endif /* CFG_STM32_GPIO */ 314