1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/stm32_etzpc.h> 12 #include <drivers/stm32_iwdg.h> 13 #include <drivers/stm32_tamp.h> 14 #include <drivers/stm32_uart.h> 15 #include <drivers/stm32mp1_etzpc.h> 16 #include <dt-bindings/clock/stm32mp1-clks.h> 17 #include <kernel/boot.h> 18 #include <kernel/dt.h> 19 #include <kernel/interrupt.h> 20 #include <kernel/misc.h> 21 #include <kernel/panic.h> 22 #include <kernel/spinlock.h> 23 #include <mm/core_memprot.h> 24 #include <platform_config.h> 25 #include <sm/psci.h> 26 #include <stm32_util.h> 27 #include <trace.h> 28 29 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB1_BASE, APB1_SIZE); 30 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB2_BASE, APB2_SIZE); 31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB3_BASE, APB3_SIZE); 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB4_BASE, APB4_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB5_BASE, APB5_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB4_BASE, AHB4_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB5_BASE, AHB5_SIZE); 36 37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB3_BASE, APB3_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB4_BASE, APB4_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB5_BASE, APB5_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB4_BASE, AHB4_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB5_BASE, AHB5_SIZE); 42 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 43 44 register_ddr(DDR_BASE, CFG_DRAM_SIZE); 45 46 #define _ID2STR(id) (#id) 47 #define ID2STR(id) _ID2STR(id) 48 49 static TEE_Result platform_banner(void) 50 { 51 #ifdef CFG_EMBED_DTB 52 IMSG("Platform stm32mp1: flavor %s - DT %s", 53 ID2STR(PLATFORM_FLAVOR), 54 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 55 #else 56 IMSG("Platform stm32mp1: flavor %s - no device tree", 57 ID2STR(PLATFORM_FLAVOR)); 58 #endif 59 60 return TEE_SUCCESS; 61 } 62 service_init(platform_banner); 63 64 /* 65 * Console 66 * 67 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 68 * trace console. Value 0 disables the early console. 69 * 70 * We cannot use the generic serial_console support since probing 71 * the console requires the platform clock driver to be already 72 * up and ready which is done only once service_init are completed. 73 */ 74 static struct stm32_uart_pdata console_data; 75 76 void console_init(void) 77 { 78 /* Early console initialization before MMU setup */ 79 struct uart { 80 paddr_t pa; 81 bool secure; 82 } uarts[] = { 83 [0] = { .pa = 0 }, 84 [1] = { .pa = USART1_BASE, .secure = true, }, 85 [2] = { .pa = USART2_BASE, .secure = false, }, 86 [3] = { .pa = USART3_BASE, .secure = false, }, 87 [4] = { .pa = UART4_BASE, .secure = false, }, 88 [5] = { .pa = UART5_BASE, .secure = false, }, 89 [6] = { .pa = USART6_BASE, .secure = false, }, 90 [7] = { .pa = UART7_BASE, .secure = false, }, 91 [8] = { .pa = UART8_BASE, .secure = false, }, 92 }; 93 94 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 95 96 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 97 return; 98 99 /* No clock yet bound to the UART console */ 100 console_data.clock = NULL; 101 102 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 103 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 104 105 register_serial_console(&console_data.chip); 106 107 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 108 } 109 110 #ifdef CFG_EMBED_DTB 111 static TEE_Result init_console_from_dt(void) 112 { 113 struct stm32_uart_pdata *pd = NULL; 114 void *fdt = NULL; 115 int node = 0; 116 TEE_Result res = TEE_ERROR_GENERIC; 117 118 fdt = get_embedded_dt(); 119 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 120 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 121 fdt = get_external_dt(); 122 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 123 if (res == TEE_ERROR_ITEM_NOT_FOUND) 124 return TEE_SUCCESS; 125 if (res != TEE_SUCCESS) 126 return res; 127 } 128 129 pd = stm32_uart_init_from_dt_node(fdt, node); 130 if (!pd) { 131 IMSG("DTB disables console"); 132 register_serial_console(NULL); 133 return TEE_SUCCESS; 134 } 135 136 /* Replace early console with the new one */ 137 console_flush(); 138 console_data = *pd; 139 free(pd); 140 register_serial_console(&console_data.chip); 141 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 142 143 return TEE_SUCCESS; 144 } 145 146 /* Probe console from DT once clock inits (service init level) are completed */ 147 service_init_late(init_console_from_dt); 148 #endif 149 150 /* 151 * GIC init, used also for primary/secondary boot core wake completion 152 */ 153 static struct gic_data gic_data; 154 155 void itr_core_handler(void) 156 { 157 gic_it_handle(&gic_data); 158 } 159 160 void main_init_gic(void) 161 { 162 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 163 itr_init(&gic_data.chip); 164 165 stm32mp_register_online_cpu(); 166 } 167 168 void main_secondary_init_gic(void) 169 { 170 gic_cpu_init(&gic_data); 171 172 stm32mp_register_online_cpu(); 173 } 174 175 static TEE_Result init_stm32mp1_drivers(void) 176 { 177 /* Without secure DTB support, some drivers must be inited */ 178 if (!IS_ENABLED(CFG_EMBED_DTB)) 179 stm32_etzpc_init(ETZPC_BASE); 180 181 /* Secure internal memories for the platform, once ETZPC is ready */ 182 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 183 etzpc_lock_tzma(0); 184 185 COMPILE_TIME_ASSERT(((SYSRAM_BASE + SYSRAM_SIZE) <= CFG_TZSRAM_START) || 186 ((SYSRAM_BASE <= CFG_TZSRAM_START) && 187 (SYSRAM_SEC_SIZE >= CFG_TZSRAM_SIZE))); 188 189 etzpc_configure_tzma(1, SYSRAM_SEC_SIZE >> SMALL_PAGE_SHIFT); 190 etzpc_lock_tzma(1); 191 192 return TEE_SUCCESS; 193 } 194 195 service_init_late(init_stm32mp1_drivers); 196 197 static TEE_Result init_late_stm32mp1_drivers(void) 198 { 199 TEE_Result res = TEE_ERROR_GENERIC; 200 201 /* Set access permission to TAM backup registers */ 202 if (IS_ENABLED(CFG_STM32_TAMP)) { 203 struct stm32_bkpregs_conf conf = { 204 .nb_zone1_regs = TAMP_BKP_REGISTER_ZONE1_COUNT, 205 .nb_zone2_regs = TAMP_BKP_REGISTER_ZONE2_COUNT, 206 }; 207 208 res = stm32_tamp_set_secure_bkpregs(&conf); 209 if (res == TEE_ERROR_DEFER_DRIVER_INIT) { 210 /* TAMP driver was not probed if disabled in the DT */ 211 res = TEE_SUCCESS; 212 } 213 if (res) 214 panic(); 215 } 216 217 return TEE_SUCCESS; 218 } 219 220 driver_init_late(init_late_stm32mp1_drivers); 221 222 vaddr_t stm32_rcc_base(void) 223 { 224 static struct io_pa_va base = { .pa = RCC_BASE }; 225 226 return io_pa_or_va_secure(&base, 1); 227 } 228 229 vaddr_t get_gicd_base(void) 230 { 231 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 232 233 return io_pa_or_va_secure(&base, 1); 234 } 235 236 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 237 { 238 cfg->base = BSEC_BASE; 239 cfg->upper_start = STM32MP1_UPPER_OTP_START; 240 cfg->max_id = STM32MP1_OTP_MAX_ID; 241 } 242 243 bool stm32mp_is_closed_device(void) 244 { 245 uint32_t otp = 0; 246 TEE_Result result = TEE_ERROR_GENERIC; 247 248 /* Non closed_device platform expects fuse well programmed to 0 */ 249 result = stm32_bsec_shadow_read_otp(&otp, DATA0_OTP); 250 if (!result && !(otp & BIT(DATA0_OTP_SECURED_POS))) 251 return false; 252 253 return true; 254 } 255 256 bool __weak stm32mp_with_pmic(void) 257 { 258 return false; 259 } 260 261 uint32_t may_spin_lock(unsigned int *lock) 262 { 263 if (!lock || !cpu_mmu_enabled()) 264 return 0; 265 266 return cpu_spin_lock_xsave(lock); 267 } 268 269 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 270 { 271 if (!lock || !cpu_mmu_enabled()) 272 return; 273 274 cpu_spin_unlock_xrestore(lock, exceptions); 275 } 276 277 static vaddr_t stm32_tamp_base(void) 278 { 279 static struct io_pa_va base = { .pa = TAMP_BASE }; 280 281 return io_pa_or_va_secure(&base, 1); 282 } 283 284 static vaddr_t bkpreg_base(void) 285 { 286 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 287 } 288 289 vaddr_t stm32mp_bkpreg(unsigned int idx) 290 { 291 return bkpreg_base() + (idx * sizeof(uint32_t)); 292 } 293 294 #ifdef CFG_STM32_GPIO 295 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 296 { 297 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 298 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 299 300 /* Get secure mapping address for GPIOZ */ 301 if (bank == GPIO_BANK_Z) 302 return io_pa_or_va_secure(&gpioz_base, GPIO_BANK_OFFSET); 303 304 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 305 assert(bank <= GPIO_BANK_K); 306 307 return io_pa_or_va_nsec(&gpios_nsec_base, 308 (bank + 1) * GPIO_BANK_OFFSET) + 309 (bank * GPIO_BANK_OFFSET); 310 } 311 312 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 313 { 314 if (bank == GPIO_BANK_Z) 315 return 0; 316 317 assert(bank <= GPIO_BANK_K); 318 return bank * GPIO_BANK_OFFSET; 319 } 320 321 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 322 { 323 if (bank == GPIO_BANK_Z) 324 return GPIOZ; 325 326 assert(bank <= GPIO_BANK_K); 327 return GPIOA + bank; 328 } 329 330 #ifdef CFG_DRIVERS_CLK 331 struct clk *stm32_get_gpio_bank_clk(unsigned int bank) 332 { 333 if (bank == GPIO_BANK_Z) 334 return stm32mp_rcc_clock_id_to_clk(GPIOZ); 335 336 assert(bank <= GPIO_BANK_K); 337 return stm32mp_rcc_clock_id_to_clk(GPIOA + bank); 338 } 339 #endif 340 #endif /* CFG_STM32_GPIO */ 341 342 #ifdef CFG_STM32_IWDG 343 TEE_Result stm32_get_iwdg_otp_config(paddr_t pbase, 344 struct stm32_iwdg_otp_data *otp_data) 345 { 346 unsigned int idx = 0; 347 uint32_t otp_value = 0; 348 349 switch (pbase) { 350 case IWDG1_BASE: 351 idx = 0; 352 break; 353 case IWDG2_BASE: 354 idx = 1; 355 break; 356 default: 357 panic(); 358 } 359 360 if (stm32_bsec_read_otp(&otp_value, HW2_OTP)) 361 panic(); 362 363 otp_data->hw_enabled = otp_value & 364 BIT(idx + HW2_OTP_IWDG_HW_ENABLE_SHIFT); 365 otp_data->disable_on_stop = otp_value & 366 BIT(idx + HW2_OTP_IWDG_FZ_STOP_SHIFT); 367 otp_data->disable_on_standby = otp_value & 368 BIT(idx + HW2_OTP_IWDG_FZ_STANDBY_SHIFT); 369 370 return TEE_SUCCESS; 371 } 372 #endif /*CFG_STM32_IWDG*/ 373