1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_etzpc.h> 11 #include <drivers/stm32_uart.h> 12 #include <drivers/stm32mp1_etzpc.h> 13 #include <dt-bindings/clock/stm32mp1-clks.h> 14 #include <kernel/generic_boot.h> 15 #include <kernel/dt.h> 16 #include <kernel/misc.h> 17 #include <kernel/panic.h> 18 #include <kernel/pm_stubs.h> 19 #include <kernel/spinlock.h> 20 #include <mm/core_memprot.h> 21 #include <platform_config.h> 22 #include <sm/psci.h> 23 #include <stm32_util.h> 24 #include <tee/entry_std.h> 25 #include <tee/entry_fast.h> 26 #include <trace.h> 27 28 #ifdef CFG_WITH_NSEC_GPIOS 29 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIOS_NSEC_BASE, GPIOS_NSEC_SIZE); 30 #endif 31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C4_BASE, SMALL_PAGE_SIZE); 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C6_BASE, SMALL_PAGE_SIZE); 33 #ifdef CFG_WITH_NSEC_UARTS 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 42 #endif 43 44 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BSEC_BASE, SMALL_PAGE_SIZE); 45 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ETZPC_BASE, SMALL_PAGE_SIZE); 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GPIOZ_BASE, SMALL_PAGE_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C4_BASE, SMALL_PAGE_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C6_BASE, SMALL_PAGE_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG1_BASE, SMALL_PAGE_SIZE); 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 55 56 static void main_fiq(void); 57 58 static const struct thread_handlers handlers = { 59 .std_smc = tee_entry_std, 60 .fast_smc = tee_entry_fast, 61 .nintr = main_fiq, 62 .cpu_on = pm_panic, 63 .cpu_off = pm_panic, 64 .cpu_suspend = pm_panic, 65 .cpu_resume = pm_panic, 66 .system_off = pm_panic, 67 .system_reset = pm_panic, 68 }; 69 70 const struct thread_handlers *generic_boot_get_handlers(void) 71 { 72 return &handlers; 73 } 74 75 #define _ID2STR(id) (#id) 76 #define ID2STR(id) _ID2STR(id) 77 78 static TEE_Result platform_banner(void) 79 { 80 #ifdef CFG_EMBED_DTB 81 IMSG("Platform stm32mp1: flavor %s - DT %s", 82 ID2STR(PLATFORM_FLAVOR), 83 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 84 #else 85 IMSG("Platform stm32mp1: flavor %s - no device tree", 86 ID2STR(PLATFORM_FLAVOR)); 87 #endif 88 89 return TEE_SUCCESS; 90 } 91 service_init(platform_banner); 92 93 /* 94 * Console 95 * 96 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 97 * trace console. Value 0 disables the early console. 98 * 99 * We cannot use the generic serial_console support since probing 100 * the console requires the platform clock driver to be already 101 * up and ready which is done only once service_init are completed. 102 */ 103 static struct stm32_uart_pdata console_data; 104 105 void console_init(void) 106 { 107 /* Early console initialization before MMU setup */ 108 struct uart { 109 paddr_t pa; 110 bool secure; 111 } uarts[] = { 112 [0] = { .pa = 0 }, 113 [1] = { .pa = USART1_BASE, .secure = true, }, 114 [2] = { .pa = USART2_BASE, .secure = false, }, 115 [3] = { .pa = USART3_BASE, .secure = false, }, 116 [4] = { .pa = UART4_BASE, .secure = false, }, 117 [5] = { .pa = UART5_BASE, .secure = false, }, 118 [6] = { .pa = USART6_BASE, .secure = false, }, 119 [7] = { .pa = UART7_BASE, .secure = false, }, 120 [8] = { .pa = UART8_BASE, .secure = false, }, 121 }; 122 123 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 124 assert(!cpu_mmu_enabled()); 125 126 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 127 return; 128 129 /* No clock yet bound to the UART console */ 130 console_data.clock = DT_INFO_INVALID_CLOCK; 131 132 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 133 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 134 135 register_serial_console(&console_data.chip); 136 137 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 138 } 139 140 #ifdef CFG_DT 141 static TEE_Result init_console_from_dt(void) 142 { 143 struct stm32_uart_pdata *pd = NULL; 144 void *fdt = NULL; 145 int node = 0; 146 147 if (get_console_node_from_dt(&fdt, &node, NULL, NULL)) 148 return TEE_SUCCESS; 149 150 pd = stm32_uart_init_from_dt_node(fdt, node); 151 if (!pd) { 152 IMSG("DTB disables console"); 153 register_serial_console(NULL); 154 return TEE_SUCCESS; 155 } 156 157 /* Replace early console with the new one */ 158 console_flush(); 159 console_data = *pd; 160 free(pd); 161 register_serial_console(&console_data.chip); 162 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 163 164 return TEE_SUCCESS; 165 } 166 167 /* Probe console from DT once clock inits (service init level) are completed */ 168 service_init_late(init_console_from_dt); 169 #endif 170 171 /* 172 * GIC init, used also for primary/secondary boot core wake completion 173 */ 174 static struct gic_data gic_data; 175 176 static void main_fiq(void) 177 { 178 gic_it_handle(&gic_data); 179 } 180 181 void main_init_gic(void) 182 { 183 assert(cpu_mmu_enabled()); 184 185 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 186 itr_init(&gic_data.chip); 187 188 stm32mp_register_online_cpu(); 189 } 190 191 void main_secondary_init_gic(void) 192 { 193 gic_cpu_init(&gic_data); 194 195 stm32mp_register_online_cpu(); 196 } 197 198 #ifndef CFG_EMBED_DTB 199 static TEE_Result init_stm32mp1_drivers(void) 200 { 201 /* Without secure DTB support, some drivers must be inited */ 202 stm32_etzpc_init(ETZPC_BASE); 203 204 return TEE_SUCCESS; 205 } 206 driver_init(init_stm32mp1_drivers); 207 #endif /*!CFG_EMBED_DTB*/ 208 209 /* Platform initializations once all drivers are ready */ 210 static TEE_Result init_late_stm32mp1_drivers(void) 211 { 212 /* Secure internal memories for the platform, once ETZPC is ready */ 213 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 214 etzpc_lock_tzma(0); 215 etzpc_configure_tzma(1, ETZPC_TZMA_ALL_SECURE); 216 etzpc_lock_tzma(1); 217 218 /* Static secure DECPROT configuration */ 219 etzpc_configure_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); 220 etzpc_configure_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); 221 etzpc_configure_decprot(STM32MP1_ETZPC_IWDG1_ID, ETZPC_DECPROT_S_RW); 222 etzpc_configure_decprot(STM32MP1_ETZPC_DDRCTRL_ID, ETZPC_DECPROT_S_RW); 223 etzpc_configure_decprot(STM32MP1_ETZPC_DDRPHYC_ID, ETZPC_DECPROT_S_RW); 224 etzpc_lock_decprot(STM32MP1_ETZPC_STGENC_ID); 225 etzpc_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID); 226 etzpc_lock_decprot(STM32MP1_ETZPC_IWDG1_ID); 227 etzpc_lock_decprot(STM32MP1_ETZPC_DDRCTRL_ID); 228 etzpc_lock_decprot(STM32MP1_ETZPC_DDRPHYC_ID); 229 /* Static non-secure DECPROT configuration */ 230 etzpc_configure_decprot(STM32MP1_ETZPC_I2C4_ID, ETZPC_DECPROT_NS_RW); 231 etzpc_configure_decprot(STM32MP1_ETZPC_RNG1_ID, ETZPC_DECPROT_NS_RW); 232 etzpc_configure_decprot(STM32MP1_ETZPC_HASH1_ID, ETZPC_DECPROT_NS_RW); 233 etzpc_configure_decprot(STM32MP1_ETZPC_CRYP1_ID, ETZPC_DECPROT_NS_RW); 234 /* Release few resource to the non-secure world */ 235 etzpc_configure_decprot(STM32MP1_ETZPC_USART1_ID, ETZPC_DECPROT_NS_RW); 236 etzpc_configure_decprot(STM32MP1_ETZPC_SPI6_ID, ETZPC_DECPROT_NS_RW); 237 etzpc_configure_decprot(STM32MP1_ETZPC_I2C6_ID, ETZPC_DECPROT_NS_RW); 238 239 return TEE_SUCCESS; 240 } 241 driver_init_late(init_late_stm32mp1_drivers); 242 243 vaddr_t get_gicc_base(void) 244 { 245 struct io_pa_va base = { .pa = GIC_BASE + GICC_OFFSET }; 246 247 return io_pa_or_va(&base); 248 } 249 250 vaddr_t get_gicd_base(void) 251 { 252 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 253 254 return io_pa_or_va(&base); 255 } 256 257 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 258 { 259 cfg->base = BSEC_BASE; 260 cfg->upper_start = STM32MP1_UPPER_OTP_START; 261 cfg->max_id = STM32MP1_OTP_MAX_ID; 262 cfg->closed_device_id = DATA0_OTP; 263 cfg->closed_device_position = DATA0_OTP_SECURED_POS; 264 } 265 266 uint32_t may_spin_lock(unsigned int *lock) 267 { 268 if (!lock || !cpu_mmu_enabled()) 269 return 0; 270 271 return cpu_spin_lock_xsave(lock); 272 } 273 274 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 275 { 276 if (!lock || !cpu_mmu_enabled()) 277 return; 278 279 cpu_spin_unlock_xrestore(lock, exceptions); 280 } 281 282 static vaddr_t stm32_tamp_base(void) 283 { 284 static struct io_pa_va base = { .pa = TAMP_BASE }; 285 286 return io_pa_or_va(&base); 287 } 288 289 static vaddr_t bkpreg_base(void) 290 { 291 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 292 } 293 294 vaddr_t stm32mp_bkpreg(unsigned int idx) 295 { 296 return bkpreg_base() + (idx * sizeof(uint32_t)); 297 } 298 299 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 300 { 301 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 302 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 303 304 if (bank == GPIO_BANK_Z) 305 return io_pa_or_va(&gpioz_base); 306 307 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 308 assert(bank <= GPIO_BANK_K); 309 310 return io_pa_or_va(&gpios_nsec_base) + (bank * GPIO_BANK_OFFSET); 311 } 312 313 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 314 { 315 if (bank == GPIO_BANK_Z) 316 return 0; 317 318 assert(bank <= GPIO_BANK_K); 319 return bank * GPIO_BANK_OFFSET; 320 } 321 322 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 323 { 324 if (bank == GPIO_BANK_Z) 325 return GPIOZ; 326 327 assert(bank <= GPIO_BANK_K); 328 return GPIOA + bank; 329 } 330