1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2022, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/stm32_etzpc.h> 12 #include <drivers/stm32_gpio.h> 13 #include <drivers/stm32_iwdg.h> 14 #include <drivers/stm32_tamp.h> 15 #include <drivers/stm32_uart.h> 16 #include <drivers/stm32mp1_etzpc.h> 17 #include <drivers/stm32mp_dt_bindings.h> 18 #include <io.h> 19 #include <kernel/boot.h> 20 #include <kernel/dt.h> 21 #include <kernel/misc.h> 22 #include <kernel/panic.h> 23 #include <kernel/spinlock.h> 24 #include <kernel/tee_misc.h> 25 #include <mm/core_memprot.h> 26 #include <platform_config.h> 27 #include <sm/psci.h> 28 #include <stm32_util.h> 29 #include <string.h> 30 #include <trace.h> 31 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB1_BASE, APB1_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB2_BASE, APB2_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB3_BASE, APB3_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB4_BASE, APB4_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB5_BASE, APB5_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB4_BASE, AHB4_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB5_BASE, AHB5_SIZE); 39 40 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB1_BASE, APB1_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB3_BASE, APB3_SIZE); 42 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB4_BASE, APB4_SIZE); 43 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB5_BASE, APB5_SIZE); 44 #ifdef CFG_STM32MP13 45 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB6_BASE, APB6_SIZE); 46 #endif 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB4_BASE, AHB4_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB5_BASE, AHB5_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 50 51 register_ddr(DDR_BASE, CFG_DRAM_SIZE); 52 53 #define _ID2STR(id) (#id) 54 #define ID2STR(id) _ID2STR(id) 55 56 static TEE_Result platform_banner(void) 57 { 58 IMSG("Platform stm32mp1: flavor %s - DT %s", 59 ID2STR(PLATFORM_FLAVOR), 60 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 61 62 return TEE_SUCCESS; 63 } 64 service_init(platform_banner); 65 66 /* 67 * Console 68 * 69 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 70 * trace console. Value 0 disables the early console. 71 * 72 * We cannot use the generic serial_console support since probing 73 * the console requires the platform clock driver to be already 74 * up and ready which is done only once service_init are completed. 75 */ 76 static struct stm32_uart_pdata console_data; 77 78 void console_init(void) 79 { 80 /* Early console initialization before MMU setup */ 81 struct uart { 82 paddr_t pa; 83 bool secure; 84 } uarts[] = { 85 [0] = { .pa = 0 }, 86 [1] = { .pa = USART1_BASE, .secure = true, }, 87 [2] = { .pa = USART2_BASE, .secure = false, }, 88 [3] = { .pa = USART3_BASE, .secure = false, }, 89 [4] = { .pa = UART4_BASE, .secure = false, }, 90 [5] = { .pa = UART5_BASE, .secure = false, }, 91 [6] = { .pa = USART6_BASE, .secure = false, }, 92 [7] = { .pa = UART7_BASE, .secure = false, }, 93 [8] = { .pa = UART8_BASE, .secure = false, }, 94 }; 95 96 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 97 98 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 99 return; 100 101 /* No clock yet bound to the UART console */ 102 console_data.clock = NULL; 103 104 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 105 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 106 107 register_serial_console(&console_data.chip); 108 109 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 110 } 111 112 static TEE_Result init_console_from_dt(void) 113 { 114 struct stm32_uart_pdata *pd = NULL; 115 void *fdt = NULL; 116 int node = 0; 117 TEE_Result res = TEE_ERROR_GENERIC; 118 119 fdt = get_embedded_dt(); 120 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 121 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 122 fdt = get_external_dt(); 123 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 124 if (res == TEE_ERROR_ITEM_NOT_FOUND) 125 return TEE_SUCCESS; 126 if (res != TEE_SUCCESS) 127 return res; 128 } 129 130 pd = stm32_uart_init_from_dt_node(fdt, node); 131 if (!pd) { 132 IMSG("DTB disables console"); 133 register_serial_console(NULL); 134 return TEE_SUCCESS; 135 } 136 137 /* Replace early console with the new one */ 138 console_flush(); 139 console_data = *pd; 140 register_serial_console(&console_data.chip); 141 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 142 free(pd); 143 144 return TEE_SUCCESS; 145 } 146 147 /* Probe console from DT once clock inits (service init level) are completed */ 148 service_init_late(init_console_from_dt); 149 150 /* 151 * GIC init, used also for primary/secondary boot core wake completion 152 */ 153 void main_init_gic(void) 154 { 155 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 156 157 stm32mp_register_online_cpu(); 158 } 159 160 void main_secondary_init_gic(void) 161 { 162 gic_cpu_init(); 163 164 stm32mp_register_online_cpu(); 165 } 166 167 #ifdef CFG_STM32MP13 168 #ifdef CFG_STM32_ETZPC 169 /* Configure ETZPC cell and lock it when resource is secure */ 170 static void config_lock_decprot(uint32_t decprot_id, 171 enum etzpc_decprot_attributes decprot_attr) 172 { 173 etzpc_configure_decprot(decprot_id, decprot_attr); 174 175 if (decprot_attr == ETZPC_DECPROT_S_RW) 176 etzpc_lock_decprot(decprot_id); 177 } 178 179 static TEE_Result set_etzpc_secure_configuration(void) 180 { 181 config_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); 182 config_lock_decprot(STM32MP1_ETZPC_DDRCTRLPHY_ID, 183 ETZPC_DECPROT_NS_R_S_W); 184 185 /* Configure ETZPC with peripheral registering */ 186 config_lock_decprot(STM32MP1_ETZPC_ADC1_ID, ETZPC_DECPROT_NS_RW); 187 config_lock_decprot(STM32MP1_ETZPC_ADC2_ID, ETZPC_DECPROT_NS_RW); 188 config_lock_decprot(STM32MP1_ETZPC_CRYP_ID, ETZPC_DECPROT_NS_RW); 189 config_lock_decprot(STM32MP1_ETZPC_DCMIPP_ID, ETZPC_DECPROT_NS_RW); 190 config_lock_decprot(STM32MP1_ETZPC_ETH1_ID, ETZPC_DECPROT_NS_RW); 191 config_lock_decprot(STM32MP1_ETZPC_ETH2_ID, ETZPC_DECPROT_NS_RW); 192 config_lock_decprot(STM32MP1_ETZPC_FMC_ID, ETZPC_DECPROT_NS_RW); 193 /* HASH is secure */ 194 config_lock_decprot(STM32MP1_ETZPC_HASH_ID, ETZPC_DECPROT_S_RW); 195 config_lock_decprot(STM32MP1_ETZPC_I2C3_ID, ETZPC_DECPROT_NS_RW); 196 /* I2C4 is secure */ 197 config_lock_decprot(STM32MP1_ETZPC_I2C4_ID, ETZPC_DECPROT_S_RW); 198 config_lock_decprot(STM32MP1_ETZPC_I2C5_ID, ETZPC_DECPROT_NS_RW); 199 /* IWDG1 is secure */ 200 config_lock_decprot(STM32MP1_ETZPC_IWDG1_ID, ETZPC_DECPROT_S_RW); 201 config_lock_decprot(STM32MP1_ETZPC_LPTIM2_ID, ETZPC_DECPROT_NS_RW); 202 /* LPTIM3 is secure */ 203 config_lock_decprot(STM32MP1_ETZPC_LPTIM3_ID, ETZPC_DECPROT_S_RW); 204 config_lock_decprot(STM32MP1_ETZPC_LTDC_ID, ETZPC_DECPROT_NS_RW); 205 /* MCE is secure */ 206 config_lock_decprot(STM32MP1_ETZPC_MCE_ID, ETZPC_DECPROT_S_RW); 207 config_lock_decprot(STM32MP1_ETZPC_OTG_ID, ETZPC_DECPROT_NS_RW); 208 /* PKA is secure */ 209 config_lock_decprot(STM32MP1_ETZPC_PKA_ID, ETZPC_DECPROT_S_RW); 210 config_lock_decprot(STM32MP1_ETZPC_QSPI_ID, ETZPC_DECPROT_NS_RW); 211 /* RNG is secure */ 212 config_lock_decprot(STM32MP1_ETZPC_RNG_ID, ETZPC_DECPROT_S_RW); 213 /* SAES is secure */ 214 config_lock_decprot(STM32MP1_ETZPC_SAES_ID, ETZPC_DECPROT_NS_RW); 215 config_lock_decprot(STM32MP1_ETZPC_SDMMC1_ID, ETZPC_DECPROT_NS_RW); 216 config_lock_decprot(STM32MP1_ETZPC_SDMMC2_ID, ETZPC_DECPROT_NS_RW); 217 config_lock_decprot(STM32MP1_ETZPC_SPI4_ID, ETZPC_DECPROT_NS_RW); 218 config_lock_decprot(STM32MP1_ETZPC_SPI5_ID, ETZPC_DECPROT_NS_RW); 219 config_lock_decprot(STM32MP1_ETZPC_SRAM1_ID, ETZPC_DECPROT_NS_RW); 220 config_lock_decprot(STM32MP1_ETZPC_SRAM2_ID, ETZPC_DECPROT_NS_RW); 221 /* SRAM3 is secure */ 222 config_lock_decprot(STM32MP1_ETZPC_SRAM3_ID, ETZPC_DECPROT_S_RW); 223 /* STGENC is secure */ 224 config_lock_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); 225 /* TIM12 is secure */ 226 config_lock_decprot(STM32MP1_ETZPC_TIM12_ID, ETZPC_DECPROT_S_RW); 227 config_lock_decprot(STM32MP1_ETZPC_TIM13_ID, ETZPC_DECPROT_NS_RW); 228 config_lock_decprot(STM32MP1_ETZPC_TIM14_ID, ETZPC_DECPROT_NS_RW); 229 /* TIM15 is secure */ 230 config_lock_decprot(STM32MP1_ETZPC_TIM15_ID, ETZPC_DECPROT_S_RW); 231 config_lock_decprot(STM32MP1_ETZPC_TIM16_ID, ETZPC_DECPROT_NS_RW); 232 config_lock_decprot(STM32MP1_ETZPC_TIM17_ID, ETZPC_DECPROT_NS_RW); 233 config_lock_decprot(STM32MP1_ETZPC_USART1_ID, ETZPC_DECPROT_NS_RW); 234 config_lock_decprot(STM32MP1_ETZPC_USART2_ID, ETZPC_DECPROT_NS_RW); 235 config_lock_decprot(STM32MP1_ETZPC_USBPHYCTRL_ID, ETZPC_DECPROT_NS_RW); 236 config_lock_decprot(STM32MP1_ETZPC_VREFBUF_ID, ETZPC_DECPROT_NS_RW); 237 238 return TEE_SUCCESS; 239 } 240 241 driver_init_late(set_etzpc_secure_configuration); 242 #endif /* CFG_STM32_ETZPC */ 243 #endif /* CFG_STM32MP13 */ 244 245 #ifdef CFG_STM32MP15 246 /* 247 * This concerns OP-TEE pager for STM32MP1 to use secure internal 248 * RAMs to execute. TZSRAM refers the TZSRAM_BASE/TZSRAM_SIZE 249 * used in boot.c to locate secure unpaged memory. 250 * 251 * STM32MP15 variants embed 640kB of contiguous securable SRAMs 252 * 253 * +--------------+ <-- SYSRAM_BASE 254 * | | lower part can be assigned to secure world 255 * | SYSRAM 256kB | 4kB granule boundary 256 * | | upper part can be assigned to secure world 257 * +--------------+ <-- SRAM1_BASE (= SYSRAM_BASE + SYSRAM_SIZE) 258 | | full range assigned to non-secure world or 259 * | SRAM1 128kB | to secure world, or to- Cortex-M4 exclusive access 260 * +--------------+ <-- SRAM2_BASE (= SRAM1_BASE + SRAM1_SIZE) 261 | | full range assigned to non-secure world or 262 * | SRAM2 128kB | to secure world, or to- Cortex-M4 exclusive access 263 * +--------------+ <-- SRAM3_BASE (= SRAM2_BASE + SRAM2_SIZE) 264 | | full range assigned to non-secure world or 265 * | SRAM3 64kB | to secure world, or to- Cortex-M4 exclusive access 266 * +--------------+ <-- SRAM4_BASE (= SRAM3_BASE + SRAM3_SIZE) 267 | | full range assigned to non-secure world or 268 * | SRAM4 64kB | to secure world, or to- Cortex-M4 exclusive access 269 * +--------------+ <-- SRAM4_BASE + SRAM4_SIZE 270 * 271 * If SRAMx memories are not used for the companion Cortex-M4 272 * processor, OP-TEE can use this memory. 273 * 274 * SYSRAM configuration for secure/non-secure boundaries requires the 275 * secure SYSRAM memory to start at the SYSRAM physical base address and grow 276 * from there while the non-secure SYSRAM range lies at SYSRAM end addresses 277 * with a 4KB page granule. 278 * 279 * SRAM1, SRAM2, SRAM3 and SRAM4 are independently assigned to secure world, 280 * to non-secure world or possibly to Cortex-M4 exclusive access. Each 281 * assignment covers the full related SRAMx memory range. 282 * 283 * Using non-secure SYSRAM or one of the SRAMx for SCMI message communication 284 * can be done using CFG_STM32MP1_SCMI_SHM_BASE/CFG_STM32MP1_SCMI_SHM_SIZE. 285 * This imposes related memory area is assigned to non-secure world. 286 287 * Using secure internal memories (SYSRAM and/or some SRAMx) with STM32MP15 288 * shall meet this constraints known the TZSRAM physical memory range shall 289 * be contiguous. 290 */ 291 292 #define SYSRAM_END (SYSRAM_BASE + SYSRAM_SIZE) 293 #define SYSRAM_SEC_END (SYSRAM_BASE + SYSRAM_SEC_SIZE) 294 #define SRAMS_END (SRAM4_BASE + SRAM4_SIZE) 295 #define SRAMS_START SRAM1_BASE 296 #define TZSRAM_END (CFG_TZSRAM_START + CFG_TZSRAM_SIZE) 297 298 #define SCMI_SHM_IS_IN_SRAMX ((CFG_STM32MP1_SCMI_SHM_BASE >= SRAM1_BASE) && \ 299 (CFG_STM32MP1_SCMI_SHM_BASE + \ 300 CFG_STM32MP1_SCMI_SHM_SIZE) <= SRAMS_END) 301 302 #define TZSRAM_FITS_IN_SYSRAM_SEC ((CFG_TZSRAM_START >= SYSRAM_BASE) && \ 303 (TZSRAM_END <= SYSRAM_SEC_END)) 304 305 #define TZSRAM_FITS_IN_SYSRAM_AND_SRAMS ((CFG_TZSRAM_START >= SYSRAM_BASE) && \ 306 (CFG_TZSRAM_START < SYSRAM_END) && \ 307 (TZSRAM_END > SYSRAM_END) && \ 308 (TZSRAM_END <= SRAMS_END) && \ 309 (SYSRAM_SIZE == SYSRAM_SEC_SIZE)) 310 311 #define TZSRAM_FITS_IN_SRAMS ((CFG_TZSRAM_START >= SRAMS_START) && \ 312 (CFG_TZSRAM_START < SRAMS_END) && \ 313 (TZSRAM_END <= SRAMS_END)) 314 315 #define TZSRAM_IS_IN_DRAM (CFG_TZSRAM_START >= CFG_DRAM_BASE) 316 317 #ifdef CFG_WITH_PAGER 318 /* 319 * At build time, we enforce that, when pager is used, 320 * either TZSRAM fully fits inside SYSRAM secure address range, 321 * or TZSRAM fully fits inside the full SYSRAM and spread inside SRAMx orderly, 322 * or TZSRAM fully fits some inside SRAMs address range, 323 * or TZSRAM is in DDR for debug and test purpose. 324 */ 325 static_assert(TZSRAM_FITS_IN_SYSRAM_SEC || TZSRAM_FITS_IN_SYSRAM_AND_SRAMS || 326 TZSRAM_FITS_IN_SRAMS || TZSRAM_IS_IN_DRAM); 327 #endif 328 329 #if TZSRAM_FITS_IN_SYSRAM_AND_SRAMS || TZSRAM_FITS_IN_SRAMS || \ 330 SCMI_SHM_IS_IN_SRAMX 331 /* At run time we enforce that SRAM1 to SRAM4 are properly assigned if used */ 332 static TEE_Result init_stm32mp15_secure_srams(void) 333 { 334 if (IS_ENABLED(CFG_WITH_PAGER)) { 335 if (core_is_buffer_intersect(CFG_TZSRAM_START, CFG_TZSRAM_SIZE, 336 SRAM1_BASE, SRAM1_SIZE)) 337 stm32mp_register_secure_periph_iomem(SRAM1_BASE); 338 339 if (core_is_buffer_intersect(CFG_TZSRAM_START, CFG_TZSRAM_SIZE, 340 SRAM2_BASE, SRAM2_SIZE)) 341 stm32mp_register_secure_periph_iomem(SRAM2_BASE); 342 343 if (core_is_buffer_intersect(CFG_TZSRAM_START, CFG_TZSRAM_SIZE, 344 SRAM3_BASE, SRAM3_SIZE)) 345 stm32mp_register_secure_periph_iomem(SRAM3_BASE); 346 347 if (core_is_buffer_intersect(CFG_TZSRAM_START, CFG_TZSRAM_SIZE, 348 SRAM4_BASE, SRAM4_SIZE)) 349 stm32mp_register_secure_periph_iomem(SRAM4_BASE); 350 } 351 352 if (SCMI_SHM_IS_IN_SRAMX) { 353 if (core_is_buffer_intersect(CFG_STM32MP1_SCMI_SHM_BASE, 354 CFG_STM32MP1_SCMI_SHM_SIZE, 355 SRAM1_BASE, SRAM1_SIZE)) 356 stm32mp_register_non_secure_periph_iomem(SRAM1_BASE); 357 358 if (core_is_buffer_intersect(CFG_STM32MP1_SCMI_SHM_BASE, 359 CFG_STM32MP1_SCMI_SHM_SIZE, 360 SRAM2_BASE, SRAM2_SIZE)) 361 stm32mp_register_non_secure_periph_iomem(SRAM2_BASE); 362 363 if (core_is_buffer_intersect(CFG_STM32MP1_SCMI_SHM_BASE, 364 CFG_STM32MP1_SCMI_SHM_SIZE, 365 SRAM3_BASE, SRAM3_SIZE)) 366 stm32mp_register_non_secure_periph_iomem(SRAM3_BASE); 367 368 if (core_is_buffer_intersect(CFG_STM32MP1_SCMI_SHM_BASE, 369 CFG_STM32MP1_SCMI_SHM_SIZE, 370 SRAM4_BASE, SRAM4_SIZE)) 371 stm32mp_register_non_secure_periph_iomem(SRAM4_BASE); 372 } 373 374 return TEE_SUCCESS; 375 } 376 377 service_init_late(init_stm32mp15_secure_srams); 378 #endif /* TZSRAM_FITS_IN_SYSRAM_AND_SRAMS || TZSRAM_FITS_IN_SRAMS */ 379 #endif /* CFG_STM32MP15 && CFG_TZSRAM_START */ 380 381 static TEE_Result init_stm32mp1_drivers(void) 382 { 383 /* Secure internal memories for the platform, once ETZPC is ready */ 384 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 385 etzpc_lock_tzma(0); 386 387 etzpc_configure_tzma(1, SYSRAM_SEC_SIZE >> SMALL_PAGE_SHIFT); 388 etzpc_lock_tzma(1); 389 390 if (SYSRAM_SIZE > SYSRAM_SEC_SIZE) { 391 size_t nsec_size = SYSRAM_SIZE - SYSRAM_SEC_SIZE; 392 paddr_t nsec_start = SYSRAM_BASE + SYSRAM_SEC_SIZE; 393 uint8_t *va = phys_to_virt(nsec_start, MEM_AREA_IO_NSEC, 394 nsec_size); 395 396 IMSG("Non-secure SYSRAM [%p %p]", va, va + nsec_size - 1); 397 398 /* Clear content from the non-secure part */ 399 memset(va, 0, nsec_size); 400 } 401 402 return TEE_SUCCESS; 403 } 404 405 service_init_late(init_stm32mp1_drivers); 406 407 static TEE_Result init_late_stm32mp1_drivers(void) 408 { 409 TEE_Result res = TEE_ERROR_GENERIC; 410 411 /* Set access permission to TAM backup registers */ 412 if (IS_ENABLED(CFG_STM32_TAMP)) { 413 struct stm32_bkpregs_conf conf = { 414 .nb_zone1_regs = TAMP_BKP_REGISTER_ZONE1_COUNT, 415 .nb_zone2_regs = TAMP_BKP_REGISTER_ZONE2_COUNT, 416 }; 417 418 res = stm32_tamp_set_secure_bkpregs(&conf); 419 if (res == TEE_ERROR_DEFER_DRIVER_INIT) { 420 /* TAMP driver was not probed if disabled in the DT */ 421 res = TEE_SUCCESS; 422 } 423 if (res) 424 panic(); 425 } 426 427 return TEE_SUCCESS; 428 } 429 430 driver_init_late(init_late_stm32mp1_drivers); 431 432 vaddr_t stm32_rcc_base(void) 433 { 434 static struct io_pa_va base = { .pa = RCC_BASE }; 435 436 return io_pa_or_va_secure(&base, 1); 437 } 438 439 vaddr_t get_gicd_base(void) 440 { 441 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 442 443 return io_pa_or_va_secure(&base, 1); 444 } 445 446 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 447 { 448 cfg->base = BSEC_BASE; 449 cfg->upper_start = STM32MP1_UPPER_OTP_START; 450 cfg->max_id = STM32MP1_OTP_MAX_ID; 451 } 452 453 bool __weak stm32mp_with_pmic(void) 454 { 455 return false; 456 } 457 458 uint32_t may_spin_lock(unsigned int *lock) 459 { 460 if (!lock || !cpu_mmu_enabled()) 461 return 0; 462 463 return cpu_spin_lock_xsave(lock); 464 } 465 466 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 467 { 468 if (!lock || !cpu_mmu_enabled()) 469 return; 470 471 cpu_spin_unlock_xrestore(lock, exceptions); 472 } 473 474 static vaddr_t stm32_tamp_base(void) 475 { 476 static struct io_pa_va base = { .pa = TAMP_BASE }; 477 478 return io_pa_or_va_secure(&base, 1); 479 } 480 481 static vaddr_t bkpreg_base(void) 482 { 483 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 484 } 485 486 vaddr_t stm32mp_bkpreg(unsigned int idx) 487 { 488 return bkpreg_base() + (idx * sizeof(uint32_t)); 489 } 490 491 static bool __maybe_unused bank_is_valid(unsigned int bank) 492 { 493 if (IS_ENABLED(CFG_STM32MP15)) 494 return bank == GPIO_BANK_Z || bank <= GPIO_BANK_K; 495 496 if (IS_ENABLED(CFG_STM32MP13)) 497 return bank <= GPIO_BANK_I; 498 499 panic(); 500 } 501 502 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 503 { 504 assert(bank_is_valid(bank)); 505 506 if (bank == GPIO_BANK_Z) 507 return 0; 508 509 return bank * GPIO_BANK_OFFSET; 510 } 511 512 #ifdef CFG_STM32_IWDG 513 TEE_Result stm32_get_iwdg_otp_config(paddr_t pbase, 514 struct stm32_iwdg_otp_data *otp_data) 515 { 516 unsigned int idx = 0; 517 uint32_t otp_id = 0; 518 size_t bit_len = 0; 519 uint32_t otp_value = 0; 520 521 switch (pbase) { 522 case IWDG1_BASE: 523 idx = 0; 524 break; 525 case IWDG2_BASE: 526 idx = 1; 527 break; 528 default: 529 panic(); 530 } 531 532 if (stm32_bsec_find_otp_in_nvmem_layout("hw2_otp", &otp_id, &bit_len) || 533 bit_len != 32) 534 panic(); 535 536 if (stm32_bsec_read_otp(&otp_value, otp_id)) 537 panic(); 538 539 otp_data->hw_enabled = otp_value & 540 BIT(idx + HW2_OTP_IWDG_HW_ENABLE_SHIFT); 541 otp_data->disable_on_stop = otp_value & 542 BIT(idx + HW2_OTP_IWDG_FZ_STOP_SHIFT); 543 otp_data->disable_on_standby = otp_value & 544 BIT(idx + HW2_OTP_IWDG_FZ_STANDBY_SHIFT); 545 546 return TEE_SUCCESS; 547 } 548 #endif /*CFG_STM32_IWDG*/ 549 550 #ifdef CFG_STM32_DEBUG_ACCESS 551 static TEE_Result init_debug(void) 552 { 553 TEE_Result res = TEE_SUCCESS; 554 uint32_t conf = stm32_bsec_read_debug_conf(); 555 struct clk *dbg_clk = stm32mp_rcc_clock_id_to_clk(CK_DBG); 556 uint32_t state = 0; 557 558 res = stm32_bsec_get_state(&state); 559 if (res) 560 return res; 561 562 if (state != BSEC_STATE_SEC_CLOSED && conf) { 563 if (IS_ENABLED(CFG_WARN_INSECURE)) 564 IMSG("WARNING: All debug accesses are allowed"); 565 566 res = stm32_bsec_write_debug_conf(conf | BSEC_DEBUG_ALL); 567 if (res) 568 return res; 569 570 /* 571 * Enable DBG clock as used to access coprocessor 572 * debug registers 573 */ 574 clk_enable(dbg_clk); 575 } 576 577 return TEE_SUCCESS; 578 } 579 early_init_late(init_debug); 580 #endif /* CFG_STM32_DEBUG_ACCESS */ 581