1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_etzpc.h> 11 #include <drivers/stm32_uart.h> 12 #include <drivers/stm32mp1_etzpc.h> 13 #include <dt-bindings/clock/stm32mp1-clks.h> 14 #include <kernel/generic_boot.h> 15 #include <kernel/dt.h> 16 #include <kernel/misc.h> 17 #include <kernel/panic.h> 18 #include <kernel/pm_stubs.h> 19 #include <kernel/spinlock.h> 20 #include <mm/core_memprot.h> 21 #include <platform_config.h> 22 #include <sm/psci.h> 23 #include <stm32_util.h> 24 #include <tee/entry_std.h> 25 #include <tee/entry_fast.h> 26 #include <trace.h> 27 28 #ifdef CFG_WITH_NSEC_GPIOS 29 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIOS_NSEC_BASE, GPIOS_NSEC_SIZE); 30 #endif 31 #ifdef CFG_WITH_NSEC_UARTS 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 40 #endif 41 42 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BSEC_BASE, SMALL_PAGE_SIZE); 43 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ETZPC_BASE, SMALL_PAGE_SIZE); 44 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 45 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GPIOZ_BASE, SMALL_PAGE_SIZE); 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG1_BASE, SMALL_PAGE_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 51 52 static void main_fiq(void); 53 54 static const struct thread_handlers handlers = { 55 .std_smc = tee_entry_std, 56 .fast_smc = tee_entry_fast, 57 .nintr = main_fiq, 58 .cpu_on = pm_panic, 59 .cpu_off = pm_panic, 60 .cpu_suspend = pm_panic, 61 .cpu_resume = pm_panic, 62 .system_off = pm_panic, 63 .system_reset = pm_panic, 64 }; 65 66 const struct thread_handlers *generic_boot_get_handlers(void) 67 { 68 return &handlers; 69 } 70 71 #define _ID2STR(id) (#id) 72 #define ID2STR(id) _ID2STR(id) 73 74 static TEE_Result platform_banner(void) 75 { 76 #ifdef CFG_EMBED_DTB 77 IMSG("Platform stm32mp1: flavor %s - DT %s", 78 ID2STR(PLATFORM_FLAVOR), 79 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 80 #else 81 IMSG("Platform stm32mp1: flavor %s - no device tree", 82 ID2STR(PLATFORM_FLAVOR)); 83 #endif 84 85 return TEE_SUCCESS; 86 } 87 service_init(platform_banner); 88 89 /* 90 * Console 91 * 92 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 93 * trace console. Value 0 disables the early console. 94 * 95 * We cannot use the generic serial_console support since probing 96 * the console requires the platform clock driver to be already 97 * up and ready which is done only once service_init are completed. 98 */ 99 static struct stm32_uart_pdata console_data; 100 101 void console_init(void) 102 { 103 /* Early console initialization before MMU setup */ 104 struct uart { 105 paddr_t pa; 106 bool secure; 107 } uarts[] = { 108 [0] = { .pa = 0 }, 109 [1] = { .pa = USART1_BASE, .secure = true, }, 110 [2] = { .pa = USART2_BASE, .secure = false, }, 111 [3] = { .pa = USART3_BASE, .secure = false, }, 112 [4] = { .pa = UART4_BASE, .secure = false, }, 113 [5] = { .pa = UART5_BASE, .secure = false, }, 114 [6] = { .pa = USART6_BASE, .secure = false, }, 115 [7] = { .pa = UART7_BASE, .secure = false, }, 116 [8] = { .pa = UART8_BASE, .secure = false, }, 117 }; 118 119 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 120 assert(!cpu_mmu_enabled()); 121 122 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 123 return; 124 125 /* No clock yet bound to the UART console */ 126 console_data.clock = DT_INFO_INVALID_CLOCK; 127 128 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 129 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 130 131 register_serial_console(&console_data.chip); 132 133 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 134 } 135 136 #ifdef CFG_DT 137 static TEE_Result init_console_from_dt(void) 138 { 139 struct stm32_uart_pdata *pd = NULL; 140 void *fdt = NULL; 141 int node = 0; 142 143 if (get_console_node_from_dt(&fdt, &node, NULL, NULL)) 144 return TEE_SUCCESS; 145 146 pd = stm32_uart_init_from_dt_node(fdt, node); 147 if (!pd) { 148 IMSG("DTB disables console"); 149 register_serial_console(NULL); 150 return TEE_SUCCESS; 151 } 152 153 /* Replace early console with the new one */ 154 console_flush(); 155 console_data = *pd; 156 free(pd); 157 register_serial_console(&console_data.chip); 158 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 159 160 return TEE_SUCCESS; 161 } 162 163 /* Probe console from DT once clock inits (service init level) are completed */ 164 service_init_late(init_console_from_dt); 165 #endif 166 167 /* 168 * GIC init, used also for primary/secondary boot core wake completion 169 */ 170 static struct gic_data gic_data; 171 172 static void main_fiq(void) 173 { 174 gic_it_handle(&gic_data); 175 } 176 177 void main_init_gic(void) 178 { 179 assert(cpu_mmu_enabled()); 180 181 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 182 itr_init(&gic_data.chip); 183 184 stm32mp_register_online_cpu(); 185 } 186 187 void main_secondary_init_gic(void) 188 { 189 gic_cpu_init(&gic_data); 190 191 stm32mp_register_online_cpu(); 192 } 193 194 #ifndef CFG_EMBED_DTB 195 static TEE_Result init_stm32mp1_drivers(void) 196 { 197 /* Without secure DTB support, some drivers must be inited */ 198 stm32_etzpc_init(ETZPC_BASE); 199 200 return TEE_SUCCESS; 201 } 202 driver_init(init_stm32mp1_drivers); 203 #endif /*!CFG_EMBED_DTB*/ 204 205 /* Platform initializations once all drivers are ready */ 206 static TEE_Result init_late_stm32mp1_drivers(void) 207 { 208 /* Secure internal memories for the platform, once ETZPC is ready */ 209 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 210 etzpc_lock_tzma(0); 211 etzpc_configure_tzma(1, ETZPC_TZMA_ALL_SECURE); 212 etzpc_lock_tzma(1); 213 214 /* Static secure DECPROT configuration */ 215 etzpc_configure_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); 216 etzpc_configure_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); 217 etzpc_configure_decprot(STM32MP1_ETZPC_IWDG1_ID, ETZPC_DECPROT_S_RW); 218 etzpc_configure_decprot(STM32MP1_ETZPC_DDRCTRL_ID, ETZPC_DECPROT_S_RW); 219 etzpc_configure_decprot(STM32MP1_ETZPC_DDRPHYC_ID, ETZPC_DECPROT_S_RW); 220 etzpc_lock_decprot(STM32MP1_ETZPC_STGENC_ID); 221 etzpc_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID); 222 etzpc_lock_decprot(STM32MP1_ETZPC_IWDG1_ID); 223 etzpc_lock_decprot(STM32MP1_ETZPC_DDRCTRL_ID); 224 etzpc_lock_decprot(STM32MP1_ETZPC_DDRPHYC_ID); 225 /* Static non-secure DECPROT configuration */ 226 etzpc_configure_decprot(STM32MP1_ETZPC_I2C4_ID, ETZPC_DECPROT_NS_RW); 227 etzpc_configure_decprot(STM32MP1_ETZPC_RNG1_ID, ETZPC_DECPROT_NS_RW); 228 etzpc_configure_decprot(STM32MP1_ETZPC_HASH1_ID, ETZPC_DECPROT_NS_RW); 229 etzpc_configure_decprot(STM32MP1_ETZPC_CRYP1_ID, ETZPC_DECPROT_NS_RW); 230 /* Release few resource to the non-secure world */ 231 etzpc_configure_decprot(STM32MP1_ETZPC_USART1_ID, ETZPC_DECPROT_NS_RW); 232 etzpc_configure_decprot(STM32MP1_ETZPC_SPI6_ID, ETZPC_DECPROT_NS_RW); 233 etzpc_configure_decprot(STM32MP1_ETZPC_I2C6_ID, ETZPC_DECPROT_NS_RW); 234 235 return TEE_SUCCESS; 236 } 237 driver_init_late(init_late_stm32mp1_drivers); 238 239 vaddr_t get_gicc_base(void) 240 { 241 struct io_pa_va base = { .pa = GIC_BASE + GICC_OFFSET }; 242 243 return io_pa_or_va(&base); 244 } 245 246 vaddr_t get_gicd_base(void) 247 { 248 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 249 250 return io_pa_or_va(&base); 251 } 252 253 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 254 { 255 cfg->base = BSEC_BASE; 256 cfg->upper_start = STM32MP1_UPPER_OTP_START; 257 cfg->max_id = STM32MP1_OTP_MAX_ID; 258 cfg->closed_device_id = DATA0_OTP; 259 cfg->closed_device_position = DATA0_OTP_SECURED_POS; 260 } 261 262 uint32_t may_spin_lock(unsigned int *lock) 263 { 264 if (!lock || !cpu_mmu_enabled()) 265 return 0; 266 267 return cpu_spin_lock_xsave(lock); 268 } 269 270 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 271 { 272 if (!lock || !cpu_mmu_enabled()) 273 return; 274 275 cpu_spin_unlock_xrestore(lock, exceptions); 276 } 277 278 static vaddr_t stm32_tamp_base(void) 279 { 280 static struct io_pa_va base = { .pa = TAMP_BASE }; 281 282 return io_pa_or_va(&base); 283 } 284 285 static vaddr_t bkpreg_base(void) 286 { 287 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 288 } 289 290 vaddr_t stm32mp_bkpreg(unsigned int idx) 291 { 292 return bkpreg_base() + (idx * sizeof(uint32_t)); 293 } 294 295 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 296 { 297 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 298 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 299 300 if (bank == GPIO_BANK_Z) 301 return io_pa_or_va(&gpioz_base); 302 303 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 304 assert(bank <= GPIO_BANK_K); 305 306 return io_pa_or_va(&gpios_nsec_base) + (bank * GPIO_BANK_OFFSET); 307 } 308 309 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 310 { 311 if (bank == GPIO_BANK_Z) 312 return 0; 313 314 assert(bank <= GPIO_BANK_K); 315 return bank * GPIO_BANK_OFFSET; 316 } 317 318 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 319 { 320 if (bank == GPIO_BANK_Z) 321 return GPIOZ; 322 323 assert(bank <= GPIO_BANK_K); 324 return GPIOA + bank; 325 } 326