1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/stm32_etzpc.h> 12 #include <drivers/stm32mp1_etzpc.h> 13 #include <drivers/stm32_uart.h> 14 #include <dt-bindings/clock/stm32mp1-clks.h> 15 #include <kernel/boot.h> 16 #include <kernel/dt.h> 17 #include <kernel/interrupt.h> 18 #include <kernel/misc.h> 19 #include <kernel/panic.h> 20 #include <kernel/spinlock.h> 21 #include <mm/core_memprot.h> 22 #include <platform_config.h> 23 #include <sm/psci.h> 24 #include <stm32_util.h> 25 #include <trace.h> 26 27 #ifdef CFG_WITH_NSEC_GPIOS 28 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIOS_NSEC_BASE, GPIOS_NSEC_SIZE); 29 #endif 30 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C4_BASE, SMALL_PAGE_SIZE); 31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C6_BASE, SMALL_PAGE_SIZE); 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, RNG1_BASE, SMALL_PAGE_SIZE); 33 #ifdef CFG_WITH_NSEC_UARTS 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 42 #endif 43 44 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BSEC_BASE, SMALL_PAGE_SIZE); 45 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ETZPC_BASE, SMALL_PAGE_SIZE); 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GPIOZ_BASE, SMALL_PAGE_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C4_BASE, SMALL_PAGE_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C6_BASE, SMALL_PAGE_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG1_BASE, SMALL_PAGE_SIZE); 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SYSCFG_BASE, SMALL_PAGE_SIZE); 54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC_BASE, SMALL_PAGE_SIZE); 56 register_phys_mem_pgdir(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 57 58 #if DDR_BASE < CFG_TZDRAM_START 59 register_dynamic_shm(DDR_BASE, CFG_TZDRAM_START - DDR_BASE); 60 #endif 61 62 #define DRAM_END (DDR_BASE + CFG_DRAM_SIZE) 63 #define TZDRAM_END (CFG_TZDRAM_START + CFG_TZDRAM_SIZE) 64 65 #if DRAM_END > TZDRAM_END 66 register_dynamic_shm(TZDRAM_END, DRAM_END - TZDRAM_END); 67 #endif 68 69 #define _ID2STR(id) (#id) 70 #define ID2STR(id) _ID2STR(id) 71 72 static TEE_Result platform_banner(void) 73 { 74 #ifdef CFG_EMBED_DTB 75 IMSG("Platform stm32mp1: flavor %s - DT %s", 76 ID2STR(PLATFORM_FLAVOR), 77 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 78 #else 79 IMSG("Platform stm32mp1: flavor %s - no device tree", 80 ID2STR(PLATFORM_FLAVOR)); 81 #endif 82 83 return TEE_SUCCESS; 84 } 85 service_init(platform_banner); 86 87 /* 88 * Console 89 * 90 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 91 * trace console. Value 0 disables the early console. 92 * 93 * We cannot use the generic serial_console support since probing 94 * the console requires the platform clock driver to be already 95 * up and ready which is done only once service_init are completed. 96 */ 97 static struct stm32_uart_pdata console_data; 98 99 void console_init(void) 100 { 101 /* Early console initialization before MMU setup */ 102 struct uart { 103 paddr_t pa; 104 bool secure; 105 } uarts[] = { 106 [0] = { .pa = 0 }, 107 [1] = { .pa = USART1_BASE, .secure = true, }, 108 [2] = { .pa = USART2_BASE, .secure = false, }, 109 [3] = { .pa = USART3_BASE, .secure = false, }, 110 [4] = { .pa = UART4_BASE, .secure = false, }, 111 [5] = { .pa = UART5_BASE, .secure = false, }, 112 [6] = { .pa = USART6_BASE, .secure = false, }, 113 [7] = { .pa = UART7_BASE, .secure = false, }, 114 [8] = { .pa = UART8_BASE, .secure = false, }, 115 }; 116 117 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 118 119 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 120 return; 121 122 /* No clock yet bound to the UART console */ 123 console_data.clock = DT_INFO_INVALID_CLOCK; 124 125 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 126 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 127 128 register_serial_console(&console_data.chip); 129 130 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 131 } 132 133 #ifdef CFG_DT 134 static TEE_Result init_console_from_dt(void) 135 { 136 struct stm32_uart_pdata *pd = NULL; 137 void *fdt = NULL; 138 int node = 0; 139 TEE_Result res = TEE_ERROR_GENERIC; 140 141 fdt = get_embedded_dt(); 142 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 143 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 144 fdt = get_external_dt(); 145 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 146 if (res == TEE_ERROR_ITEM_NOT_FOUND) 147 return TEE_SUCCESS; 148 if (res != TEE_SUCCESS) 149 return res; 150 } 151 152 pd = stm32_uart_init_from_dt_node(fdt, node); 153 if (!pd) { 154 IMSG("DTB disables console"); 155 register_serial_console(NULL); 156 return TEE_SUCCESS; 157 } 158 159 /* Replace early console with the new one */ 160 console_flush(); 161 console_data = *pd; 162 free(pd); 163 register_serial_console(&console_data.chip); 164 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 165 166 return TEE_SUCCESS; 167 } 168 169 /* Probe console from DT once clock inits (service init level) are completed */ 170 service_init_late(init_console_from_dt); 171 #endif 172 173 /* 174 * GIC init, used also for primary/secondary boot core wake completion 175 */ 176 static struct gic_data gic_data; 177 178 void itr_core_handler(void) 179 { 180 gic_it_handle(&gic_data); 181 } 182 183 void main_init_gic(void) 184 { 185 assert(cpu_mmu_enabled()); 186 187 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 188 itr_init(&gic_data.chip); 189 190 stm32mp_register_online_cpu(); 191 } 192 193 void main_secondary_init_gic(void) 194 { 195 gic_cpu_init(&gic_data); 196 197 stm32mp_register_online_cpu(); 198 } 199 200 static TEE_Result init_stm32mp1_drivers(void) 201 { 202 /* Without secure DTB support, some drivers must be inited */ 203 if (!IS_ENABLED(CFG_EMBED_DTB)) 204 stm32_etzpc_init(ETZPC_BASE); 205 206 /* Secure internal memories for the platform, once ETZPC is ready */ 207 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 208 etzpc_lock_tzma(0); 209 210 COMPILE_TIME_ASSERT(((SYSRAM_BASE + SYSRAM_SIZE) <= CFG_TZSRAM_START) || 211 ((SYSRAM_BASE <= CFG_TZSRAM_START) && 212 (SYSRAM_SEC_SIZE >= CFG_TZSRAM_SIZE))); 213 214 etzpc_configure_tzma(1, SYSRAM_SEC_SIZE >> SMALL_PAGE_SHIFT); 215 etzpc_lock_tzma(1); 216 217 return TEE_SUCCESS; 218 } 219 service_init_late(init_stm32mp1_drivers); 220 221 vaddr_t get_gicc_base(void) 222 { 223 struct io_pa_va base = { .pa = GIC_BASE + GICC_OFFSET }; 224 225 return io_pa_or_va_secure(&base); 226 } 227 228 vaddr_t get_gicd_base(void) 229 { 230 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 231 232 return io_pa_or_va_secure(&base); 233 } 234 235 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 236 { 237 cfg->base = BSEC_BASE; 238 cfg->upper_start = STM32MP1_UPPER_OTP_START; 239 cfg->max_id = STM32MP1_OTP_MAX_ID; 240 } 241 242 bool stm32mp_is_closed_device(void) 243 { 244 uint32_t otp = 0; 245 TEE_Result result = TEE_ERROR_GENERIC; 246 247 /* Non closed_device platform expects fuse well programmed to 0 */ 248 result = stm32_bsec_shadow_read_otp(&otp, DATA0_OTP); 249 if (!result && !(otp & BIT(DATA0_OTP_SECURED_POS))) 250 return false; 251 252 return true; 253 } 254 255 bool __weak stm32mp_with_pmic(void) 256 { 257 return false; 258 } 259 260 uint32_t may_spin_lock(unsigned int *lock) 261 { 262 if (!lock || !cpu_mmu_enabled()) 263 return 0; 264 265 return cpu_spin_lock_xsave(lock); 266 } 267 268 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 269 { 270 if (!lock || !cpu_mmu_enabled()) 271 return; 272 273 cpu_spin_unlock_xrestore(lock, exceptions); 274 } 275 276 static vaddr_t stm32_tamp_base(void) 277 { 278 static struct io_pa_va base = { .pa = TAMP_BASE }; 279 280 return io_pa_or_va_secure(&base); 281 } 282 283 static vaddr_t bkpreg_base(void) 284 { 285 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 286 } 287 288 vaddr_t stm32mp_bkpreg(unsigned int idx) 289 { 290 return bkpreg_base() + (idx * sizeof(uint32_t)); 291 } 292 293 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 294 { 295 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 296 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 297 298 /* Get secure mapping address for GPIOZ */ 299 if (bank == GPIO_BANK_Z) 300 return io_pa_or_va_secure(&gpioz_base); 301 302 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 303 assert(bank <= GPIO_BANK_K); 304 305 return io_pa_or_va_nsec(&gpios_nsec_base) + (bank * GPIO_BANK_OFFSET); 306 } 307 308 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 309 { 310 if (bank == GPIO_BANK_Z) 311 return 0; 312 313 assert(bank <= GPIO_BANK_K); 314 return bank * GPIO_BANK_OFFSET; 315 } 316 317 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 318 { 319 if (bank == GPIO_BANK_Z) 320 return GPIOZ; 321 322 assert(bank <= GPIO_BANK_K); 323 return GPIOA + bank; 324 } 325