1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_etzpc.h> 11 #include <drivers/stm32_uart.h> 12 #include <drivers/stm32mp1_etzpc.h> 13 #include <dt-bindings/clock/stm32mp1-clks.h> 14 #include <kernel/generic_boot.h> 15 #include <kernel/dt.h> 16 #include <kernel/misc.h> 17 #include <kernel/panic.h> 18 #include <kernel/pm_stubs.h> 19 #include <kernel/spinlock.h> 20 #include <mm/core_memprot.h> 21 #include <platform_config.h> 22 #include <sm/psci.h> 23 #include <stm32_util.h> 24 #include <tee/entry_std.h> 25 #include <tee/entry_fast.h> 26 #include <trace.h> 27 28 #ifdef CFG_WITH_NSEC_GPIOS 29 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIOS_NSEC_BASE, GPIOS_NSEC_SIZE); 30 #endif 31 #ifdef CFG_WITH_NSEC_UARTS 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 40 #endif 41 42 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ETZPC_BASE, SMALL_PAGE_SIZE); 43 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 44 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GPIOZ_BASE, SMALL_PAGE_SIZE); 45 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 49 50 static void main_fiq(void); 51 52 static const struct thread_handlers handlers = { 53 .std_smc = tee_entry_std, 54 .fast_smc = tee_entry_fast, 55 .nintr = main_fiq, 56 .cpu_on = pm_panic, 57 .cpu_off = pm_panic, 58 .cpu_suspend = pm_panic, 59 .cpu_resume = pm_panic, 60 .system_off = pm_panic, 61 .system_reset = pm_panic, 62 }; 63 64 const struct thread_handlers *generic_boot_get_handlers(void) 65 { 66 return &handlers; 67 } 68 69 #define _ID2STR(id) (#id) 70 #define ID2STR(id) _ID2STR(id) 71 72 static TEE_Result platform_banner(void) 73 { 74 #ifdef CFG_EMBED_DTB 75 IMSG("Platform stm32mp1: flavor %s - DT %s", 76 ID2STR(PLATFORM_FLAVOR), 77 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 78 #else 79 IMSG("Platform stm32mp1: flavor %s - no device tree", 80 ID2STR(PLATFORM_FLAVOR)); 81 #endif 82 83 return TEE_SUCCESS; 84 } 85 service_init(platform_banner); 86 87 /* 88 * Console 89 * 90 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 91 * trace console. Value 0 disables the early console. 92 * 93 * We cannot use the generic serial_console support since probing 94 * the console requires the platform clock driver to be already 95 * up and ready which is done only once service_init are completed. 96 */ 97 static struct stm32_uart_pdata console_data; 98 99 void console_init(void) 100 { 101 /* Early console initialization before MMU setup */ 102 struct uart { 103 uintptr_t pa; 104 bool secure; 105 } uarts[] = { 106 [0] = { .pa = 0 }, 107 [1] = { .pa = USART1_BASE, .secure = true, }, 108 [2] = { .pa = USART2_BASE, .secure = false, }, 109 [3] = { .pa = USART3_BASE, .secure = false, }, 110 [4] = { .pa = UART4_BASE, .secure = false, }, 111 [5] = { .pa = UART5_BASE, .secure = false, }, 112 [6] = { .pa = USART6_BASE, .secure = false, }, 113 [7] = { .pa = UART7_BASE, .secure = false, }, 114 [8] = { .pa = UART8_BASE, .secure = false, }, 115 }; 116 117 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 118 assert(!cpu_mmu_enabled()); 119 120 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 121 return; 122 123 /* No clock yet bound to the UART console */ 124 console_data.clock = DT_INFO_INVALID_CLOCK; 125 126 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 127 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 128 129 register_serial_console(&console_data.chip); 130 131 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 132 } 133 134 #ifdef CFG_DT 135 static TEE_Result init_console_from_dt(void) 136 { 137 struct stm32_uart_pdata *pd; 138 void *fdt; 139 int node; 140 141 if (get_console_node_from_dt(&fdt, &node, NULL, NULL)) 142 return TEE_SUCCESS; 143 144 pd = stm32_uart_init_from_dt_node(fdt, node); 145 if (!pd) { 146 IMSG("DTB disables console"); 147 register_serial_console(NULL); 148 return TEE_SUCCESS; 149 } 150 151 /* Replace early console with the new one */ 152 console_flush(); 153 console_data = *pd; 154 free(pd); 155 register_serial_console(&console_data.chip); 156 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 157 158 return TEE_SUCCESS; 159 } 160 161 /* Probe console from DT once clock inits (service init level) are completed */ 162 service_init_late(init_console_from_dt); 163 #endif 164 165 /* 166 * GIC init, used also for primary/secondary boot core wake completion 167 */ 168 static struct gic_data gic_data; 169 170 static void main_fiq(void) 171 { 172 gic_it_handle(&gic_data); 173 } 174 175 void main_init_gic(void) 176 { 177 assert(cpu_mmu_enabled()); 178 179 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 180 itr_init(&gic_data.chip); 181 182 stm32mp_register_online_cpu(); 183 } 184 185 void main_secondary_init_gic(void) 186 { 187 gic_cpu_init(&gic_data); 188 189 stm32mp_register_online_cpu(); 190 } 191 192 #ifndef CFG_EMBED_DTB 193 static TEE_Result init_stm32mp1_drivers(void) 194 { 195 /* Without secure DTB support, some drivers must be inited */ 196 stm32_etzpc_init(ETZPC_BASE); 197 198 return TEE_SUCCESS; 199 } 200 driver_init(init_stm32mp1_drivers); 201 #endif /*!CFG_EMBED_DTB*/ 202 203 /* Platform initializations once all drivers are ready */ 204 static TEE_Result init_late_stm32mp1_drivers(void) 205 { 206 /* Secure internal memories for the platform, once ETZPC is ready */ 207 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 208 etzpc_lock_tzma(0); 209 etzpc_configure_tzma(1, ETZPC_TZMA_ALL_SECURE); 210 etzpc_lock_tzma(1); 211 212 /* Static secure DECPROT configuration */ 213 etzpc_configure_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); 214 etzpc_configure_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); 215 etzpc_configure_decprot(STM32MP1_ETZPC_IWDG1_ID, ETZPC_DECPROT_S_RW); 216 etzpc_configure_decprot(STM32MP1_ETZPC_DDRCTRL_ID, ETZPC_DECPROT_S_RW); 217 etzpc_configure_decprot(STM32MP1_ETZPC_DDRPHYC_ID, ETZPC_DECPROT_S_RW); 218 etzpc_lock_decprot(STM32MP1_ETZPC_STGENC_ID); 219 etzpc_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID); 220 etzpc_lock_decprot(STM32MP1_ETZPC_IWDG1_ID); 221 etzpc_lock_decprot(STM32MP1_ETZPC_DDRCTRL_ID); 222 etzpc_lock_decprot(STM32MP1_ETZPC_DDRPHYC_ID); 223 /* Static non-secure DECPROT configuration */ 224 etzpc_configure_decprot(STM32MP1_ETZPC_I2C4_ID, ETZPC_DECPROT_NS_RW); 225 etzpc_configure_decprot(STM32MP1_ETZPC_RNG1_ID, ETZPC_DECPROT_NS_RW); 226 etzpc_configure_decprot(STM32MP1_ETZPC_HASH1_ID, ETZPC_DECPROT_NS_RW); 227 etzpc_configure_decprot(STM32MP1_ETZPC_CRYP1_ID, ETZPC_DECPROT_NS_RW); 228 /* Release few resource to the non-secure world */ 229 etzpc_configure_decprot(STM32MP1_ETZPC_USART1_ID, ETZPC_DECPROT_NS_RW); 230 etzpc_configure_decprot(STM32MP1_ETZPC_SPI6_ID, ETZPC_DECPROT_NS_RW); 231 etzpc_configure_decprot(STM32MP1_ETZPC_I2C6_ID, ETZPC_DECPROT_NS_RW); 232 233 return TEE_SUCCESS; 234 } 235 driver_init_late(init_late_stm32mp1_drivers); 236 237 uintptr_t get_gicc_base(void) 238 { 239 uintptr_t pbase = GIC_BASE + GICC_OFFSET; 240 241 if (cpu_mmu_enabled()) 242 return (uintptr_t)phys_to_virt_io(pbase); 243 244 return pbase; 245 } 246 247 uintptr_t get_gicd_base(void) 248 { 249 uintptr_t pbase = GIC_BASE + GICD_OFFSET; 250 251 if (cpu_mmu_enabled()) 252 return (uintptr_t)phys_to_virt_io(pbase); 253 254 return pbase; 255 } 256 257 uint32_t may_spin_lock(unsigned int *lock) 258 { 259 if (!lock || !cpu_mmu_enabled()) 260 return 0; 261 262 return cpu_spin_lock_xsave(lock); 263 } 264 265 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 266 { 267 if (!lock || !cpu_mmu_enabled()) 268 return; 269 270 cpu_spin_unlock_xrestore(lock, exceptions); 271 } 272 273 static uintptr_t stm32_tamp_base(void) 274 { 275 static struct io_pa_va base = { .pa = TAMP_BASE }; 276 277 return io_pa_or_va(&base); 278 } 279 280 static uintptr_t bkpreg_base(void) 281 { 282 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 283 } 284 285 uintptr_t stm32mp_bkpreg(unsigned int idx) 286 { 287 return bkpreg_base() + (idx * sizeof(uint32_t)); 288 } 289 290 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 291 { 292 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 293 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 294 295 if (bank == GPIO_BANK_Z) 296 return io_pa_or_va(&gpioz_base); 297 298 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 299 assert(bank <= GPIO_BANK_K); 300 301 return io_pa_or_va(&gpios_nsec_base) + (bank * GPIO_BANK_OFFSET); 302 } 303 304 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 305 { 306 if (bank == GPIO_BANK_Z) 307 return 0; 308 309 assert(bank <= GPIO_BANK_K); 310 return bank * GPIO_BANK_OFFSET; 311 } 312 313 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 314 { 315 if (bank == GPIO_BANK_Z) 316 return GPIOZ; 317 318 assert(bank <= GPIO_BANK_K); 319 return GPIOA + bank; 320 } 321