1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_uart.h> 11 #include <kernel/generic_boot.h> 12 #include <kernel/dt.h> 13 #include <kernel/misc.h> 14 #include <kernel/panic.h> 15 #include <kernel/pm_stubs.h> 16 #include <kernel/spinlock.h> 17 #include <mm/core_memprot.h> 18 #include <platform_config.h> 19 #include <sm/psci.h> 20 #include <stm32_util.h> 21 #include <tee/entry_std.h> 22 #include <tee/entry_fast.h> 23 #include <trace.h> 24 25 #ifdef CFG_WITH_NSEC_UARTS 26 register_phys_mem(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 27 register_phys_mem(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 28 register_phys_mem(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 29 register_phys_mem(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 30 register_phys_mem(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 31 register_phys_mem(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 32 register_phys_mem(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 33 register_phys_mem(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 34 #endif 35 36 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 37 register_phys_mem(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 40 41 static void main_fiq(void); 42 43 static const struct thread_handlers handlers = { 44 .std_smc = tee_entry_std, 45 .fast_smc = tee_entry_fast, 46 .nintr = main_fiq, 47 .cpu_on = pm_panic, 48 .cpu_off = pm_panic, 49 .cpu_suspend = pm_panic, 50 .cpu_resume = pm_panic, 51 .system_off = pm_panic, 52 .system_reset = pm_panic, 53 }; 54 55 const struct thread_handlers *generic_boot_get_handlers(void) 56 { 57 return &handlers; 58 } 59 60 #define _ID2STR(id) (#id) 61 #define ID2STR(id) _ID2STR(id) 62 63 static TEE_Result platform_banner(void) 64 { 65 #ifdef CFG_EMBED_DTB 66 IMSG("Platform stm32mp1: flavor %s - DT %s", 67 ID2STR(PLATFORM_FLAVOR), 68 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 69 #else 70 IMSG("Platform stm32mp1: flavor %s - no device tree", 71 ID2STR(PLATFORM_FLAVOR)); 72 #endif 73 74 return TEE_SUCCESS; 75 } 76 service_init(platform_banner); 77 78 /* 79 * Console 80 * 81 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 82 * trace console. Value 0 disables the early console. 83 * 84 * We cannot use the generic serial_console support since probing 85 * the console requires the platform clock driver to be already 86 * up and ready which is done only once service_init are completed. 87 */ 88 static struct stm32_uart_pdata console_data; 89 90 void console_init(void) 91 { 92 /* Early console initialization before MMU setup */ 93 struct uart { 94 uintptr_t pa; 95 bool secure; 96 } uarts[] = { 97 [0] = { .pa = 0 }, 98 [1] = { .pa = USART1_BASE, .secure = true, }, 99 [2] = { .pa = USART2_BASE, .secure = false, }, 100 [3] = { .pa = USART3_BASE, .secure = false, }, 101 [4] = { .pa = UART4_BASE, .secure = false, }, 102 [5] = { .pa = UART5_BASE, .secure = false, }, 103 [6] = { .pa = USART6_BASE, .secure = false, }, 104 [7] = { .pa = UART7_BASE, .secure = false, }, 105 [8] = { .pa = UART8_BASE, .secure = false, }, 106 }; 107 108 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 109 assert(!cpu_mmu_enabled()); 110 111 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 112 return; 113 114 /* No clock yet bound to the UART console */ 115 console_data.clock = DT_INFO_INVALID_CLOCK; 116 117 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 118 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 119 120 register_serial_console(&console_data.chip); 121 122 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 123 } 124 125 #ifdef CFG_DT 126 static TEE_Result init_console_from_dt(void) 127 { 128 struct stm32_uart_pdata *pd; 129 void *fdt; 130 int node; 131 132 if (get_console_node_from_dt(&fdt, &node, NULL, NULL)) 133 return TEE_SUCCESS; 134 135 pd = stm32_uart_init_from_dt_node(fdt, node); 136 if (!pd) { 137 IMSG("DTB disables console"); 138 register_serial_console(NULL); 139 return TEE_SUCCESS; 140 } 141 142 /* Replace early console with the new one */ 143 console_flush(); 144 console_data = *pd; 145 free(pd); 146 register_serial_console(&console_data.chip); 147 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 148 149 return TEE_SUCCESS; 150 } 151 152 /* Probe console from DT once clock inits (service init level) are completed */ 153 service_init_late(init_console_from_dt); 154 #endif 155 156 /* 157 * GIC init, used also for primary/secondary boot core wake completion 158 */ 159 static struct gic_data gic_data; 160 161 static void main_fiq(void) 162 { 163 gic_it_handle(&gic_data); 164 } 165 166 void main_init_gic(void) 167 { 168 assert(cpu_mmu_enabled()); 169 170 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 171 itr_init(&gic_data.chip); 172 173 stm32mp_register_online_cpu(); 174 } 175 176 void main_secondary_init_gic(void) 177 { 178 gic_cpu_init(&gic_data); 179 180 stm32mp_register_online_cpu(); 181 } 182 183 uintptr_t get_gicc_base(void) 184 { 185 uintptr_t pbase = GIC_BASE + GICC_OFFSET; 186 187 if (cpu_mmu_enabled()) 188 return (uintptr_t)phys_to_virt_io(pbase); 189 190 return pbase; 191 } 192 193 uintptr_t get_gicd_base(void) 194 { 195 uintptr_t pbase = GIC_BASE + GICD_OFFSET; 196 197 if (cpu_mmu_enabled()) 198 return (uintptr_t)phys_to_virt_io(pbase); 199 200 return pbase; 201 } 202 203 uint32_t may_spin_lock(unsigned int *lock) 204 { 205 if (!lock || !cpu_mmu_enabled()) 206 return 0; 207 208 return cpu_spin_lock_xsave(lock); 209 } 210 211 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 212 { 213 if (!lock || !cpu_mmu_enabled()) 214 return; 215 216 cpu_spin_unlock_xrestore(lock, exceptions); 217 } 218 219 static uintptr_t stm32_tamp_base(void) 220 { 221 static struct io_pa_va base = { .pa = TAMP_BASE }; 222 223 return io_pa_or_va(&base); 224 } 225 226 static uintptr_t bkpreg_base(void) 227 { 228 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 229 } 230 231 uintptr_t stm32mp_bkpreg(unsigned int idx) 232 { 233 return bkpreg_base() + (idx * sizeof(uint32_t)); 234 } 235